THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 D D D D D D D D D D D Member of the Pin-Compatible CommsDAC Product Family 100 MSPS Update Rate 12-Bit Resolution Spurious Free Dynamic Range (SFDR) to Nyquist at 20 MHz Output: 63 dBc 1 ns Setup/Hold Time Differential Scalable Current Outputs: 2 mA to 20 mA On-Chip 1.2 V Reference 3 V and 5 V CMOS-Compatible Digital Interface Straight Binary or Twos Complement Input Power Dissipation: 175 mW at 5 V, Sleep Mode: 25 mW at 5 V Package: 28-Pin SOIC and TSSOP SOIC (DW) OR TSSOP (PW) PACKAGE (TOP VIEW) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CLK DVDD DGND MODE AVDD COMP2 IOUT1 IOUT2 AGND COMP1 BIASJ EXTIO EXTLO SLEEP NC – No internal connection description The THS5661 is a 12-bit resolution digital-to-analog converter (DAC) specifically optimized for digital data transmission in wired and wireless communication systems. The 12-bit DAC is a member of the CommsDAC series of high-speed, low-power CMOS digital-to-analog converters. The CommsDAC family consists of pin compatible 14-, 12-, 10-, and 8-bit DACs. All devices offer identical interface options, small outline package, and pinout. The THS5661 offers superior ac and dc performance while supporting update rates up to 100 MSPS. The THS5661 operates from an analog supply of 4.5 V to 5.5 V. Its inherent low power dissipation of 175 mW ensures that the device is well-suited for portable and low-power applications. Lowering the full-scale current output reduces the power dissipation without significantly degrading performance. The device features a SLEEP mode, which reduces the standby power to approximately 25 mW, thereby optimizing the power consumption for system needs. The THS5661 is manufactured in Texas Instruments advanced high-speed mixed-signal CMOS process. A current-source-array architecture combined with simultaneous switching shows excellent dynamic performance. On-chip edge-triggered input latches and a 1.2 V temperature-compensated bandgap reference provide a complete monolithic DAC solution. The digital supply range of 3 V to 5.5 V supports 3 V and 5 V CMOS logic families. Minimum data input setup and hold times allow for easy interfacing with external logic. The THS5661 supports both a straight binary and twos complement input word format, enabling flexible interfacing with digital signal processors. The THS5661 provides a nominal full-scale differential output current of 20 mA and >300 kΩ output impedance, supporting both single-ended and differential applications. The output current can be directly fed to the load (e.g., external resistor load or transformer), with no additional external output buffer required. An accurate on-chip reference and control amplifier allows the user to adjust this output current from 20 mA down to 2 mA, with no significant degradation of performance. This reduces power consumption and provides 20 dB gain range control capabilities. Alternatively, an external reference voltage and control amplifier may be applied in applications using a multiplying DAC. The output voltage compliance range is 1.25 V. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. CommsDAC is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 description (continued) The THS5661 is available in both a 28-pin SOIC and TSSOP package. The device is characterized for operation over the industrial temperature range of –40°C to 85°C. AVAILABLE OPTIONS PACKAGE TA 28-TSSOP (PW) – 40°C to 85°C THS5661IPW 28-SOIC (DW) THS5661IDW functional block diagram AVDD C1 SLEEP EXTLO COMP1 0.1 µF COMP2 0.1 µF 1.2 V REF IOUT1 1 nF EXTIO – CEXT BIASJ 0.1 µF + I BIAS 2 kΩ Control AMP Current Source Array 50 Ω Output Current Switches IOUT2 RBIAS DVDD 50 Ω Logic D[11:0] Control MODE CLK DGND 2 RLOAD AGND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RLOAD THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 Terminal Functions TERMINAL NAME NO. AGND 20 AVDD BIASJ I/O DESCRIPTION I Analog ground return for the internal analog circuitry 24 I Positive analog supply voltage (4.5 V to 5.5 V) 18 O Full-scale output current bias CLK 28 I External clock input. Input data latched on rising edge of the clock. COMP1 19 I Compensation and decoupling node, requires a 0.1 µF capacitor to AVDD. COMP2 23 I Internal bias node, requires a 0.1 µF decoupling capacitor to AGND. D[11:0] [1:12] I Data bits 0 through 11. D11 is most significant data bit (MSB), D0 is least significant data bit (LSB). DGND 26 I Digital ground return for the internal digital logic circuitry DVDD 27 I Positive digital supply voltage (3 V to 5.5 V) EXTIO 17 I/O Used as external reference input when internal reference is disabled (i.e., EXTLO = AVDD). Used as internal reference output when EXTLO = AGND, requires a 0.1 µF decoupling capacitor to AGND when used as reference output. EXTLO 16 O Internal reference ground. Connect to AVDD to disable the internal reference source. IOUT1 22 O DAC current output. Full scale when all input bits are set 1 IOUT2 21 O Complementary DAC current output. Full scale when all input bits are 0 MODE 25 I Mode select. Internal pulldown. Mode 0 is selected if this pin is left floating or connected to DGND. See timing diagram. [13:14] N No connection 15 I Asynchronous hardware power down input. Active high. Internal pulldown. Requires 5 µs to power down but 3 ms to power up. NC SLEEP absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, AVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V DVDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V Voltage between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 0.5 V Supply voltage range, AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6.5 V to 6.5 V CLK, SLEEP, MODE (see Note 2) . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V Digital input D11–D0 (see Note 2) . . . . . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V IOUT1, IOUT2 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to AVDD + 0.3 V COMP1, COMP2 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V EXTIO, BIASJ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V EXTLO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 0.3 V Peak input current (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA Operating free-air temperature range, TA: THS5661I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Measured with respect to AGND. 2. Measured with respect to DGND. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA (unless otherwise noted) dc specifications PARAMETER TEST CONDITIONS Resolution MIN TYP MAX 12 UNIT Bits DC accuracy† INL Integral nonlinearity DNL Differential nonlinearity Monotonicity –4 TA = –40°C 40°C to 85°C –2 At 11-bit level ±0.75 4 LSB ±0.5 2 LSB Monotonic Analog output Offset error Gain error 0.02 Without internal reference 2.3 With internal reference 1.3 Full scale output current‡ Output compliance range AVDD = 5 V, IOUTFS = 20 mA %FSR %FSR 2 20 –1 1.25 Output resistance Output capacitance mA V 300 kΩ 5 pF Reference output Reference voltage 1.18 Reference output current§ 1.22 1.32 100 V nA Reference input VEXTIO Input voltage range 0.1 Input resistance Small signal bandwidth¶ Without CCOMP1 Input capacitance 1.25 V 1 MΩ 1.3 MHz 100 pF Temperature coefficients Offset drift Gain drift 0 ±40 Without internal reference ppm m of FSR/°C ±120 With internal reference ±35 Reference voltage drift Power supply AVDD DVDD IAVDD IDVDD AVDD DVDD Analog supply voltage 4.5 Digital supply voltage Analog supply current Sleep mode supply current Digital supply current# Sleep mode Power dissipation|| AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA 5.5 V 5.5 V 25 30 mA 3 5 mA 5 6 mA 175 mW ±0.4 Power supply rejection ratio %FSR/V ±0.025 Operating range † Measured at IOUT1 in virtual ground configuration. ‡ Nominal full-scale current IOUTFS equals 32X the IBIAS current. § Use an external buffer amplifier with high impedance input to drive any external load. ¶ Reference bandwidth is a function of external cap at COMP1 pin and signal level. # Measured at fCLK = 50 MSPS and fOUT= 1 MHz. || Measured for 50 Ω RLOAD at IOUT1 and IOUT2, fCLK = 50 MSPS and fOUT = 20 MHz. Specifications subject to change 4 5 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 –40 85 °C THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load (unless otherwise noted) ac specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog output fCLK Maximum output update rate ts(DAC) tpd Output settling time to 0.1%† GE Output propagation delay Glitch energy‡ tr(IOUT) tf(IOUT) Output rise time 10% to 90%† Output fall time 90% to 10%† Output noise DVDD = 4.5 V to 5.5 V DVDD = 3 V to 3.6 V 100 MSPS 67 Worst case LSB transition (code 2047 – code 2048) IOUTFS = 20 mA IOUTFS = 2 mA 35 ns 1 ns 5 pV-s 1 ns 1 ns 15 pA/√HZ 10 AC linearity THD Total harmonic distortion fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25°C fCLK = 50 MSPS, fOUT = 1 MHz, TA = –40°C to 85°C –75 fCLK = 50 MSPS, fOUT = 2 MHz, TA = 25°C fCLK = 100 MSPS, fOUT = 2 MHz, TA = 25°C –72 fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25°C fCLK = 50 MSPS, fOUT= 1 MHz, TA = –40°C to 85°C Spurious free dynamic range to Nyquist SFDR Spurious free dynamic range within a window –72 –66 dBc –72 81 68 fCLK = 50 MSPS, fOUT = 1 MHz, TA = 25°C fCLK = 50 MSPS, fOUT = 2.51 MHz, TA = 25°C 81 fCLK = 50 MSPS, fOUT = 5.02 MHz, TA = 25°C fCLK = 50 MSPS, fOUT = 20.2 MHz, TA = 25°C 68 fCLK = 100 MSPS, fOUT = 5.04 MHz, TA = 25°C fCLK = 100 MSPS, fOUT = 20.2 MHz, TA = 25°C 67 dBc 54 dBc fCLK = 100 MSPS, fOUT = 40.4 MHz, TA = 25°C fCLK = 50 MSPS, fOUT = 1 MHz, TA= 25°C,1 MHz span 56 dBc fCLK = 50 MSPS, fOUT = 5.02 MHz, 2 MHz span fCLK = 100 MSPS, fOUT= 5.04 MHz, 4 MHz span 84 74 dBc 63 86 dBc 87 † Measured single ended into 50 Ω load at IOUT1. ‡ Single-ended output IOUT1, 50 Ω doubly terminated load. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA (unless otherwise noted) digital specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Interface DVDD = 5 V 3.5 5 DVDD = 3.3 V 2.1 3.3 VIH High level input voltage High-level V VIL Low level input voltage Low-level IIH IIL High-level input current DVDD = 3 V to 5.5 V –10 10 µA Low-level input current DVDD = 3 V to 5.5 V –10 10 µA Input capacitance 1 5 pF tsu(D) th(D) Input setup time 1 ns Input hold time 1 ns tw(LPH) td(D) Input latch pulse high time 4 DVDD = 5 V 0 1.3 DVDD = 3.3 V 0 0.9 V Timing Digital delay time Specifications subject to change 6 ns 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 clk THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 TYPICAL CHARACTERISTICS† SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 0 dBFS SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 5 MSPS 90 90 84 84 fCLK = 5 MSPS 78 0 dBFS 72 SFDR – dBc SFDR – dBc fCLK = 25 MSPS fCLK = 50 MSPS fCLK = 70 MSPS 66 fCLK = 100 MSPS 78 –6 dBFS 72 –12 dBFS 60 66 54 48 0 10 20 30 40 60 50 0 0.5 Fout – MHz 1.5 2.0 2.5 Fout – MHz Figure 1 Figure 2 SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 25 MSPS SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 50 MSPS 90 78 84 72 78 SFDR – dBc SFDR – dBc 1.0 –6 dBFS 72 –12 dBFS –6 dBFS 66 –12 dBFS 60 0 dBFS 0 dBFS 66 54 60 0 2 4 6 8 10 12 48 0 Fout – MHz 5 10 15 20 25 Fout – MHz Figure 3 Figure 4 † AVDD = DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise noted.) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 TYPICAL CHARACTERISTICS† SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 100 MSPS 78 78 72 72 0 dBFS 66 SFDR – dBc SFDR – dBc SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 70 MSPS –6 dBFS 60 66 –6 dBFS –12 dBFS 60 –12 dBFS 54 54 0 dBFS 48 0 10 20 30 48 40 0 10 Fout – MHz 20 30 40 50 Fout – MHz Figure 5 Figure 6 SPURIOUS FREE DYNAMIC RANGE vs AOUT AT FOUT = FCLOCK/5 SPURIOUS FREE DYNAMIC RANGE vs AOUT AT FOUT = FCLOCK/11 78 78 2.27 MHz @ 25 MSPS 72 72 4.55 MHz @ 50 MSPS 5 MHz @ 25 MSPS 6.36 MHz @ 70 MSPS 66 SFDR – dBc SFDR – dBc 66 60 54 9.1 MHz @ 100 MSPS 10 MHz @ 50 MSPS 14 MHz @ 70 MSPS 60 54 48 48 20 MHz @ 100 MSPS 42 –27 –24 –21 –18 –15 –12 –9 –6 –3 0 42 –27 –24 –21 –18 –15 –12 –9 –6 –3 0 Aout – dBFS Aout – dBFS Figure 7 Figure 8 † AVDD = DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise noted.) 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 TYPICAL CHARACTERISTICS† DUAL TONE SPURIOUS FREE DYNAMIC RANGE vs AOUT AT FOUT = FCLOCK/7 TOTAL HARMONIC DISTORTION vs CLOCK FREQUENCY AT FOUT = 2 MHZ 78 –66 0.675/0.725 MHz @ 5 MSPS 3.38/3.63 MHz @ 25 MSPS 72 –72 66 THD – dBc SFDR – dBc 6.75/7.25 MHz @ 50 MSPS 60 2nd Harmonic –78 4th Harmonic –84 13.5/14.5 MHz @ 100 MSPS 54 3rd Harmonic 9.67/10.43 MHz @ 70 MSPS 48 –30 –27 –24 –21 –18 –15 –12 –9 –6 –3 –90 0 0 20 40 Aout – dBFS 60 80 100 120 Fclock – MSPS Figure 9 Figure 10 SPURIOUS FREE DYNAMIC RANGE vs FULL-SCALE OUTPUT CURRENT SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 100 MSPS 78 84 Fout = 2.5 MHz 78 72 Differential @ –6 dBFS 66 SFDR – dBc SFDR – dBc 72 Fout = 10 MHz 60 Fout = 40 MHz 66 Differential @ 0 dBFS Single-ended @ 0 dBFS 60 54 54 Fout = 28.6 MHz 48 48 2 4 6 8 10 12 14 16 18 20 Single-ended @ –6 dBFS 42 0 5 10 IoutFS – mA 15 20 25 30 35 40 45 50 Fout – MHz Figure 11 Figure 12 † AVDD = DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise noted.) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 TYPICAL CHARACTERISTICS† SPURIOUS FREE DYNAMIC RANGE vs TEMPERATURE AT 70 MSPS 78 Fout = 2 MHz 72 SFDR – dBc Fout = 10 MHz 66 Fout = 25 MHz 60 54 48 –40 –20 0 20 40 60 80 TA – °C Figure 13 INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY 1.0 0.5 0.0 –0.5 –1 0 512 1024 1536 2048 2560 3072 3584 4096 Code Figure 14 † AVDD = DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise noted.) 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 DNL – Differential Nonlinearity – LSB TYPICAL CHARACTERISTICS† DIFFERENTIAL NONLINEARITY 0.50 0.25 0.00 –0.25 –0.5 0 512 1024 1536 2048 2560 3072 3584 4096 Code Figure 15 SINGLE-TONE OUTPUT SPECTRUM 0 Amplitude – dBm –10 Fout = 5 MHz at Fclock = 50 MSPS –20 –30 –40 –50 –60 –70 –80 –90 –100 0 5 10 15 20 25 Frequency – MHz Figure 16 SINGLE-TONE OUTPUT SPECTRUM 0 Amplitude – dBm –10 Fout = 10 MHz at Fclock = 100 MSPS –20 –30 –40 –50 –60 –70 –80 –90 –100 0 10 20 30 40 50 Frequency – MHz Figure 17 † AVDD = DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise noted.) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 TYPICAL CHARACTERISTICS† DUAL-TONE OUTPUT SPECTRUM 0 Fclock = 100 MSPS Fout1 = 13.2 MHz, Fout2 = 14.2 MHz –10 Amplitude – dBm –20 –30 –40 –50 –60 –70 –80 –90 –100 0 10 20 30 40 50 20 25 Frequency – MHz Figure 18 FOUR-TONE OUTPUT SPECTRUM 0 Fclock = 50 MSPS Fout1 = 6.25 MHz, Fout2 = 6.75 MHz, Fout3 = 7.25 MHz, Fout4 = 7.75 MHz –10 Amplitude – dBm –20 –30 –40 –50 –60 –70 –80 –90 –100 0 5 10 15 Frequency – MHz Figure 19 † AVDD = DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise noted.) 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 TYPICAL CHARACTERISTICS† SUPPLY CURRENT vs OUTPUT FULL-SCALE OUTPUT CURRENT DIGITAL SUPPLY CURRENT vs RATIO (Fclock/Fout) AT DVDD = 5 V 30 25 100 MSPS I(DVDD) – Supply Current – mA I(AVDD) – Supply Current – mA 25 20 15 10 5 0 2 4 6 8 10 12 14 16 18 20 70 MSPS 15 50 MSPS 10 25 MSPS 5 5 MSPS 0 20 0 0.1 IOUTFS – Full-Scale Output Current – mA 0.2 0.3 0.4 0.5 Ratio – (Fclock/Fout) Figure 20 Figure 21 DIGITAL SUPPLY CURRENT vs RATIO (Fclock/Fout) AT DVDD = 3.3 V I(DVDD) – Supply Current – mA 10 8 70 MSPS 6 50 MSPS 4 25 MSPS 2 5 MSPS 0 0 0.1 0.2 0.3 0.4 0.5 Ratio – (Fclock/Fout) Figure 22 † AVDD = DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise noted.) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 APPLICATION INFORMATION The THS5661 architecture is based on current steering, combining high update rates with low power consumption. The CMOS device consists of a segmented array of PMOS transistor current sources, which are capable of delivering a full-scale current up to 20 mA. High-speed differential current switches direct the current of each current source to either one of the output nodes, IOUT1 or IOUT2. The complementary output currents thus enable differential operation, canceling out common mode noise sources (on-chip and PCB noise), dc offsets, even order distortion components, and increase signal output power by a factor of two. Major advantages of the segmented architecture are minimum glitch energy, excellent DNL, and very good dynamic performance. The DAC’s high output impedance of >300 kΩ and fast switching result in excellent dynamic linearity (spurious free dynamic range SFDR). The full-scale output current is set using an external resistor RBIAS in combination with an on-chip bandgap voltage reference source (1.2 V) and control amplifier. The current IBIAS through resistor RBIAS is mirrored internally to provide a full-scale output current equal to 32 times IBIAS. The full-scale current can be adjusted from 20 mA down to 2 mA. data interface and timing The THS5661 comprises separate analog and digital supplies, i.e. AVDD and DVDD. The digital supply voltage can be set from 5.5 V down to 3 V, thus enabling flexible interfacing with external logic. The THS5661 provides two operating modes, as shown in Table 1. Mode 0 (mode pin connected to DGND) supports a straight binary input data word format, whereas mode 1 (mode pin connected to DVDD) sets a twos complement input configuration. Figure 23 shows the timing diagram. Internal edge-triggered flip-flops latch the input word on the rising edge of the input clock. The THS5661 provides for minimum setup and hold times (> 1 ns), allowing for noncritical external interface timing. Conversion latency is one clock cycle for both modes. The clock duty cycle can be chosen arbitrarily under the timing constraints listed in the digital specifications table. However, a 50% duty cycle will give optimum dynamic performance. Figure 24 shows a schematic of the equivalent digital inputs of the THS5661, valid for pins D11–D0, SLEEP, and CLK. The digital inputs are CMOS-compatible with logic thresholds of DVDD/2 ±20%. Since the THS5661 is capable of being updated up to 100 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. The drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the THS5661, as well as its required min/max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above conditions will result in the lowest data feed-through and noise. Additionally, operating the THS5661 with reduced logic swings and a corresponding digital supply (DVDD) will reduce data feed-through. Note that the update rate is limited to 67 MSPS for a digital supply voltage DVDD of 3 V to 3.6 V. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 APPLICATION INFORMATION D[11:0] Valid Data ts(DAC) tpd 0.1% DAC 90% 50% Output 10% (IOUT1 or IOUT2) 0.1% tr(IOUT) th(D) tsu(D) td(D) 1/fCLK CLK 50% 50% 50% 50% 50% 50% tw(LPH) Figure 23. Timing Diagram Table 1. Input Interface Modes MODE 0 MODE 1 FUNCTION/MODE MODE PIN CONNECTED TO DGND MODE PIN CONNECTED TO DVDD Input code format Binary Twos complement DVDD External Digital in Internal Digital in Figure 24. Digital Equivalent Input POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 APPLICATION INFORMATION DAC transfer function The THS5661 delivers complementary output currents IOUT1 and IOUT2. Output current IOUT1 equals the approximate full-scale output current when all input bits are set high in mode 0 (straight binary input), i.e. the binary input word has the decimal representation 4095. For mode 1, the MSB is inverted (twos complement input format). Full-scale output current will flow through terminal IOUT2 when all input bits are set low (mode 0, straight binary input). The relation between IOUT1 and IOUT2 can thus be expressed as: IOUT1 + IOUT * IOUT2 FS where IOUTFS is the full-scale output current. The output currents can be expressed as: IOUT1 + IOUT FS CODE 4096 IOUT2 + IOUT FS (4095 CODE) 4096 * where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2 drive resistor loads RLOAD or a transformer with equivalent input load resistance RLOAD. This would translate into single-ended voltages VOUT1 and VOUT2 at terminal IOUT1 and IOUT2, respectively, of: VOUT1 + IOUT1 R LOAD + CODE 4096 VOUT2 + IOUT2 R LOAD + (4095–CODE) 4096 IOUT FS R LOAD IOUT FS R LOAD The differential output voltage VOUTDIFF can thus be expressed as: VOUT DIFF + VOUT1–VOUT2 + (2CODE–4095) 4096 IOUT FS R LOAD The latter equation shows that applying the differential output will result in doubling of the signal power delivered to the load. Since the output currents of IOUT1 and IOUT2 are complementary, they become additive when processed differentially. Care should be taken not to exceed the compliance voltages at node IOUT1 and IOUT2, which would lead to increased signal distortion. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 APPLICATION INFORMATION reference operation The THS5661 comprises a bandgap reference and control amplifier for biasing the full-scale output current. The full-scale output current is set by applying an external resistor RBIAS. The bias current IBIAS through resistor RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current equals 32 times this bias current. The full-scale output current IOUTFS can thus be expressed as: IOUT FS + 32 I BIAS + 32 R V EXTIO BIAS where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of 1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor CEXT of 0.1 µF should be connected externally to terminal EXTIO for compensation. The bandgap reference can additionally be used for external reference operation. In that case, an external buffer with high impedance input should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be disabled and overridden by an external reference by connecting EXTLO to AVDD. Capacitor CEXT may hence be omitted. Terminal EXTIO thus serves as either input or output node. The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor RBIAS or changing the externally applied reference voltage. The internal control amplifier has a wide input range, supporting the full-scale output current range of 20 dB. The bandwidth of the internal control amplifier is defined by the internal 1 nF compensation capacitor at pin COMP1 and the external compensation capacitor C1. The relatively weak internal control amplifier may be overridden by an externally applied amplifier with sufficient drive for the internal 1 nF load, as shown in Figure 25. This provides the user with more flexibility and higher bandwidths, which are specifically attractive for gain control and multiplying DAC applications. Pin SLEEP should be connected to AGND or left disconnected when an external control amplifier is used. EXT Reference Voltage – External Control AMP THS4041 + AGND AVDD SLEEP AVDD EXTLO EXTIO BIASJ 1.2 V REF COMP1 1 nF AVDD Current Source Array – REF AMP + Internal Control AMP R EXT IOUT1 or IOUT2 Figure 25. Bypassing the Internal Reference and Control Amplifier POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 APPLICATION INFORMATION analog current outputs Figure 26 shows a simplified schematic of the current source array output with corresponding switches. Differential PMOS switches direct the current of each individual PMOS current source to either the positive output node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack of the current sources and differential switches, and is typically >300 kΩ in parallel with an output capacitance of 5 pF. Output nodes IOUT1 and IOUT2 have a negative compliance voltage of –1 V, determined by the CMOS process. Beyond this value, transistor breakdown may occur, resulting in reduced reliability of the THS5661 device. The positive output compliance depends on the full-scale output current IOUTFS and positive supply voltage AVDD. The positive output compliance equals 1.25 V for AVDD = 5 V and IOUTFS = 20 mA. Exceeding the positive compliance voltage adversely affects distortion performance and integral nonlinearity. The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not exceed 0.5 V (e.g. when applying a 50 Ω doubly terminated load for 20 mA full-scale output current). Applications requiring the THS5661 output (i.e., OUT1 and/or OUT2) to extend its output compliance should size RLOAD accordingly. AVDD Current Sources Switches IOUT1 IOUT2 RLOAD Current Source Array RLOAD Figure 26. Equivalent Analog Current Output Figure 27(a) shows the typical differential output configuration with two external matched resistor loads. The nominal resistor load of 50 Ω will give a differential output swing of 2 VPP when applying a 20 mA full-scale output current. The output impedance of the THS5661 depends slightly on the output voltage at nodes IOUT1 and IOUT2. Consequently, for optimum dc integral nonlinearity, the configuration of Figure 27(b) should be chosen. In this I–V configuration, terminal IOUT1 is kept at virtual ground by the inverting operational amplifier. The complementary output should be connected to ground to provide a dc current path for the current sources switched to IOUT2. Note that the INL/DNL specifications for the THS5661 are measured with IOUT1 maintained at virtual ground. The amplifier’s maximum output swing and the DAC’s full-scale output current determine the value of the feedback resistor RFB. Capacitor CFB filters the steep edges of the THS5661 current output, thereby reducing the operational amplifier slew-rate requirements. In this configuration, the op amp should operate on a dual supply voltage due to its positive and negative output swing. Node IOUT1 should be selected if a single-ended unipolar output is desirable. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 APPLICATION INFORMATION CFB RFB 50 Ω IOUT1 100 Ω – IOUT1 +) +) VOUT + VOUT –) IOUT2 IOUT2 THS4001 THS4011 50 Ω (a) –) (b) Figure 27. Differential and Single-Ended Output Configuration The THS5661 can be easily configured to drive a doubly terminated 50 Ω cable. Figure 28(a) shows the single-ended output configuration, where the output current IOUT1 flows into an equivalent load resistance of 25 Ω. Node IOUT2 should be connected to ground or terminated with a resistor of 25 Ω. Differential-to-single conversion (e.g., for measurement purposes) can be performed using a properly selected RF transformer, as shown in Figure 28(b). This configuration provides maximum rejection of common-mode noise sources and even order distortion components, thereby doubling the power to the output. The center tap on the primary side of the transformer is connected to AGND, enabling a dc current flow for both IOUT1 and IOUT2. Note that the ac performance of the THS5661 is optimum and specified using this differential transformer coupled output, limiting the voltage swing at IOUT1 and IOUT2 to ±0.5 V. 50 Ω 50 Ω 1:1 VOUT VOUT IOUT1 IOUT1 100 Ω 50 Ω 50 Ω IOUT2 IOUT2 25 Ω 50 Ω (a) (b) Figure 28. Driving a Doubly Terminated 50 Ω Cable POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 APPLICATION INFORMATION sleep mode The THS5661 features a power-down mode that turns off the output current and reduces the supply current to less than 5 mA over the analog supply range of 4.5 V to 5.5 V and temperature range. The power-down mode is activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to AVDD). An internal pulldown circuit at node SLEEP ensures that the THS5661 is enabled if the input is left disconnected. Power-up and power-down activation times depend on the value of external capacitor at node SLEEP. For a nominal capacitor value of 0.1 µF power down takes less than 5 µs, and approximately 3 ms to power backup. The SLEEP mode should not be used when an external control amplifier is used, as shown in Figure 25. definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. offset error Offset error is defined as the deviation of the output current from the ideal of zero at a digital input value of 0. gain error Gain error is the error in slope of the DAC transfer function. signal-to-noise ratio + distortion (S/N+D or SINAD) S/N+D or SINAD is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. total harmonic distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels. output compliance range The maximum and minimum allowable voltage of the output of the DAC, beyond which either saturation of the output stage or breakdown may occur. settling time The time required for the output to settle within a specified error band. glitch energy The time integral of the analog value of the glitch transient. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 APPLICATION INFORMATION definitions of specifications and terminology (continued) offset drift The change in offset error versus temperature from the ambient temperature (TA = 25°C) in ppm of full-scale range per °C. gain drift The change in gain error versus temperature from the ambient temperature (TA = 25°C) in ppm of full-scale range per °C. reference voltage drift The change in reference voltage error versus temperature from the ambient temperature (TA = 25°C) in ppm of full-scale range per °C. THS5661 evaluation board An evaluation module (EVM) board for the THS5661 digital-to-analog converter is available for evaluation. This board allows the user the flexibility to operate the THS5661 in various configurations. Possible output configurations include transformer coupled, resistor terminated, and inverting/noninverting amplifier outputs. The digital inputs are designed to interface with the TMS320 C5000 or C6000 family of DSPs or to be driven directly from various pattern generators with the onboard option to add a resistor network for proper load termination. See the THS56x1 Evaluation Module User’s Guide for more details (SLAU032). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 22 J4 0.1 µF 4.7 µF J6 C34 6 U9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 2 1 R25 TDB 0.01 µF T1 4.7 µF C28 2 3 L2 L3 3 1 R24 49.9 C9 0.1 µF C23 0.1 µF R23 100 0.1 µF 0.01 µF C26 –5VA W8 C25 C27 750 R28 750 R30 W9 T1–1T–KK81 + 750 THS3001 4 –5VA R26 C33 +5VA 10 R22 + C35 J7 7 +5VA 750 R27 J8 D E F A B C FB2 + 10 µF C15 + C32 C24 10 µF 4.7 µH R16 3.0 K D2 4.7 µH FB4 W7 W6 J9 1 µF C22 1 µF C31 R29 49.9 0.01 µF 0.01 µF C20 –5VA 0.1 µF C21 R19 C18 4.7 µF + J2 W4 C14 0.01 µF 2 1 R15 2.94 K C12 0.1 µF FB3 +5VA 33 + C19 U7 4.7 µF LT1004D C29 +5VA 0.1 µF C30 1 +5VA 3 W3 20 23 19 24 R14 5K 18 2 1 10 µF + C4 26 27 25 15 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C3 C7 C6 C10 0.1 µF 0.1 µF 0.1 µF 0.1 µF C8 W5 0.01 µF C2 DVDCC 1 µF 0.1 µF C1 C11 0.1 µF DVDCC R20 10 K DVDCC DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 DAC8 DAC9 DAC10 DAC11 DAC12 DAC13 DAC14 DAC15 DVDCC MiscellaniousDigital Bypass Caps C5 0.1 µF FB1 DGND DVDD MODE SLEEP CLK NC4 NC3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Figure 29. Schematic R1 1.5 K D1 4.7 µH L1 U8 AD1580BRT 3 U5 THS5661 AGND COMP2 COMP1 AVDD BIASJ EXTIO EXTLO IOUT2 IOUT1 ALTERNATECONFIGURATION C13 0.1 µF C16 0.1 µF C17 0.1 µF 17 16 21 22 SN74ALVC08 U6A 11 12 13 14 15 16 17 18 R11A R11B R11C R11D R11E R11F R11G R11H U6D B8 B7 B6 B5 B4 B3 B2 B1 A8 A7 A6 A5 A4 A3 A2 A1 9 8 7 6 5 4 3 2 B1 B2 B3 B4 B5 B6 B7 B8 A1 A2 A3 A4 A5 A6 A7 A8 DIR 19 W2 3 R18 49.9 3 1 W1 R6 10 K R3 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP1 DSP0 J5 CLKOUT PDAC CLKOUT 3 5 0Ω 0Ω R8 0Ω R13 0Ω R17 R21 U3 SN74AHC1G00 A0 A1 I/OSTROBE DVDCC DSP[2..15] R5A R5B R5C R5D R5E R5F R5G R5H ~OE 10K R4H DSP8 R4G DSP9 R4F DSP10 R4E DSP11 R4D DSP12 R4C DSP13 R4B DSP14 R4A DSP15 DVDCC DVDCC U4 SN74HC1G32 5 2 3 4 5 6 7 8 9 1 SN74LVT245B 10 GND 18 17 16 15 14 13 12 11 U2 20 VCC OE 1 DIR 20 VCC OE 19 SN74LVT245B DVDCC R10H R10G R10F R10E R10D R10C R10B R10A ~OE DAC[2..15] DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 DAC8 DAC9 DAC10 DAC11 DAC12 DAC13 DAC14 DAC15 U1 10 GND U6C U6B 33 R7 33 R9 33 R12 0 Ω R2 DSP15 DSP14 DSP13 DSP12 DSP11 DSP10 DSP9 DSP8 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP1 DSP0 J3 12 11 10 9 8 7 6 5 4 3 2 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 J1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 APPLICATION INFORMATION THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 APPLICATION INFORMATION Figure 30. Board Layout, Layer 1 Figure 31. Board Layout, Layer 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 APPLICATION INFORMATION Figure 32. Board Layout, Layer 3 Figure 33. Board Layout, Layer 4 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 APPLICATION INFORMATION Figure 34. Board Layout, Layer 5 Table 2. Bill of Materials QTY REF. DES PART NUMBER DESCRIPTION MFG. 3 C1, C22, C31 1206ZC105KAT2A Ceranucm 1 µF, 10 V, X7R, 10% AVX 4 C18, C19, C28, C35 ECSTOJY475 6.3 V, 4.7 µF, tantalum Panasonic 3 C15, C24, C4 ECSTOJY106 6.3 V, 10 µF, tantalum Panasonic 0 C25, C32 6 C14, C2, C20, C26, C29, C33 12065C103KAT2A Ceramic, 0.01 µF, 50 V, X7R, 10% AVX 17 C10, C11, C12, C13, C16, C17, C21, C23, C27, C3, C30, C34, C5, C6, C7, C8, C9 12065C104KAT2A Ceramic, 0.1 µF, 50 V, X7R, 10% AVX 2 D1, D2 AND/AND5GA or equivalent GREEN LED, 1206 size SM chip LED 4 FB1, FB2, FB3, FB4 27-43-037447 Fair-Rite SM beads #27-037447 FairRite 1 J1 TSW-117-07-L-D or equivalent 34-Pin header for IDC Samtec 1 J2 KRMZ2 or equivalent 2 Terminal screw connector, 2TERM_CON Lumberg 1 J3 TSW-112-07-L-S or equivalent Single row 12-pin header Samtec 1 J4 KRMZ3 or equivalent 3 Terminal screw connector Lumberg 3 J5, J6, J7 142-0701-206 or equivalent PCB Mount SMA jack, SMA_PCB_MT Johnson Components 0 J8, J9 142-0701-206 or equivalent PCB Mount SMA jack, not installed Johnson Components 3 L1, L2, L3 DO1608C-472 DO1608C-series, DS1608C-472 Coil Craft 1 R1 1206 1206 Chip resistor, 1.5K, 1/4 W, 1% 4 R10, R11, R4, R5 CTS/CTS766-163-(R)330-G-TR 8 Element isolated resistor pack, 33 Ω Ceramic, not installed, 50 V, X7R, 10% POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 APPLICATION INFORMATION Table 2. Bill of Materials (Continued) QTY 26 REF. DES PART NUMBER DESCRIPTION MFG. 4 R12, R19, R7, R9 1206 1206 Chip resistor, 33 Ω, 1/4 W, 1% 5 R13, R17. R2, R21, R8 1206 1206 Chip resistor, 0 Ω, 1/4 W, 1% 1 R14 3214W-1-502 E or equivalent 4 mm SM Pot, 5K 1 R15 1206 1206 Chip resistor, 2.94K, 1/4 W, 1% 1 R16 1206 1206 Chip resistor, 3K, 1/4 W, 1% 3 R18, R24, R29 1206 1206 Chip resistor, 49.94K, 1/4 W, 1% 3 R20, R3, R6 1206 1206 Chip resistor, 10K, 1/4 W, 1% 1 R22 1206 1206 Chip resistor, 10K, 1/4 W, 1% 1 R23 1206 1206 Chip resistor, 100K, 1/4 W, 1% 1 R25 1206 1206 Chip resistor, TBD, 1/4 W, 1% 4 R26, R27, R28, R30 1206 1206 Chip resistor, 750K, 1/4 W, 1% 1 T1 T1-1T-KK81 RF Transformer, T1-1T-KK81 MiniCircuits 2 U1, U2 SN74LVT245BDW Octal bus transceiver, 3-state, SN74LVT245B TI 1 U3 SN74AHCT1G00DBVR/ SN74AHC1G00DBVR Single gate NAND, SN74AHC1G00 TI 1 U4 SN74AHCT1G32DBVR/ SN74AHCC1G32DBVR Single 2 input positive or gate, SN74AHC1G32 TI THS5641 THS5641IDW DAC, 2.7–5.5 V, 8 Bit, 125 MHz TI THS5651 THS5651IDW DAC, 2.7–5.5 V, 10 Bit, 125 MHz TI THS5661 THS5661IDW DAC, 2.7–5.5 V, 12 Bit, 125 MHz TI THS5671 THS5647IDW DAC, 2.7–5.5 V, 14 Bit, 125 MHz TI 1 SN74ALVC08 SN74ALVC08D Quad AND gate TI 1 LT1004D LT1004CD-1-2/LT1004ID-1-2 Precision 1.2 V reference TI 0 NOT INSTALLED AD1580BRT Precision voltage reference, not installed 1 THS3001 THS3001CD/THS2001ID THS3001 high-speed op amp TI 4 W2 TSW-102-07-L-S or equivalent 2 position jumper_.1’’ spacing, W2 Samtec 3 W3 TSW-102-07-L-S or equivalent 3 position jumper_.1’’ spacing, W3 Samtec 2 2X3_JUMPER TSW-102-07-L-S or equivalent 6-Pin header dual row, 0.025×0.1, 2X3_JUMPER Samtec POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Bourns THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.293 (7,45) Gage Plane 0.010 (0,25) 1 8 0°– 8° A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** 0.004 (0,10) 16 20 24 28 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 4040000 / C 07/96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 THS5661 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER SLAS200A – MAY 1999 – REVISED JULY 1999 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. 28 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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