THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 D D D D D D D D D D 28-PIN TSSOP/SOIC PACKAGE (TOP VIEW) 10-Bit Resolution 30 MSPS Analog-to-Digital Converter: Configurable Input Functions: – Single-Ended – Single-Ended With Analog Clamp – Single-Ended With Programmable Digital Clamp – Differential Built-in Programmable Gain Amplifier (PGA) Differential Nonlinearity: ±0.3 LSB Signal-to-Noise: 56 dB Spurious Free Dynamic Range: 60 dB Adjustable Internal Voltage Reference Straight Binary/ 2s Complement Output Out-of-Range Indicator Power-Down Mode AGND DVDD I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 OVR DGND 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 AVDD AIN VREF REFBS REFBF MODE REFTF REFTS CLAMPIN CLAMP REFSENSE WR OE CLK description The THS1031 is a CMOS, low power, 10-bit, 30 MSPS analog-to-digital converter (ADC) that can operate with a supply range from 2.7 V to 3.3 V. The THS1031 has been designed to give circuit developers more flexibility. The analog input to the THS1031 can be either single-ended or differential. This device has a built-in clamp amplifier whose clamp input level can be selected from an external dc source or from an internal high-precision 10-bit digital clamp level programmable via an internal CLAMP register. A 3-bit PGA is included to maintain SNR for small signal. The THS1031 provides a wide selection of voltage reference to match the user’s design requirements. For more design flexibility, the internal reference can be bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the application. The out-of-range output is used to monitor any out-of-range condition in THS1031’s input range. The format of digital output can be coded in either straight binary or 2s complement. The speed, resolution, and single-supply operation of the THS1031 are suited for applications in set-top-box (STB), video, multimedia, imaging, high-speed acquisition, and communications. The built-in clamp function allows dc restoration of video signal and is suitable for video application. The speed and resolution ideally suit charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and camcorders. A wide input voltage range between REFBS and REFTS allows the THS1031 to be applied in both imaging and communications systems The THS1031I is characterized for operation from – 40°C to 85°C. AVAILABLE OPTIONS PACKAGED DEVICES TA 28-TSSOP (PW) 28-SOIC (DW) 0°C to 70°C THS1031CPW THS1031CDW – 40°C to 85°C THS1031IPW THS1031IDW Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 functional block diagram CLAMP DAC Power Down 10 CLAMPIN WR CTL REG SW2 CLAMP SW1 BIN/2’S 3 AIN SHA A/D PGA REFTS DAC Output Buffers I/O0 – I/O9 REF REFBS MODE OVR DC REF OE SW3 Timing Circuit REFTF REFBF VBG SW4 REFSENSE 2 VREF POST OFFICE BOX 655303 CLK • DALLAS, TEXAS 75265 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AGND 1 I Analog ground AIN 27 I Analog input AVDD CLAMP 28 I Analog supply 19 I HI to enable CLAMP mode, LO to disable CLAMP mode CLAMPIN 20 I Connect to an external analog clamp reference input. CLK 15 I Clock input DGND 14 I Digital ground DVDD 2 I Digital driver supply I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 3 4 5 6 7 8 9 10 11 12 I/O MODE 23 I Mode input OE 16 I HI to the 3-state data bus, LO to enable the data bus OVR 13 O Out-of-range indicator REFBS 25 I Reference bottom sense REFBF 24 I Reference bottom decoupling REFSENSE 18 I Reference sense REFTF 22 I Reference top decoupling REFTS 21 I Reference top sense VREF WR 26 I/O 17 I Digital I/O bit 0 (LSB) Digital I/O bit 1 Digital I/O bit 2 Digital I/O bit 3 Digital I/O bit 4 Digital I/O bit 5 Digital I/O bit 6 Digital I/O bit 7 Digital I/O bit 8 Digital I/O bit 9 (MSB) Internal and external reference for ADC Write strobe goes HI to write data value D0:D9 to the internal registers. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage: AVDD to AGND, DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to 6.5 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to 0.3 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 6.5 to 6.5 V Mode input MODE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to AVDD + 0.3 V Reference voltage input range REFTF, REFTB, REFTS, REFBS to AGND . . . . . . . . . – 0.3 to AVDD + 0.3 V Analog input voltage range AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to AVDD + 0.3 V Reference input VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to AVDD + 0.3 V Reference output VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to AVDD + 0.3 V Clock input CLK to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to AVDD + 0.3 V Digital input to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to DVDD + 0.3 V Digital output to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to DVDD + 0.3 V Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 150°C Storage temperature range, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions digital inputs MIN High-level input voltage, VIH NOM MAX 2.4 UNIT V Low-level input voltage, VIL 0.2 x DVDD V analog inputs MIN Analog input voltage, VI(AIN) NOM MAX UNIT REFBS REFTS V Reference input voltage, VI(VREF) 1 2 V Reference input voltage, VI(REFTS) 1 0 AVDD AVDD–1 REFTS V Reference input voltage, VI(REFBS) Clamp input voltage, VI(CLAMPIN) REFBS V V power supply Supply voltage Maximum sampling rate = 30 MSPS AVDD DVDD MIN NOM MAX 2.7 3 5.5 2.7 3 5.5 UNIT V REFTS, REFBS reference voltages (MODE = AVDD) PARAMETER MIN REFTS Reference input voltage (top) 1 REFBS Reference input voltage (bottom) 0 Differential input (REFTS – REFBS) 1 TYP MAX UNIT AVDD AVDD–1 2 V V V Switched input capacitance on REFTS 0.6 pF Switched input capacitance on REFBS 0.6 pF sampling rate and resolution PARAMETER MIN Fs 5 Resolution 4 NOM 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT 30 MHz Bits THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 electrical characteristics, AVDD = 3 V, DVDD = 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AVDD, 2 V input span from 0.5 V to 2.5 V, external reference, PGA = 1X, TA = –40°C to 85°C (unless otherwise noted) analog inputs PARAMETER MIN TYP MAX REFBS REFTS UNIT VI(AIN) CI Analog input voltage V Switched input capacitance 1.2 pF FPBW Full power BW (–3 dB) 150 MHz DC leakage current (input = ± FS) 100 µA REFTF, REFBF reference voltages PARAMETER TEST CONDITIONS Differential input (REFTF – REFBF) MIN TYP MAX 1.3 1.5 1.7 2 2.5 3 1 2 Input common mode (REFTF + REFBF)/2 AVDD = 3 V AVDD = 5 V VREF = 1 V AVDD = 3 V AVDD = 5 V 2 VREF = 2 V AVDD = 3 V AVDD = 5 V 2.5 VREF = 1 V AVDD = 3 V AVDD = 5 V 1 0.5 VREF = 2 V AVDD = 3 V AVDD = 5 V 1.5 REFTF (MODE = AVDD) REFBF (MODE = AVDD) V V V 3 V 3.5 V 2 Input resistance between REFTF and REFBF UNIT V Ω 600 VREF reference voltages MIN TYP MAX UNIT Internal 1 V reference (REFSENSE = VREF) PARAMETER 0.95 1 1.05 V Internal 2 V reference (REFSENSE = AVSS) 1.90 2 2.10 V External reference (REFSENSE = AVDD) 1 Reference input resistance 2 18 V kΩ dc accuracy PARAMETER INL Integral nonlinearity DNL Differential nonlinearity MIN TYP MAX UNIT ±1 ±2 LSB ± 0.3 ±1 LSB Offset error 0.4 1.4 %FSR Gain error 1.4 3.5 %FSR Missing code No missing code assured POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 electrical characteristics, AVDD = 3 V, DVDD = 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AVDD, 2 V input span from 0.5 V to 2.5 V, external reference, PGA = 1X, TA = –40°C to 85°C (unless otherwise noted) (continued) dynamic performance (ADC and PGA) PARAMETER TEST CONDITIONS f = 3.5 MHz ENOB Effective number of bits MIN TYP 8.2 9 f = 3.5 MHz, AVDD = 5 V 8.8 f = 15 MHz 7.7 f = 15 MHz, AVDD = 5 V f = 3.5 MHz SFDR Spurious free dynamic range Total harmonic distortion 55 63 f = 15 MHz 48 – 58.2 f = 3.5 MHz, AVDD = 5 V – 68.7 f = 15 MHz Signal to noise Signal-to-noise dB – 51.9 51.2 56 f = 3.5 MHz, AVDD = 5 V 55 f = 15 MHz 53 f = 3.5 MHz dB 49.3 51.1 56 f = 3.5 MHz, AVDD = 5 V Signal to noise and distortion Signal-to-noise – 54.7 – 47 f = 15 MHz, AVDD = 5 V SINAD dB 52.4 f = 3.5 MHz f = 15 MHz, AVDD = 5 V SNR Bits 60 f = 3.5 MHz, AVDD = 5 V f = 3.5 MHz UNIT 7.64 f = 15 MHz, AVDD = 5 V THD MAX 55 f = 15 MHz 48.1 f = 15 MHz, AVDD = 5 V 47.7 dB PGA PARAMETER MIN Gain range (linear scale) TYP MAX 0.5 4 Gain step size (linear scale) UNIT V/V 0.5 Gain error from nominal 3% Number of control bits 3 Bits clamp DAC PARAMETER MIN Resolution TYP MAX 10 DAC output range Bits REFBF REFTF Clamping analog output voltage range 0.1 Clamping analog output voltage error – 40 AVDD– 0.1 + 40 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V mV THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 electrical characteristics, AVDD = 3 V, DVDD = 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AVDD, 2 V input span from 0.5 V to 2.5 V, external reference, PGA = 1X, TA = –40°C to 85°C (unless otherwise noted) (continued) clock PARAMETER MIN TYP tCK tCKH Clock period 33 Pulse duration, clock high 15 16.5 tCKL td Pulse duration, clock high 15 16.5 UNIT ns Clock to data valid t(ap) MAX ns ns 25 ns Pipeline latency 3 Cycles Aperture delay 4 ns Aperture uncertainty (jitter) 2 ps timing PARAMETER MIN TYP MAX UNIT t(PZ) t(DEN) Output disable to high-Z output 0 20 ns Output enable to output valid 0 20 ns t(OEW) t(WOE) Output disable to write enable 12 ns Output disable to write enable 12 ns t(WP) t(DS) Write pulse 15 ns Input data setup time 5 ns t(DH) Input data hold time 5 ns power supply PARAMETER ICC Operating supply current PD Power dissipation PD(STBY) Standby power TEST CONDITIONS MIN TYP MAX AVDD = 3 V, MODE = AGND AVDD = DVDD = 3 V 30.6 45 94 135 AVDD = DVDD = 5 V AVDD = DVDD = 3 V, MODE = AGND 160 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 5 UNIT mA mW mW 7 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION OE (See Note A) t(WP) t(WOE) t(OEW) WE t(DZ) t(DH) t(DS) hi–Z Output I/O t(DEN) hi–Z Input Output NOTE A: All timing measurements are based on 50% of edge transition. Figure 1. Write Timing Diagram Sample 2 Sample 3 Sample 1 Sample 5 Sample 4 Analog Input t(CK) t(CKL) t(CKH) Input Clock (See Note A) td Pipeline Latency Digital Output Sample 1 NOTE A: All timing measurements are based on 50% of edge transition. Figure 2. Digital Output Timing Diagram 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Sample 2 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 TYPICAL CHARACTERISTICS POWER DISSIPATION vs SAMPLING FREQUENCY 96 AVDD = DVDD = 3 V Fin = 3.5 MHz TA = 25°C 94 Power – mW 92 90 88 86 84 82 5 10 15 20 25 30 60 85 fs – Sampling Frequency – MHz Figure 3 EFFECTIVE NUMBER OF BITS vs TEMPERATURE Effective Number of Bits 10.0 9.5 9.0 AVDD = DVDD = 3 V Fin = 3.5 MHz Fs = 30 MSPS 8.5 8.0 7.5 7 –40 –15 10 35 Temperature – °C Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS vs FREQUENCY Effective Number of Bits 10.0 9.5 9.0 8.5 8.0 AVDD = DVDD = 3 V Fin = 3.5 MHz TA = 25°C 7.5 7 5 10 15 20 25 30 fs – Sampling Speed – MSPS Figure 5 EFFECTIVE NUMBER OF BITS vs FREQUENCY Effective Number of Bits 10.0 9.5 9.0 8.5 AVDD = 5 V, DVDD = 3 V Fin = 3.5 MHz TA = 25°C 8.0 7.5 7 5 10 15 20 fs – Sampling Speed – MSPS Figure 6 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 30 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS vs FREQUENCY Effective Number of Bits 10.00 9.50 9.00 8.50 AVDD = DVDD= 5 V, Fin = 3.5 MHz TA = 25°C 8.00 7.50 7.00 5 10 15 20 25 30 fs – Sampling Speed – MSPS Figure 7 DNL – Differential Nonlinearity – LSB DIFFERENTIAL NONLINEARITY vs INPUT CODE 1.0 0.8 0.6 0.4 0.2 –0.0 –0.2 –0.4 –0.6 –0.8 –1 AVDD = 3 V, DVDD = 3 V Fs = 30 MSPS 0 128 256 384 512 640 768 896 1024 Input Code Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 TYPICAL CHARACTERISTICS INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY vs INPUT CODE 2.0 AVDD = 3 V DVDD = 3 V Fs = 30 MSPS 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0 128 256 384 512 640 768 896 1024 Input Code Figure 9 FFT vs FREQUENCY 0 AVDD = 3 V DVDD = 3 V Fin = 3.5 MHz –20 –40 dB –60 –80 –100 –120 –140 0 0 200 1.5 400 3 600 4.5 800 6 1000 7.5 1200 9 1400 10.5 f –Frequency – MHz Figure 10 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1600 12 1800 13.5 2000 15 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 PRINCIPLES OF OPERATION Table 1. Mode Selection MODES ANALOG INPUT INPUT SPAN MODE PIN REFSENSE PIN AIN 1V AIN 2V AVDD AVDD AGND Short together AGND 9, 16 AIN AVDD AVDD/2 Mid Ra & Rb Short together to Ra AGND 10, 15, 16 AIN 1+Ra/Rb External VREF AGND 10, 15, 16 AIN 1V AIN 2V AVDD/2 AVDD/2 AIN 1+Ra/Rb VREF AVDD/2 AVDD/2 Top/bottom Center span AIN VREF PIN REFTS PIN Short together AVDD External Short together AGND NC Mid Ra & Rb Ra External AVDD External reference AIN 2 V max AGND AIN is input 1 REFTS & REFBS are shorted together for input 2 1V Differential Diff ti l in ut input AVDD/2 2V AVDD/2 AGND NC VREF AVDD/2 AVDD External See Note 1 See Note 1 NC REFBS PIN FIGURE AGND 8, 15 8, 14 Short together to the g common mode voltage 9, 14 10, 14 11, 14 Voltage within supply (REFTS–REBS) = 2 V max 12, 13 Short together AVDD/2 17 Short together NOTE 1: In external reference mode, VREF can be available for external use with CENTER SPAN setup. reference operations VREF-pin reference The voltage reference sources on the VREF pin are controlled by the REFSENSE pin as shown in Table 2. Table 2. VREF Reference Selection REFSENSE VREF AGND 2V AVDD Short to VREF The internal reference is disabled and an external reference should be connected to VREF pin if mode = AVDD/2 Connect to Ra/Rb 1+Ra/Rb 1V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 PRINCIPLES OF OPERATION reference operations (continued) D 1-V reference: The internal reference may be set to 1 V by connecting REFSENSE to VREF . THS1031 ADC/DAC REF + _ VBG VREF = 1 V + – REFSENSE AGND Figure 11. VREF 1-V Reference Mode D 2-V reference: The internal reference may be set to 2 V by connecting REFSENSE to AGND. THS1031 ADC/DAC REF + _ VBG VREF = 2 V + – REFSENSE AGND Figure 12. VREF 2-V Reference Mode 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 PRINCIPLES OF OPERATION reference operations (continued) D External divider: The internal reference can be set to a voltage between 1 V and 2 V by adding external resistors. THS1031 ADC/DAC REF + _ VBG VREF = 1 + (Ra/Rb) + – Ra REFSENSE Rb AGND Figure 13. VREF External Divider Reference Mode D External reference: The internal reference may be overridden by using an external reference. This condition is met by connecting REFSENSE to AVDD and an external reference circuit to the VREF pin. THS1031 ADC/DAC REF + _ VBG VREF = External + – REFSENSE AVDD AGND Figure 14. VREF External Reference Mode POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 PRINCIPLES OF OPERATION reference operations (continued) ADC reference The MODE pin is used to select the reference source for the ADC. D D Internal ADC Reference: Connect the MODE pin to AVDD to use the reference source for ADC generated on the VREF pin. (See VREF REFERENCE described in Table 2) such that (REFTF–REFBF) = VREF and (REFTF+REFBF)/2 is set to a voltage for optimum operation of the ADC (near AVDD/2). External ADC Reference: To supply an external reference source to the ADC, connect the MODE pin to AGND. An external reference source should be connected to REFTF/REFTS and REFBF/REFBS. MODE = AGND closes internal switches to allow a Kelvin connection through REFTS/REFBS, and disables the on-chip amplifiers which drive on to the ADC references. Differential input is not supported analog input mode single-ended input The single-ended input can be configured to work with either an external ADC reference or internal ADC reference. D External ADC Reference Mode: A single-ended analog input is accepted at the AIN pin where the input signal is bounded by the voltages on the REFTS and REFBS pins. Figure 15 shows an example of applying external reference to REFTS and REFBS pins in which REFTS is connected to the low-impedance 2-V source and REFBS is connected to the low-impedance 2-V source. REFTS and REFBS may be driven to any voltage within the supply as long as the difference (REFTS – REFBS) is between 1 V and 2 V as specified in Table 2. Figure 16 shows an example of external-reference using a Kelvin connection to eliminate line voltage drop errors. 2V THS1031 AIN 1V 2V 1V SHA REFTS REFBS MODE SW3 REFTF 0.1 µF 0.1 µF 10 µF REFBF 0.1 µF Figure 15. External ADC Reference Mode 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PGA A/D THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 PRINCIPLES OF OPERATION analog input mode(continued) REFTF THS1031 AIN REFBF SHA REFTS PGA A/D REFBS MODE 0.1 µF SW3 REFTF REFT 0.1 µF 0.1 µF 0.1 µF 10 µF REFBF REFB 0.1 µF Figure 16. Kelvin Connection With External ADC Reference Mode D Internal ADC Reference Mode With External Input Common Mode: The input common mode is supplied to pins REFTS and REFBS while connected together. The input signal should be centered around this common mode with peak-to-peak input equal to the voltage on the VREF pin. Input can be either dc-coupled or ac-coupled to the same common mode voltage (Figure 17) or any other voltage within the input voltage range. 2V THS1031 AIN 1V SHA REFTS PGA A/D 1.5 V REFBS AVDD MODE REFTF ADC REF VREF 0.1 µF 0.1 µF + _ 10 µF – + REFBF 1V REFSENSE 0.1 µF Figure 17. External Input Common Mode POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 PRINCIPLES OF OPERATION analog input mode(continued) D Internal ADC Reference Mode With Common Mode Input VREF/2: The input common mode is set to VREF/2 by connecting REFTS to VREF and REFBS to AVSS. The input signal at AIN will swing between VREF and AVSS. 2V THS1031 AIN 1V SHA REFTS PGA A/D 1.5 V REFBS MODE AVDD REFTF ADC REF VREF + _ 0.1 µF 0.1 µF – + 10 µF REFBF 1V 0.1 µF REFSENSE Figure 18. Common Mode Input VREF/2 With 1-V Internal Reference 2V THS1031 AIN 0V SHA REFTS PGA A/D REFBS AVDD MODE REFTF ADC REF VREF + _ – + 1V 0.1 µF 0.1 µF 10 µF REFBF 0.1 µF REFSENSE Figure 19. Common Mode Input VREF/2 With 2-V Internal Reference 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 PRINCIPLES OF OPERATION analog input mode(continued) differential input In this mode, the first differential input is applied to the AIN pin and the second differential input is applied to the common point where REFTS and REFBS are tied together. The common mode of the input should be set to AVDD/2 as shown in Figure 20. The maximum magnitude of the differential input signal should be equal to VREF. VREF THS1031 AIN AVDD/2 SHA REFTS A/D PGA REFBS AVDD MODE REFTF VREF is either internal or external VREF ADC REF 0.1 µF 0.1 µF 10 µF REFBF 0.1 µF Figure 20. Differential Input digital input mode The THS1031 contains 4 registers: two CLAMP registers, a CONTROL register, and a TEST register. The TEST register is reserved for test purposes. Binary data can be written into the CLAMP and CONTROL registers via I/O0– I/O9 by inserting an active-low write strobe to the WR input pin and an active-low signal to the OE input pin. This will disable the ADC’s output bus. The two MSBs of each register are address bits. For example, set bit 9 and bit 8 to 00 to select the clamp register 1. Set bit 9 and bit 8 to 01 to select the clamp register 2. clamp registers The internal digital clamp circuit uses a 10-bit DAC to convert the 10-bit digital value into the analog clamp level in which the clamp register 1 contains 8 LSBs of DAC(7:0). The clamp register 2 contains two MSBs of the DAC(9:8). DAC(9:8) (Default = 00): For clamping purpose, the entire range of voltage reference VREF is divided into 4 quarters which can be selected by bit 0 (DAC8) and bit 1 (DAC9) in the clamp register 2. The user can clamp to any of 256-dc levels within each quarter determined by the 8-bit content of the clamp register 1. Figure 21 shows how the DACs 10-bit digital input map to the analog clamping range from 0 V to VREF. D D Clamp Register 1 9 8 7 6 5 4 3 2 1 0 0 0 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 Clamp Register 2 9 8 7 6 5 4 3 2 1 0 0 1 X X X X X X DAC9 DAC8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 PRINCIPLES OF OPERATION digital input mode (continued) REFTF DAC (9:0) 1111111111 • • • 1100000000 1011111111 3/4 (REFTF – REFBF) • • • 1000000000 0111111111 1/2 (REFTF – REFBF) • • • 0100000000 0011111111 1/4 (REFTF – REFBF) • • • 0000000000 REFBF Figure 21. Digital Clamp Input Range control register D D D D 20 9 8 7 6 5 4 3 2 1 0 1 0 X Clamp Disable Bin/2’s Output INT/EXT Clamp Power Down PGA2 PGA1 PGA0 Clamp Disable: (Default = 0) Set bit 6 to 1 to disable the internal clamp amplifier for power savings. BIN/2s Output: (Default is straight binary) Set bit 5 to 0 to set the output data format to straight binary or set bit 5 to1 to set the output data format to 2s complement. INT/EXT Clamp: (Default = 0) Set bit 4 of the CONTROL register to 0 to select the external analog clamp or set bit 4 to 1 to select the internal digital clamp whose clamp level is defined in the clamp register described above. Power Down: (Default = 0) Set bit 3 of the CONTROL register to 1 to power down the THS1031. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 PRINCIPLES OF OPERATION digital input mode (continued) D PGA(2–0): (Default = 001) 3-bit gain for programmable gain amplifier can be set as indicated in the following table: PGA[2– 0] GAIN 000 0.5 001 Unity gain 010 1.5 011 2.0 100 2.5 101 3.0 110 3.5 111 4.0 test register (reserved) 9 8 7 6 5 4 3 2 1 0 1 1 X X X X X X X X digital output mode D D 3-State Output: The digital outputs can be set to high-impedance state by applying a Hi logic to the OE pin. Output Format: Defined by bit 5 of the CONTROL register. The output format is straight binary if bit 5 set to 0. The output format is 2s complement if bit 5 is set to 1. The default format is straight binary. clamp operation The THS1031 ADC features an internal clamp circuit for dc restoration of video or ac coupled signals. The clamp input level can come from either an external source or an internal digital clamp circuit containing a 10-bit DAC and clamp register. D D External Clamp Input: To enable the external clamp input source, use the default state on power up or write a 0 to bit 4 of the PGA/CONTROL register. This will connect the switch SW2 to the CLAMPIN pin. The clamp amplifier will then servo the voltage at the AIN pin to be equal to the clamp voltage applied at the CLAMPIN pin. After the desired clamp level is attained, the switch SW1 is opened by taking CLAMP back to logic low. Ignoring the droop caused by the input bias current, the input capacitor CIN will hold the DC voltage at AIN constant until the next clamp interval. The input resistor RIN has a minimum recommended value of 10 W, to maintain the closed-loop stability of the clamp amplifier. Internal Programmable Digital Clamp Input: The THS1031 ADC features a programmable digital clamp circuit to set more precise clamping level to 1-LSB accuracy for dc restoration of video or ac coupled signals. Figure 22 shows the internal clamp circuitry and the external control signals needed for the digital clamp operation. To enable the digital clamp input source, write a 1 to bit 4 of the CONTROL register which will connect the switch SW2 to the output of the 10-bit clamp DAC. In the CLAMP register, bit 0 to bit 7 are used to set the clamp level input to the 10-bit DAC and bit 6–7 are used to select one of 4 equal clamping voltage sub-ranges as described in the description of CLAMP REGISTER for digital input mode. The clamp amplifier will then servo the voltage at the AIN pin to be equal to the clamp voltage applied at the CLAMPIN pin. After the desired clamp level is attained, the switch SW1 is opened by taking CLAMP back to logic low. Ignoring the droop caused by the input bias current, the input capacitor CIN will hold the dc voltage at AIN constant until the next clamp interval. The input resistor RIN has a minimum recommended value of 10 W, to maintain the closed-loop stability of the clamp amplifier. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 PRINCIPLES OF OPERATION clamp operation (continued) D Clamp and Droop Analysis 16–Bit DAC CLAMPIN SW2 CLAMP Control Register + – SW1 C1 R1 AIN S/H Figure 22. Clamp Operation D Clamp Acquisition Time: Figure 22 shows the basic operation of the clamp circuit in which the ac input signal is passed through an RC coupler. The acquisition time when the switch is closed will equal a: T(acq) = Ci.Ri ln(Vc/Ve)(Eq.1) In case of composite video, typical input Ri = 20 Ω. In a video clamping application, the droop is a critical parameter and thus the input capacitor should be sized to allow sufficient acquisition time of clamp voltage at AIN within the CLAMP interval, but also to minimize droop between clamping intervals. Typically, Ci = 1µF By applying equation 1 above, the following examples apply to an NTSC composite video signal: D D D The acquisition time needed to clamp 1-V input level to black level (0.340 Vdc ) is about 130 µs. The acquisition time needed to clamp 2-V input level to the white level (1 Vdc) is about 140 µs. The acquisition time needed to clamp 3-V input level to the sync level (0.288 Vdc) is about 160 µs. droop The voltage droop is the voltage change across the input capacitor Ci by the bias current as follows: dV + ǒI ńCiǓ(t) bias where t = elapsed time between clamping intervals The bias current depends on the sampling rate. For a sampling rate of 30 MSPS and a typical input capacitance of 1 pF, the input resistance is Rs = 1/(Cs.Fs) = 1/(1 pFx30 MHz) = 33 kΩ For 1-V input range and clamping period = 64 µs, the max bias current will equal Ibias = 0.5 V/33 kΩ = 15 µA: dV = (15 µA/1 µF)(64 µs) = 0.96 mV For 1-V input range and clamping period = 64 µs, the max bias current will equal Ibias = 0.5 V/33 kΩ = 15 µA: dV = (15 µA/1 µF)(64 µs) = 0.96 mV For 2-V input range and clamping period = 64 µs, the max bias current will equal Ibias = 1.0 V/33 kΩ = 30 µA dV = (30 µA/1 µF)(64 µs) = 1.9 mV 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 PRINCIPLES OF OPERATION clamp operation (continued) requirements For a single direct source of NTSC video, D The initial clamp acquisition time needs to be between 130 µs and 160 µs to set the input dc level within 1 mV accuracy. D D The clamp pulse at CLAMP is recommended to be 2 µs (typ). The droop voltage needs to be compensated within one clamping period of 64 µs for 1 V and 2 V. Input ranges are 1 mV and 1.9 mV respectively which are less than 1 LSB. power management Upon power up, the THS1031 is put in the default mode. In the default mode, the PGA (PGA bypass) and the clamp DAC are powered down which adds to the device’s flexibility. The users need not incur the penalty of having to provide power for a certain section if it is not necessary to their design. When bit 3 of PGA/control register is set to 1, the entire device is powered down. The ADC will wake-up in 400 ns (typ) after the bit 3 is reset. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. 24 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS1031 2.7 V – 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE 16 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.293 (7,45) Gage Plane 0.010 (0,25) 1 8 0°– 8° A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** 0.004 (0,10) 16 20 24 28 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 4040000 / C 07/96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). 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