Si4136 I SM RF S Y N T H E S I Z E R W I T H I N T E G R A T E D VCO S FOR WIRELESS COMMUNICATIONS Features ! Dual-Band RF Synthesizers ! RF1: 2300 MHz to 2500 MHz RF2: 2025 MHz to 2300 MHz ! " " ! IF Synthesizer " ! ! Minimal External Components Required Low Phase Noise 5 µA Standby Current 25.7 mA Typical Supply Current 3.0 V to 3.6 V Operation Package: 24-pin TSSOP ! Dual-Band Communications ! ! 62.5 MHz to 1000 MHz Integrated VCOs, Loop Filters, Varactors, and Resonators ! Ordering Information: See page 28. Applications ! ! Pin Assignments ISM Band Communications Wireless LAN and WAN Description The Si4136 is a monolithic integrated circuit that performs both IF and RF synthesis for wireless communications applications. The Si4136 includes three VCOs, loop filters, reference and VCO dividers, and phase detectors. Divider and power down settings are programmable through a three-wire serial interface. Functional Block Diagram X IN P W D NB S DA TA S CLK S EN B A UX O U T R eference A m plifier ÷1/÷2 ÷ RRF1 P hase D etect R F1 P ow er D ow n C ontrol S erial Interface ÷ NRF1 ÷ RRF2 SCLK 1 24 SENB SDATA 2 23 VDDI GNDR 3 22 IFOUT GNDR 4 21 GNDI NC 5 20 IFLB GNDR 6 19 IFLA NC 7 18 GNDD GNDR 8 17 VDDD GNDR 9 16 GNDD GNDR 10 15 XIN RFOUT 11 14 PWDNB VDDR 12 13 AUXOUT R FO U T P hase D etect R F2 22-bit D ata R egister Test Mux ÷2 Si4136 ÷ NRF2 ÷ R IF Patents pending ÷2 P hase D etect IFD IV IFO U T IF ÷ N IF Rev. 1.0 12/00 IFLA IFLB Copyright © 2000 by Silicon Laboratories Si4136-DS10 S i4 13 6 2 Rev. 1.0 Si4136 TA B L E O F C O N T E N T S Section Page Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF and IF Outputs (RFOUT and IFOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si4136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev. 1.0 4 16 16 16 17 17 18 18 19 19 20 21 27 28 29 30 3 S i4 13 6 Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Ambient Temperature TA –40 25 85 °C Supply Voltage VDD 3.0 3.3 3.6 V Supply Voltages Difference V∆ –0.3 — 0.3 V (VDDR – VDDD), (VDDI – VDDD) Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. Table 2. Absolute Maximum Ratings1,2 Parameter Symbol Value Unit VDD –0.5 to 4.0 V Input Current3 IIN ±10 mA Input Voltage3 VIN –0.3 to VDD+0.3 V TSTG –55 to 150 DC Supply Voltage Storage Temperature Range o C Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. This device is a high performance RF integrated circuit with an ESD rating of < 2 kV. Handling and assembly of this device should only be done at ESD-protected workstations. 3. For signals SCLK, SDATA, SENB, PWDNB and XIN. 4 Rev. 1.0 Si4136 Table 3. DC Characteristics (VDD = 3.0 to 3.6 V, TA = –40 to 85°C) Parameter Test Condition Min Typ Max Unit RF1 and IF operating — 25.7 35 mA RF1 Mode Supply Current1 — 15.7 20 mA RF2 Mode Supply Current1 — 15.4 20 mA IF Mode Supply Current1 — 10 15 mA — 1 — µA Total Supply Current Symbol 1 Standby Current PWDNB = 0 High Level Input Voltage2 VIH 0.7 VDD — — V Low Level Input Voltage2 VIL — — 0.3 VDD V High Level Input Current2 IIH VIH = 3.6 V, VDD = 3.6 V –10 — 10 µA Low Level Input Current2 IIL VIL = 0 V, VDD= 3.6 V –10 — 10 µA High Level Output Voltage3 VOH IOH = –500 µA VDD–0.4 — — V Low Level Output Voltage3 VOL IOH = 500 µA — — 0.4 V Notes: 1. RF1 = 2.4 GHz, RF2 = 2.1 GHz, IFOUT = 800 MHz, LPWR = 0. 2. For signals SCLK, SDATA, SENB, and PWDNB. 3. For signal AUXOUT. Rev. 1.0 5 S i4 13 6 Table 4. Serial Interface Timing (VDD = 3.0 to 3.6 V, TA = –40 to 85°C) Symbol Test Condition Min Typ Max Unit SCLK Cycle Time tclk Figure 1 40 — — ns SCLK Rise Time tr Figure 1 — — 50 ns SCLK Fall Time tf Figure 1 — — 50 ns SCLK High Time th Figure 1 10 — — ns SCLK Low Time tl Figure 1 10 — — ns SDATA Setup Time to SCLK↑2 tsu Figure 2 5 — — ns SDATA Hold Time from SCLK↑2 Parameter1 thold Figure 2 0 — — ns 2 SENB↓ to SCLK↑ Delay Time ten1 Figure 2 10 — — ns SCLK↑ to SENB↑ Delay Time2 ten2 Figure 2 12 — — ns SENB↑ to SCLK↑ Delay Time2 ten3 Figure 2 12 — — ns tw Figure 2 10 — — ns SENB Pulse Width Notes: 1. All timing is referenced to the 50% level of the waveform, unless otherwise noted. 2. Timing is not referenced to 50% level of the waveform. See Figure 2. tr tf 80% SCLK 50% 20% th tclk tl Figure 1. SCLK Timing Diagram 6 Rev. 1.0 Si4136 A A Figure 2. Serial Interface Timing Diagram First bit clocked in Last bit clocked in D D D D D D D D D D D D D D D D D D A A A A 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0 data field address field Figure 3. Serial Word Format Rev. 1.0 7 S i4 13 6 Table 5. RF and IF Synthesizer Characteristics (VDD = 3.0 to 3.6 V, TA = –40 to 85°C) Symbol Test Condition Min Typ Max Unit XIN Input Frequency fREF XINDIV2 = 0 2 — 25 MHz XIN Input Frequency fREF XINDIV2 = 1 25 — 50 MHz Reference Amplifier Sensitivity VREF 0.5 — VDD +0.3 V VPP 0.010 — 1.0 MHz RF1 VCO Tuning Range2 2300 — 2500 MHz RF2 VCO Tuning Range2 2025 — 2300 MHz 526 — 952 MHz with IFDIV 62.5 — 1000 MHz Note: L ±10% –5 — 5 % Open loop — 0.75 — MHz/V RF2 VCO Pushing — 0.65 — MHz/V IF VCO Pushing — 0.10 — MHz/V — 0.250 — MHz p-p — 0.100 — MHz p-p — 0.025 — MHz p-p 1 MHz offset — –130 — dBc/Hz 100 Hz to 100 kHz — 1.2 — degrees rms 1 MHz offset — –131 — dBc/Hz RF2 Integrated Phase Error 100 Hz to 100 kHz — 1.0 — degrees rms IF Phase Noise at 800 MHz 100 kHz offset — –104 — dBc/Hz 100 Hz to 100 kHz — 0.4 — degrees rms Parameter1 Phase Detector Update Frequency IF VCO Center Frequency Range IFOUT Tuning Range from fCEN IFOUT VCO Tuning Range from fCEN RF1 VCO Pushing RF1 VCO Pulling RF2 VCO Pulling fφ fφ = fREF/R for XINDIV2 = 0 fφ = fREF/2R for XINDIV2 = 1 fCEN VSWR = 2:1, all phases, open loop IF VCO Pulling RF1 Phase Noise RF1 Integrated Phase Error RF2 Phase Noise IF Integrated Phase Error Notes: 1. fφ(RF) = 1 MHz, fφ(IF) = 1 MHz, RF1 = 2.4 GHz, RF2 = 2.1 GHz, IFOUT = 800 MHz, LPWR = 0, for all parameters unless otherwise noted. 2. RF VCO tuning range limits are fixed by inductance of internally bonded wires. 3. From power up request (PWDNB↑ or SENB↑ during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF synthesizers ready (settled to within 0.1 ppm frequency error). 4. From power down request (PWDNB↓, or SENB↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply current equal to IPWDN. 8 Rev. 1.0 Si4136 Table 5. RF and IF Synthesizer Characteristics (Continued) (VDD = 3.0 to 3.6 V, TA = –40 to 85°C) Test Condition Min Typ Max Unit Second Harmonic — –28 –20 dBc RF2 Harmonic Suppression — –23 –20 dBc IF Harmonic Suppression — –26 –20 dBc Parameter1 Symbol RF1 Harmonic Suppression RFOUT Power Level ZL = 50 Ω, RF1 active –15 –7 0 dBm RFOUT Power Level ZL = 50 Ω, RF2 active –15 –9 0 dBm IFOUT Power Level ZL = 50 Ω –7 –3 1 dBm Offset = 1 MHz — –63 — dBc Offset = 2 MHz — –68 — dBc Offset = 3 MHz — –70 — dBc Offset = 1 MHz — –63 — dBc Offset = 2 MHz — –68 — dBc Offset = 3 MHz — –70 — dBc µs RF1 Output Reference Spurs RF2 Output Reference Spurs Power Up Request to Synthesizer Ready3 Time tpup Figures 4, 5 fφ > 500 kHz — 80 100 Power Up Request to Synthesizer Ready3 Time tpup Figures 4, 5 fφ ≤ 500 kHz — 40/fφ 50/fφ Power Down Request to Synthesizer Off4 Time tpdn Figures 4, 5 — — 100 ns Notes: 1. fφ(RF) = 1 MHz, fφ(IF) = 1 MHz, RF1 = 2.4 GHz, RF2 = 2.1 GHz, IFOUT = 800 MHz, LPWR = 0, for all parameters unless otherwise noted. 2. RF VCO tuning range limits are fixed by inductance of internally bonded wires. 3. From power up request (PWDNB↑ or SENB↑ during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF synthesizers ready (settled to within 0.1 ppm frequency error). 4. From power down request (PWDNB↓, or SENB↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply current equal to IPWDN. Rev. 1.0 9 S i4 13 6 Figure 4. Software Power Management Timing Diagram 10 Figure 5. Hardware Power Management Timing Diagram Rev. 1.0 Si4136 Figure 6. Typical Transient Response RF1 at 2.4 GHz with 1 MHz Phase Detector Update Frequency Rev. 1.0 11 S i4 13 6 -60 -70 Phase Noise (dBc/Hz) -80 -90 -100 -110 -120 -130 -140 1.E+02 1.E+03 1.E+04 1.E+05 Offset Frequency (Hz) Typical RF1 Phase Noise at 2.4 GHz Figure 7. Typical RF1 Phase Noise at 2.4 GHz with 1 MHz Phase Detector Update Frequency Figure 8. Typical RF1 Spurious Response at 2.4 GHz with 1 MHz Phase Detector Update Frequency 12 Rev. 1.0 1.E+06 Si4136 s -60 -70 Phase Noise (dBc/Hz) -80 -90 -100 -110 -120 -130 -140 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 Offset Frequency (Hz) Typical RF2 Phase Noise at 2.1 GHz Figure 9. Typical RF2 Phase Noise at 2.1 GHz with 1 MHz Phase Detector Update Frequency Figure 10. Typical RF2 Spurious Response at 2.1 GHz with 1 MHz Phase Detector Update Frequency Rev. 1.0 13 S i4 13 6 -60 -70 Phase Noise (dBc/Hz) -80 -90 -100 -110 -120 -130 -140 1.E+02 1.E+03 1.E+04 1.E+05 Offset Frequency (Hz) Typical IF Phase Noise at 800 MHz Figure 11. Typical IF Phase Noise at 800 MHz with 1 MHz Phase Detector Update Frequency Figure 12. IF Spurious Response at 800 MHz with 1 MHz Phase Detector Update Frequency 14 Rev. 1.0 1.E+06 Si4136 V DD S i4136 F ro m 1 S ys te m SCLK SENB 30 Ω ∗ 24 0.0 22 µ F C o n tro ller 2 VDDI S D ATA 3 4 5 G NDR IF O U T G NDR G NDI NC IF L B G NDR IF L A 6 7 NC G NDD G NDR VDDD G NDR G NDD G NDR X IN 23 L M A TC H 22 IF O U T 21 P rin ted Trace In d u c to r o r C h ip In d u cto r 20 19 18 V DD 8 9 56 0 pF 0.0 22 µ F 17 16 56 0 pF 10 15 E xtern a l C lo ck 56 0 pF 11 RFOUT RFOUT 0.0 22 µ F PW DNB 14 PDW NB V DD 12 VDDR AUXO UT 13 AUXO UT *A dd 30 Ω se ries resistor if using IF outp u t divid e valu es 2 , 4, or 8 and f C E N < 600 M H z. Figure 13. Typical Application Circuit: Si4136-BT Rev. 1.0 15 S i4 13 6 Functional Description The Si4136 is a monolithic integrated circuit that performs IF and dual-band RF synthesis for many wireless communications applications. This integrated circuit (IC), along with a minimum number of external components, is all that is necessary to implement the frequency synthesis function in applications like W-LAN using the IEEE 802.11 standard. The Si4136 has three complete phase-locked loops (PLLs), with integrated voltage-controlled oscillators (VCOs). The low phase noise of the VCOs makes the Si4136 suitable for use in demanding wireless communications applications. Also integrated are phase detectors, loop filters, and reference and output frequency dividers. The IC is programmed through a three-wire serial interface. Two PLLs are provided for RF synthesis. These RF PLLs are multiplexed so that only one PLL is active at a given time (as determined by the setting of an internal register). The active PLL is the last one written. The center frequency of the VCO in each PLL is set by the internal bond wire inductance within the package. Inaccuracies in these inductances are compensated for by the self-tuning algorithm. The algorithm is run following power-up or following a change in the programmed output frequency. The RF PLLs contain a divide-by-2 circuit before the Ndivider. As a result, the phase detector frequency (fφ) is equal to half the desired channel spacing. For example, for a 200 kHz channel spacing, fφ would equal 100 kHz. The IF PLL does not contain the divide-by-2 circuit before the N-divider. In this case, fφ is equal to the desired channel spacing. Each RF VCO is optimized for a particular frequency range. The RF1 VCO is optimized to operate from 2.3 GHz to 2.5 GHz, while the RF2 VCO is optimized to operate between 2.025 GHz and 2.3 GHz. One PLL is provided for IF synthesis. The center frequency of this circuit’s VCO is set by an external inductance. The PLL can adjust the IF output frequency by ±5% of the VCO center frequency. Inaccuracies in the value of the external inductance are compensated for by the Si4136’s proprietary self-tuning algorithm. This algorithm is initiated each time the PLL is poweredup (by either the PWDNB pin or by software) and/or each time a new output frequency is programmed. The IF VCO can have its center frequency set as low as 526 MHz and as high as 952 MHz. An IF output divider is provided to divide down the IF output frequencies, if needed. The divider is programmable, capable of dividing by 1, 2, 4, or 8. 16 In order to accommodate designs running at XIN frequencies greater than 25 MHz, the Si4136 includes a programmable divide-by-2 option (XINDIV2 in Register 0, D6) on the XIN input. By enabling this option, the Si4136 can accept a range of TCXO frequencies from 25 MHz to 50 MHz. This feature makes the Si4136 ideal for W-LAN radio designs operating at an XIN of 44 MHz. The unique PLL architecture used in the Si4136 produces settling (lock) times that are comparable in speed to fractional-N architectures without suffering the high phase noise or spurious modulation effects often associated with those designs. Serial Interface A timing diagram for the serial interface is shown in Figure 2 on page 7. Figure 3 on page 7 shows the format of the serial word. The Si4136 is programmed serially with 22-bit words comprised of 18-bit data fields and 4-bit address fields. When the serial interface is enabled (i.e., when SENB is low) data and address bits on the SDATA pin are clocked into an internal shift register on the rising edge of SCLK. Data in the shift register is then transferred on the rising edge of SENB into the internal data register addressed in the address field. The serial interface is disabled when SENB is high. Table 11 on page 21 summarizes the data register functions and addresses. It is not necessary (although it is permissible) to clock into the internal shift register any leading bits that are “don’t cares.” Setting the IF VCO Center Frequencies The IF PLL can adjust its output frequency ±5% from the center frequency as established by the value of an external inductance connected to the VCO. The RF1 and RF2 PLLs have fixed operating ranges due to the inductance set by the internal bond wires. Each center frequency is established by the value of the total inductance (internal and/or external) connected to the respective VCO. Manufacturing tolerance of ±10% for the external inductor is acceptable for the IF VCO. The Si4136 will compensate for inaccuracies by executing a self-tuning algorithm following PLL power-up or following a change in the programmed output frequency. Because the total tank inductance is in the low nH range, the inductance of the package needs to be considered in determining the correct external inductance. The total inductance (LTOT) presented to the IF VCO is the sum of the external inductance (LEXT) Rev. 1.0 Si4136 and the package inductance (LPKG). The IF VCO has a nominal capacitance (CNOM) in parallel with the total inductance, and the center frequency is as follows: 1 1 fCEN = --------------------------------------------- = ---------------------------------------------------------------------2π ( L PKG + L EXT ) ⋅ C NOM 2π L TOT ⋅ C NOM Table 6 summarizes the characteristics of the IF VCO. Table 6. Si4136-BT VCO Characteristics VCO IF Fcen Range Cnom (MHz) (pF) Min Max 526 952 6.5 Lpkg (nH) 2.1 Lext Range (nH) Min Max 2.2 12.0 IFLA The Si4136’s self-tuning algorithm will compensate for component value errors at any temperature within the specified temperature range. However, the ability of the PLL to compensate for drift in component values that occur after self-tuning is limited. For external inductances with temperature coefficients around ±150 ppm/°C, the PLL will be able to maintain lock for changes in temperature of approximately ±30°C. 2 L EXT L PKG The self-tuning algorithm is initiated immediately following power-up of a PLL or, if the PLL is already powered, following a change in its programmed output frequency. This algorithm attempts to tune the VCO so that its free-running frequency is near the desired output frequency. In so doing, the algorithm will compensate for manufacturing tolerance errors in the value of the external inductance connected to the IF VCO. It will also reduce the frequency error for which the PLL must correct to get the precise desired output frequency. The self-tuning algorithm will leave the VCO oscillating at a frequency in error by somewhat less than 1% of the desired output frequency. After self-tuning, the PLL controls the VCO oscillation frequency. The PLL will complete frequency locking, eliminating any remaining frequency error. Thereafter, it will maintain frequency-lock, compensating for effects caused by temperature and supply voltage variations. Si4136 L PKG Self-Tuning Algorithm IFLB 2 As a design example, suppose synthesizing frequencies in a 30 MHz band between 735 MHz and 765 MHz is desired. The center frequency should be defined as midway between the two extremes, or 750 MHz. The PLL will be able to adjust the VCO output frequency ±5% of the center frequency, or ±37.5 MHz of 750 MHz (i.e., from approximately 713 MHz to 788 MHz). The IF VCO has a CNOM of 6.5 pF, and a 6.9 nH inductance (correct to two digits) in parallel with this capacitance will yield the desired center frequency. An external inductance of 4.8 nH should be connected between IFLA and IFLB, as shown in Figure 14. This, in addition to 2.1 nH of package inductance, will present the correct total inductance to the VCO. In manufacturing, the external inductance can vary ±10% of its nominal value and the Si4136 will correct for the variation with the self-tuning algorithm. Applications where the PLL is regularly powered-down or the frequency is periodically reprogrammed minimize or eliminate the potential effects of temperature drift because the VCO is re-tuned in either case. In applications where the ambient temperature can drift substantially after self-tuning, it may be necessary to monitor the lock-detect bar (LDETB) signal on the AUXOUT pin to determine whether a PLL is about to run out of locking capability. (See “Auxiliary Output (AUXOUT)” for how to select LDETB.) The LDETB signal will be low after self-tuning has completed but will rise when either the IF or RF PLL nears the limit of its compensation range. (LDETB will also be high when either PLL is executing the self-tuning algorithm.) The output frequency will still be locked when LDETB goes high, but the PLL will eventually lose lock if the temperature continues to drift in the same direction. Therefore, if LDETB goes high both the IF and RF PLLs should promptly be re-tuned by initiating the self-tuning algorithm. For more information on designing the external trace inductor, please refer to Application Note 31. Output Frequencies Figure 14. Example of IF External Inductor The IF and RF output frequencies are set by programming the R- and N-Divider registers. Each PLL has its own R and N registers so that each can be Rev. 1.0 17 S i4 13 6 programmed independently. Programming either the Ror N-Divider register for RF1 or RF2 automatically selects the associated output. transient until the point at which stability begins to be compromised. The optimal gain depends on N. Table 8 lists recommended settings for different values of N. When XINDIV2 = 0, the reference frequency on the XIN pin is divided by R and this signal is the input to the PLL’s phase detector. The other input to the phase detector is the PLL’s VCO output frequency divided by 2N for the RF PLLs or N for the IF PLL. After an initial transient Table 8. Optimal KP Settings N RF1 KP1<1:0> RF2 KP2<1:0> IF KPI<1:0> ≤2047 00 00 00 2048 to 4095 00 01 01 4096 to 8191 01 10 10 8192 to 16383 10 11 11 ≥16384 11 11 11 fOUT = (2N/R) " fREF (for the RF PLLs) fOUT = (N/R) " fREF (for the IF PLL). The integers R are set by programming the RF1 RDivider register (Register 6), the RF2 R-Divider register (Register 7) and the IF R-Divider register (Register 8). The integers N are set by programming the RF1 NDivider register (register 3), the RF2 N-Divider register (Register 4), and the IF N-Divider register (Register 5). If the optional divide-by-2 circuit on the XIN pin is enabled (XINDIV2 = 1) then after an initial transient fOUT = (N/R) " fREF (for the RF PLLs) fOUT/N = (N/2R) " fREF (for the IF PLL). Each N-Divider is implemented as a conventional high speed divider. That is, it consists of a dual-modulus prescaler, a swallow counter, and a lower speed synchronous counter. However, the control of these sub-circuits is handled automatically. Only the appropriate N value should be programmed. PLL Loop Dynamics The transient response for each PLL is determined by its phase detector update rate fφ (equal to fREF/R) and the phase detector gain programmed for each RF1, RF2, or IF synthesizer. (See Register 1.) Four different settings for the phase detector gain are available for each PLL. The highest gain is programmed by setting the two phase detector gain bits to 00, and the lowest by setting the bits to 11. The values of the available gains, relative to the highest gain, are listed in Table 7. Table 7. Gain Values (Register 1) KP Bits Relative P.D. Gain 00 1 01 1/2 10 1/4 11 1/8 The settling time for each PLL is directly proportional to its phase detector update period Tφ (Tφ equals 1/fφ). During the first 13 update periods the Si4136 executes the self-tuning algorithm. Thereafter the PLL controls the output frequency. Because of the unique architecture of the Si4136 PLLs, the time required to settle the output frequency to 0.1 ppm error is only about 25 update periods. Thus, the total time after power-up or a change in programmed frequency until the synthesized frequency is well settled—including time for self-tuning—is around 40 update periods. Note: This settling time analysis holds for fφ ≤ 500 kHz. For fφ > 500 kHz, the settling time can be a maximum of 100 µs as specified in Table 5. RF and IF Outputs (RFOUT and IFOUT) The RFOUT and IFOUT pins are driven by amplifiers that buffer the RF VCOs and IF VCO, respectively. The RF output amplifier receives its input from either the RF1 or RF2 VCO, depending upon which R- or NDivider register was last written. For example, programming the N-Divider register for RF1 automatically selects the RF1 VCO output. Figure 13 on page 15 shows an application diagram for the Si4136. The RF output signal must be AC coupled to its load through a capacitor. In general, a higher phase detector gain will decrease in-band phase noise and increase the speed of the PLL 18 The VCO gain and loop filter characteristics are not programmable. The IFOUT pin must also be AC coupled to its load through a capacitor. The IF output level is dependent upon the load. Figure 17 displays the output level versus load resistance. For resistive loads greater than 500 Ω the output level saturates and the bias currents in the IF output amplifier are higher than they need to be. The LPWR bit in the Main Configuration register Rev. 1.0 Si4136 (Register 0) can be set to 1 to reduce the bias currents and therefore reduce the power dissipated by the IF amplifier. For loads less than 500 Ω, LPWR should be set to 0 to maximize the output level. 450 400 350 LPWR=1 LPWR=0 300 Output Voltage (mVrms) For IF frequencies greater than 500 MHz, a matching network is required in order to drive a 50 Ω load. See Figure 15 below. The value of LMATCH can be determined by Table 9. 250 200 150 Typical values range between 8 nH and 40 nH. 100 50 >500 pF 0 IFOUT 0 200 400 600 800 1000 1200 Ω) Load Resistance (Ω L MATCH Figure 17. Typical IF Output Voltage vs. Load Resistance at 550 MHz 50 Ω Reference Frequency Amplifier The Si4136 provides a reference frequency amplifier. If the driving signal has CMOS levels, it can be connected directly to the XIN pin. Otherwise, the reference frequency signal should be AC coupled to the XIN pin through a 560 pF capacitor. Figure 15. IF Frequencies > 500 MHz Table 9. LMATCH Values Frequency LMATCH 500–600 MHz 40 nH 600–800 MHz 27 nH 800–1 GHz 18 nH Power Down Modes For frequencies less than 500 MHz, the IF output buffer can directly drive a 200 Ω resistive load or higher. For resistive loads greater than 500 Ω (f < 500 MHz) the LPWR bit can be set to reduce the power consumed by the IF output buffer. See Figure 16 below. >500 pF IFOUT >200 Ω Table 10 summarizes the power down functionality. The Si4136 can be powered down by taking the PWDNB pin low or by setting bits in the Power Down register (Register 2). When the PWDNB pin is low, the Si4136 will be powered down regardless of the Power Down register settings. When the PWDNB pin is high, power management is under control of the Power Down register bits. The IF and RF sections of the Si4136 circuitry can be individually powered down by setting the Power Down register bits PDIB and PDRB low. The reference frequency amplifier will also be powered up if either the PDRB and PDIB bits are high. Also, setting the AUTOPDB bit to 1 in the Main Configuration register (Register 0) is equivalent to setting both bits in the Power Down register to 1. The serial interface remains available and can be written in all power-down modes. Figure 16. IF Frequencies < 500 MHz Auxiliary Output (AUXOUT) The signal appearing on AUXOUT is selected by setting the AUXSEL bits in the Main Configuration register (Register 0). The LDETB signal can be selected by setting the AUXSEL bits to 011. This signal can be used to indicate that the IF or RF PLL is about to lose lock due to excessive ambient temperature drift and should be retuned. Rev. 1.0 19 S i4 13 6 Table 10. Power Down Configuration PWDNB Pin AUTOPDB PDIB PDRB IF Circuitry RF Circuitry PWDNB = 0 x x x OFF OFF 0 0 0 OFF OFF 0 0 1 OFF ON 0 1 0 ON OFF 0 1 1 ON ON 1 x x ON ON PWDNB = 1 Note: x = don’t care. 20 Rev. 1.0 Si4136 Control Registers Table 11. Register Summary Register Name Bit Bit Bit Bit 17 16 15 14 Bit 13 Bit 12 AUXSEL Bit 11 Bit Bit Bit Bit 10 9 8 7 Bit 6 Bit 5 0 Main Configuration 0 0 0 0 1 Phase Detector Gain 0 0 0 0 0 2 Power Down 0 0 0 0 0 3 RF1 N Divider 4 RF2 N Divider 0 5 IF N Divider 0 0 6 RF1 R Divider 0 0 0 0 0 RRF1 7 RF2 R Divider 0 0 0 0 0 RRF2 8 IF R Divider 0 0 0 0 0 RIF 9 Reserved IFDIV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XIN LPWR DIV2 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 AUTO PDB 0 0 0 KPI 0 KP2 0 0 KP1 0 PDIB PDRB NRF1 NRF2 NIF . . . 15 Reserved Note: Registers 9–15 are reserved. Writes to these registers may result in unpredictable behavior. Rev. 1.0 21 S i4 13 6 Register 0. Main Configuration Address Field = A[3:0] = 0000 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name 22 0 0 0 0 AUXSEL IFDIV 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 XIN DIV2 LPWR 0 AUTO PDB 0 0 0 Bit Name Function 17:14 Reserved Program to zero. 13:12 AUXSEL Auxiliary Output Pin Definition. 00 = Reserved. 01 = Force output low. 11 = Lock Detect (LDETB). 11:10 IFDIV IF Output Divider 00 = IFOUT = IFVCO Frequency 01 = IFOUT= IFVCO Frequency/2 10 = IFOUT = IFVCO Frequency/4 11 = IFOUT = IFVCO Frequency/8 9:7 Reserved Program to zero. 6 XINDIV2 XIN Divide-By-2 Mode. 0 = XIN not divided by 2. 1 = XIN divided by 2. 5 LPWR 4 Reserved Program to zero. 3 AUTOPDB Auto Power Down 0 = Software powerdown is controlled by Register 2. 1 = Equivalent to setting all bits in Register 2 = 1. 2:0 Reserved Program to zero. Output Power-Level Settings for IF Synthesizer Circuit. 0 = RLOAD < 500 Ω—normal power mode. 1 = RLOAD ≥ 500 Ω—low power mode. Rev. 1.0 Si4136 Register 1. Phase Detector Gain Address Field (A[3:0]) = 0001 Bit Name D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 0 0 0 0 D9 D8 D7 D6 0 0 0 0 0 Bit Name 17:6 Reserved 5:4 KPI IF Phase Detector Gain Constant. N Value KPI <2048 = 00 2048–4095 = 01 4096–8191 = 10 >8191 = 11 3:2 KP2 RF2 Phase Detector Gain Constant. N Value KP2 <2048 = 00 2048–4095 = 01 4096–8191 = 10 >8191 = 11 1:0 KP1 RF1 Phase Detector Gain Constant. N Value KP1 <4096 = 00 4096–8191 = 01 8192–16383 = 10 >16383 = 11 D5 D4 KPI D3 D2 KP2 D1 D0 KP1 Function Program to zero. Rev. 1.0 23 S i4 13 6 Register 2. Power Down Address Field (A[3:0]) = 0010 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name 0 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 0 0 0 0 0 0 0 0 Bit Name 17:2 Reserved 1 PDIB Power Down IF Synthesizer. 0 = IF synthesizer powered down. 1 = IF synthesizer on. 0 PDRB Power Down RF Synthesizer. 0 = RF synthesizer powered down. 1 = RF synthesizer on. D1 D0 PDIB PDRB Function Program to zero. Register 3. RF1 N Divider Address Field (A[3:0]) = 0011 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name D8 D7 D6 D5 D4 D3 D2 D1 D0 D5 D4 D3 D2 D1 D0 NRF1 Bit Name 17:0 NRF1 Function N Divider for RF1 Synthesizer. NRF1 ≥ 992. Register 4. RF2 N Divider Address Field = A[3:0] = 0100 Bit Name 24 D17 D16 D15 D14 D13 D12 D11 D10 D9 0 D8 D7 D6 NRF2 Bit Name 17 Reserved 16:0 NRF2 Function Program to zero. N Divider for RF2 Synthesizer. NRF2 ≥ 240. Rev. 1.0 Si4136 Register 5. IF N Divider Address Field (A[3:0]) = 0101 Bit D17 D16 D15 D14 D13 D12 D11 D10 Name 0 D9 D8 0 D7 D6 D5 D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 NIF Bit Name 17:16 Reserved 15:0 NIF Function Program to zero. N Divider for IF Synthesizer. NIF ≥ 56. Register 6. RF1 R Divider Address Field (A[3:0]) = 0110 Bit Name D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 0 D9 D8 0 Reserved 12:0 RRF1 D6 D5 RRF1 Name 17:13 D7 Function Program to zero. R Divider for RF1 Synthesizer. RRF1 can be any value from 7 to 8189 if KP1 = 00 8 to 8189 if KP1 = 01 10 to 8189 if KP1 = 10 14 to 8189 if KP1 = 11 Register 7. RF2 R Divider Address Field (A[3:0]) = 0111 Bit Name D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 Bit Name 17:13 Reserved 12:0 RRF2 0 D9 0 D8 D7 D6 D5 RRF2 Function Program to zero. R Divider for RF2 Synthesizer. RRF2 can be any value from 7 to 8189 if KP2 = 00 8 to 8189 if KP2 = 01 10 to 8189 if KP2 = 10 14 to 8189 if KP2 = 11 Rev. 1.0 25 S i4 13 6 Register 8. IF R Divider Address Field (A[3:0]) = 1000 Bit Name 26 D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 Bit Name 17:13 Reserved 12:0 RIF 0 D9 0 D8 D7 D6 D5 RIF Function Program to zero. R Divider for IF Synthesizer. RIF can be any value from 7 to 8189 if KP1 = 00 8 to 8189 if KP1 = 01 10 to 8189 if KP1 = 10 14 to 8189 if KP1 = 11 Rev. 1.0 D4 D3 D2 D1 D0 Si4136 Pin Descriptions: Si4136 SCLK 1 24 SENB SDATA 2 23 VDDI GNDR 3 22 IFOUT GNDR 4 21 GNDI NC 5 20 IFLB GNDR 6 19 IFLA NC 7 18 GNDD GNDR 8 17 VDDD GNDR 9 16 GNDD GNDR 10 15 XIN RFOUT 11 14 PWDNB VDDR 12 13 AUXOUT Pin Number(s) Name Description 1 SCLK Serial clock input 2 SDATA Serial data input 3, 4, 6, 8–10 GNDR Common ground for RF analog circuitry 5, 7 NC No connect 11 RFOUT Radio frequency (RF) output of the selected RF VCO 12 VDDR Supply voltage for the RF analog circuitry 13 AUXOUT Auxiliary output 14 PWDNB Power down input pin 15 XIN Reference frequency amplifier input 16, 18 GNDD Common ground for digital circuitry 17 VDDD Supply voltage for digital circuitry 19, 20 IFLA, IFLB Pins for inductor connection to IF VCO 21 GNDI Common ground for IF analog circuitry 22 IFOUT Intermediate frequency (IF) output of the IF VCO 23 VDDI Supply voltage for IF analog circuitry 24 SENB Enable serial port input Rev. 1.0 27 S i4 13 6 Ordering Guide 28 Ordering Part Number Description Temperature Si4136-BT 2.5 GHz/2.3 GHz/IF OUT –40 to 85oC Rev. 1.0 Si4136 Package Outline Figure 18 illustrates the package details for the Si4136. Table 12 lists the values for the dimensions shown in the illustration. E1 θ2 E S R1 R θ1 L e L1 θ3 D A2 c A b A1 Figure 18. 24-pin Thin Small Shrink Outline Package (TSSOP) Table 12. Package Diagram Dimensions Symbol A A1 A2 b c D e E E1 L L1 R R1 S θ1 θ2 θ3 Min — 0.05 0.80 0.19 0.09 4.85 4.30 0.45 0.09 0.09 0.20 0 Millimeters Nom 1.10 — 1.00 — — 5.00 0.65 BSC 6.40 BSC 4.40 0.60 1.00 REF — — — — 12 REF 12 REF Rev. 1.0 Max 1.20 0.15 1.05 0.30 0.20 5.15 4.50 0.75 — — — 8 29 S i4 13 6 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: [email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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