SUMMIT SMH4042A MICROELECTRONICS, Inc. Distributed Power Hot-Swap Controller for CompactPCI Preliminary FEATURES l Full Voltage Control for Hot Swap Applications w 15V High Side Driver Generation Allows use of Low On Resistance N-Channel FETs w Under-Voltage Lockout l Flexible Reset Control w Low Voltage Resets w Host Reset Filtering w Soft Reset w Electronic Circuit Breakers l Adjustable Power On Slew Rate w Card Insertion Detection l Suppoprts Mixed Voltage Cards w Host VCC Detection l Two Wire I2C Serial Data Interface w Card Voltage Sequencing w 4k-Bit E2PROM Memory FUNCTIONAL BLOCK DIAGRAM 28 BD_SEL1# VCC BD_SEL2# 3 8 10 11 19 18 24 1 13 12 ISLEW A0 1VREF A1 VGATE3 A2 SCL EEPROM Memory Array VGATE5 5 22 27 SDA CBI_3 CBI_5 – LOCAL_PCI_RST + LOCAL_PCI_RST# 20 9 ASSOCIATE MEMBER – + SGNL_VLD# 16 CONTROL + – 23 HST_3V_MON HEALTHY# 15 + – DRVREN# 21 CARD_3V_MON + FAULT# – 25 CARD_5V_MON 2 4 + – 1.25V 7 17 6 PWR_EN PCI_RST# VSEL GND 14 ©SUMMIT MICROELECTRONICS, Inc., 2003 • 1717 Fox Drive, San Jose, CA 95131 • Phone 408-436-9890 • FAX 408-436-9897 • www.summitmicro.com Characteristics subject to change without notice 2070 9.1 5/27/03 1 SMH4042A DESCRIPTION The SMH4042A is a fully integrated hot swap controller that provides complete power control for add-in cards ranging in use for basic hot swap systems to high availability CompactPCI systems. It detects proper insertion of the card and senses valid supply voltage levels at the backplane. Utilizing external low on-resistance N-channel MOSFETs, card power is ramped by two high-side driver outputs that are slew-rate limited at 250V/s. The SMH4042A continuously monitors the host supplies, the add-in card supplies and the add-in card current. If the SMH4042A detects the current is higher than the programmed value it will shut down the MOSFETs and issue a fault status back to the host. The internal 512 × 8 E2PROM can be used as configuration memory for the individual card or as general purpose memory. The proprietary Data Download mode provides a more direct interface to the E2PROM, simplifying access by the add-in card’s controller or ASIC. Programming of configuration, control and calibration values by the user can be simplified with the interface adapter and Windows GUI software obtainable from Summit Microelectronics. PIN CONFIGURATION CBI_5 DRVREN# ISLEW FAULT# 1VREF VSEL PWR_EN A0 LOCAL_PCI_RST# A1 A2 BD_SEL2# BD_SEL1# GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC VGATE5 nc CARD_5V_MON CBI_3 HST_3V_MON VGATE3 CARD_3V_MON LOCAL_PCI_RST SCL SDA PCI_RST# SGNL_VLD# HEALTHY# 2070 PCon 2 2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. SMH4042A PIN DESCRIPTIONS A0 (8) HST_3V_MON (23) Address 0 is not used by the memory array. It can be connected to ground or left floating. It must not be connected VCC. This input monitors the host 3.3V supply and it is used as a reference for the circuit breaker comparator. If VCC3 falls below VTRIP then SGNL_VLD# is de-asserted, the high side drivers are disabled, and LOCAL_PCI_RST# is asserted. A1, A2 (10, 11) Address inputs 1 and 2 are used to set the two-bit device address of the memory array. The state of these inputs will determine the device address for the memory if it is on a two-wire bus with multiple memories with the same device type identifier. ISLEW (3) A Diode-connected NFET input. It may be used to adjust the 250V/s default slew rate of the high-side driver outputs. SCL (19) PCI_RST# (17) The SCL input is used to clock data into and out of the memory array. In the write mode, data must remain stable while SCL is HIGH. In the read mode, data is clocked out on the falling edge of SCL. A TTL level reset input signal from the host interface. A high to low transition (held low longer than 40ns) will initiate a reset sequence. The LOCAL_PCI_RST# and LOCAL_PCI_RST outputs will be driven active for a minimum period of tPURST. If the PCI_RST# input is still held low after tPURST times out the reset outputs will continue to be driven until PCI_RST# is released. SDA (18) The SDA pin is a bidirectional pin used to transfer data into and out of the memory array. Data changing from one state to the other may occur only when SCL is LOW, except when generating START or STOP conditions. SDA is an open-drain output and may be wire-ORed with any number of open-drain outputs. CARD_3V_MON (21) This input monitors the card-side 3.3V supply. If the input falls below VTRIP then the HEALTHY# and SGNL_VLD# outputs are de-asserted and the reset outputs are driven active. CARD_5V_MON (25) This input monitors the card-side 5V supply. If the input falls below VTRIP then the HEALTHY# and SGNL_VLD# outputs are de-asserted and the reset outputs are driven active. CBI_3 (24) CBI_3 is the circuit breaker input for the low supply. With a series resistor placed in the supply path between VCC3 and CBI_3, the circuit breaker will trip whenever the voltage across the resistor exceeds 50mV. CBI_5 (1) CBI_5 is the circuit breaker input for the supply voltage. With a series resistor placed in the supply path between the 5V early power and CBI_5, the circuit breaker will trip whenever the voltage across the resistor exceeds 50mV. SUMMIT MICROELECTRONICS, Inc. 2070 PWR_EN (7) A TTL level input that allows the host to enable or disable the power to the individual card. During initial power up this signal would start in a low state, and then be driven high during software initialization. If this signal is driven low then the power supply control outputs will be driven into the inactive state and the reset signals asserted. In a “non-High Availability” system this input can be tied high. The PWR_EN input is also used to reset the SMH4042A circuit breakers. After an over-current condition is detected the VGATE outputs can be turned back on by first taking PWR_EN low then returning it high. VSEL (6) A TTL level input used to determine which of the host power supply inputs will be monitored for valid voltage and reset generation. This is a static input and the pin should be tied to VCC or ground through a resistor. VSEL is high for 3.3V power. VSEL is low for 5V or mixed mode power. VCC (28) The power supply input. It is monitored for power integrity. If it falls below the 5V sense threshold (VTRIP) and the VSEL input is low then the SGNL_VLD# and HEALTHY# signals are de-asserted, the high side drivers disabled, and reset outputs asserted. On a CompactPCI board this must be connected to early power. 9.1 5/27/03 3 SMH4042A GND (14) LOCAL_PCI_RST# (9) Power supply return line. Ground should be applied at the same time as early power. BD_SEL1#, BD_SEL2# (13, 12) These are active low TTL level inputs with internal pullups to VCC. When pulled low they indicate full board insertion. On the host side the signals should be directly tied to ground. In a “High Availability” application these inputs can be the last pins to mate with the backplane. Alternatively, they can be actively driven by the host, or be connected to switches interfaced to the board ejectors, or any combination. Regardless, both inputs must be low before the SMH4042A will begin to turn on the backend voltage. An open-drain active-low output. It is used to reset the backend circuitry on the add-in card. It is active whenever the card-side monitor inputs are below their respective VTRIP levels. It may also be driven low by a low input on the PCI_RST# pin. LOCAL_PCI_RST (20) An open-drain (PFET) active-high output. It operates in parallel with LOCAL_PCI_RST#, providing an active high reset signal which is required by many 8051 style MCUs. It is active whenever the card-side monitor inputs are below their respective VTRIP levels. It may also be driven active by a low input on the PCI_RST# pin. SGNL_VLD# (16) DRVREN# (2) An open-drain, active-low output that indicates the status of the 3 volt and 5 volt high side driver outputs (VGATE5 and VGATE3). This signal may also be used as a switching signal for the 12 volt supply. FAULT# (4) An open-drain, active-low output. It will be driven low whenever an over-current condition is detected. It will be reset at the same time that the VGATE outputs are turned back on after a reset from the host on the PWR_EN signal. HEALTHY# (15) An open-drain, active-low output indicating card side power inputs are above their reset trip levels. An open-drain, active-low output that indicates card side power is valid and the internal card side PCI_RST# timer has timed out. VGATE3 (22) A slew rate limited high side driver output for the 3.3V external power FET gate. The output-voltage is generated by an on-board charge pump. VGATE5 (27) A slew rate limited high side driver output for the 5V external power FET gate. The output voltage is generated by an on-board charge pump. 1VREF (5) This output provides a 1V reference for pre-charging the bus signal pins. Implementing a simple unity-gain amplifier circuit will allow pre-charging a large number of pins. RECOMMENDED OPERATING CONDITIONS* ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ......................... –55°C to 125°C Storage Temperature .............................. –65°C to 150°C Lead Solder Temperature (10 secs) ..................... 300 °C Terminal Voltage with Respect to GND: CARD_3V_MON, CARD_5V_MON, HST_3V_MON, SGNL_VLD#, HEALTHY#, LOCAL_PCI_RET#, VCC ........................................ 7V VGATE3, VGATE5, DRVREN# .................. 16V RESET ............................................ VCC + 0.7V All Others ........................................ VCC + 0.7V Junction Temperature..........................................150°C ESD Rating per JEDEC……………………………..2000V Latch-Up testing per JEDEC………………......+/- 100mA 4 2070 Temperature Range (Industrial)...……....-40° C to +85°C (Commercial)...……....-5° C to +70°C Supply Voltage………………….....….………2.7V to 5.5V Package Thermal Resistance (θ JA) 28 Lead SOIC/SSOP...…………………………80oC/W Moisture Classification Level 1 (MSL 1) per J-STD- 020 RELIABILITY CHARACTERISTICS Data Retention……………………………..…..100 Years Endurance……………………….……….100,000 Cycles Note * - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. SMH4042A DC OPERATING CHARACTERISTICS (Over Recommended Operating Conditions; Voltages are relative to GND) Symbol VCC ICC1 ICC2 Parameter Supply voltage Power Supply Current VTRIP (2) Threshold Levels Conditions (2) (1) Min. Typ. Max. 1 Units V Operating Writing 500 µA 3 mA VCC5 A 4.250 4.375 4.500 V VCC5 B 4.500 4.625 4.750 V HST_3V_MON G 2.57 2.65 2.72 V HST_3V_MON H 2.72 2.80 2.87 V HST_3V_MON K 2.87 2.95 3.00 V HST_3V_MON L 3.00 3.10 3.17 V CARD_5V_MON M VCC5 + 50mV V CARD_5V_MON N VCC5 – 50mV V CARD_3V_MON M HST_3V_MON + 50mV V CARD_3V_MON N HST_3V_MON – 50mV V 7 mV VTRHYST Trip Point Hysteresis ILI Input Leakage Current 2 µA ILO Output Leakage Current 10 µA VIL Input Low Voltage –0.1 0.8 V VIH Input High Voltage 2 VCC + 1V V VOL Output Low Voltage VCC = 5.0V, IOL = 2.1mA 0.4 V VOH Output High Voltage VCC = 5.0V, IOH = –400µA VOLRS LOCAL_PCI_RST# Low IOL = 3.2mA VOHRS RESET High IOH = –800µA VOHVG3 VGATE3 High IOH = 5µA 12 13 15 V VOHVG5 VGATE5 High IOH = 5µA 13 14 15 V VREF Reference Output Voltage No Load 0.95 1.00 1.05 V VCB Circuit Breaker Trip Voltage (3) 40 50 60 mV 2.4 V 0.4 VCC – 0.75V V V 2037 Elect Table 2.0 Notes: (1) The SMH4042A will drive the Reset outputs and voltage control signals throughout the operating range of 1V to 5.5V. The balance of the logic will not be guaranteed operational unless VCC is greater than 2.7V. (2) A, B,G, H, K. L, M, & N refer to the Part Number Suffix. (3) For TA = –10ºC to 85ºC. SUMMIT MICROELECTRONICS, Inc. 2070 9.1 5/27/03 5 SMH4042A DEVICE OPERATION Power-Up Sequence The SMH4042A is an integrated power controller for any hot swappable add-in card. It provides all the signals and control functions to be compatible with CompactPCI Hot Swap requirements for basic hot swap systems, full hot swap boards, and high availability systems. Insertion Process As the add-in board is inserted into the backplane, physical connections are made with the chassis in order to properly discharge any voltage potentials to ground. The board will first contact the long pins on the backplane that provide early power (5V, 3.3V and ground). Depending upon the board configuration, early power should be routed to the VCC pin of the SMH4042A. As soon as power is applied the SMH4042A will assert the reset outputs to the backend circuits, turn off the VGATE3 and VGATE5 outputs (disabling the external power FETs) and assert 1VREF. This signal can be used to pre-charge the I/O pins before they begin to mate with the bus signals. The open collector HEALTHY# output will be de-asserted. It should be actively pulled high by an external pull-up resistor (minimum 10kΩ). The next pins to mate are the I/Os, and the balance of the power pins if they are not already mated. The I/Os will have been pre-charged by the 1VREF output. The BD_SEL# pins are the last inputs to be driven to their true state. In most systems these will most likely be driven to ground when the short pins are mated. This would indicate the card is fully inserted and the power-up sequence can begin. If, however, the design is based on high availability requirements, the two pins can be actively driven by the host or combined with a switch input indicating the ejector handles are fully engaged. Sequencing Once the proper card insertion has been assured the SMH4042A will check the status of the Power Enable signal from the host. This input can be used to power down individual cards on the bus via software control. It must by held high in order for the SMH4042A to enable power sequencing to the card. When these conditions have been met, the SMH4042A will drive the VGATE3 and VGATE5 outputs to turn on the external 3 volt and 5 volt power FETs. The slew rate of these outputs is controlled to a slew rate of 250V/s. Different slew rates can be accommodated by either adding an additional capacitor between the MOSFET gate 6 2070 and ground or by injecting current into the ISLEW input. All circuitry on the card is held in a reset condition until the 5V (or 3.3V) supply is stable and the reset interval timer has timed out the 150ms reset time. At this point, the reset signals are de-asserted, and proper operation of the card commences. See Figure 1, Table 1, and Flow Chart 1. The SMH4042A will monitor the card’s backend voltages. Once they are at or above the card VTRIP levels the SMH4042A will drive the HEALTHY# output. Card Removal Process The card removal process operates in the opposite sequence. For non-high-availability cards the action of card removal disconnects the BD_SEL# (short pins) from ground and the SMH4042A will instantly shutdown the VGATE outputs, change the HEALTHY# status, and assert the LOCAL_PCI_RST# output. Because connectors to the host backplane employ staggered pins, power will still be applied to the SMH4042A and the I/O interface circuits. The LOCAL_PCI_RST# signal will place the interface circuits into a high impedance condition. The pre-charge voltage will be applied to the I/Os enabling a graceful disengagement from the active bus. Once the I/O pins are free of the backplane, power can be removed from the SMH4042A and other early power devices by releasing the long pins. The removal process is slightly different for a highavailability system. As the ejector handle is rotated the ejector switch will open, causing a change of state that will activate the ENUM# signal to the host. In response to this notification the host will de-assert a hardware controlled BD_SEL# signal. This action will turn on an indicator LED on the card, notifying the operator it is now safe to proceed with the removal of the card. The sequence will then follow that outlined for the non-high-availability removal process. Power Configurations The SMH4042A can be used in 5V-only, 3.3V-only and mixed voltage systems. For systems with a single power supply, connect VCC and HST_3V_MON together to the bus power line. Also connect CARD_3V_MON and CARD_5V_MON together to the card side power. Now the state of VSEL determines the reset level that will be used to signal valid power. For 3.3V systems tie VSEL to VCC, for 5V systems tie VSEL to ground. 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. SMH4042A VTRIP VCC & HST_3V_MON VRVALID LOCAL_PCI_RST# RESET tHSE BD_SEL1# & BD_SEL2# tSLEW VGATE3 & VGATE5 VOHVG DRVREN# CARD_3V_MON & CARD_5V_MON VTRIP tPURST HEALTHY# SGNL_VLD# 2070 Fig01 Figure 1. Card Insertion Timing Diagram Symbol Description Min. Typ. Max. Units tVTPD VTRIP to Power Down Delay, Host Voltage Input 1 5 µs tVTR VTRIP to Reset Output Delay, Card Voltage Input 1 5 µs tPRLPR PCI_RST# to LOCAL_PCI_RST# 0.1 1 µs VRVALID Local Reset Output Valid tSLEW Slew Rate tHSE BD_SEL# to Power On Delay, BD_SEL Noise Filter 100 tPURST Reset Timeout 100 tGLITCH Glitch Reject Pulse Width tOCF Over-Current to Fault# 1 µs tOCVG Over-Current to VGATE Off 1 µs Circuit Breaker Time Constant, Power up 4 µs Circuit Breaker Time Constant, Operating 16 µs tCBTC 1 V 250 V/s 150 200 ms 150 200 ms 40 ns 2037 Table01 2.0 Table 1. Card Insertion Timing SUMMIT MICROELECTRONICS, Inc. 2070 9.1 5/27/03 7 SMH4042A VCC ≥ 1V Monitor VCC & HOST_3V_MON Input Level Assert Outputs LOCAL_PCI_RST & LOCAL_PCI_RST# OK Turn On Signals DRVREN#, VGATE3 & VGATE5 Shut Off Signals DRVREN#, HEALTHY#, SGNL_VLD#, VGATE3 & VGATE5 Monitor CARD_3V_MON & CARD_3V_MON: ≥ VTRIP? Monitor BD_SEL1# & BD_SEL2# For Insertion LOW HIGH NO YES LOW Turn On HEALTHY# Start Timer tPURST Monitor VSEL Input Level LOW HIGH tPURST Timeout? NO YES LOW Monitor HOST_3V_MON Input Level OK PCI_RST Released? NO YES Release Resets Turn On SGNL_VLD 2070 Flow01 Flow Chart 1. Sequence Diagram 8 2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. SMH4042A MONITORING POWER SUPPLY HEALTH MONITOR INPUTS The SMH4042A has a total of six comparators that are used to monitor the health of the host platform supplies and the card-side (backend) voltages. In hot swap applications each supply going to the backend logic needs to be monitored at three points. The first point is at the source on the host connector, VCC and HST_3V_MON. If this voltage is not within specification, then the down stream sequencing of powering-on the backend logic will not proceed. The next stage (the CBI inputs) is one step closer to the backend logic to monitor the current flowing into the backend logic. This can not exceed the specification; however, If it does, then the SMH4042A must turn off the source to the backend logic. The CARD_5V_MON and CARD_3V_MON inputs are used to sense the actual voltage level in the backend logic. If either comparator detects a low voltage condition the backend logic will be placed in a reset condition (LOCAL_PCI_RST# asserted), but the VGATE outputs will remain active so long as the host voltage and current sense are valid. VCC or HST_3V_MON VTRIP VCC vs. HST_3V_MON The VCC input is the supply input and in a CompactPCI application this pin must connect to an early power pin on the host connector. The HST_3V_MON input is strictly a voltage monitoring input, it is not a supply input. The operating supply voltage range on the VCC pin is 2.7V to 5.5V, but it will only monitor a 5V supply. This is not an issue with a dual supply application. But in a single supply application these two pins must be shorted and VSEL conditioned. Programmable VTRIP Thresholds The host voltage monitors and the backend voltage monitors are programmable (by the factory) and provide a number of options to the end user. The VCC monitor VTRIP level can be selected for either a 5% or 10% supply with default values of 4.25V or 4.625V. The HST_3V_MON VTRIP level can be programmed to 2.65V, 2.8V, 2.95V and 3.1V. The CARD_5V_MON and CARD_3V_MON thresholds are set in relation to their corresponding host voltage monitor thresholds. Their offset can be either +50mV or –50mV. This allows the designer to select +50mV if they want a collapse in the backend voltage to trigger a local reset condition prior to the host supply collapsing and powering down the board without warning. Alternatively they can choose –50mV to trigger a board shutdown based on the host power supply falling out of spec. Also see Figure 2 tVTPD DRVREN# & SGNL_VLD# tCBTC CBI_3 or CBI_5 VGATE3 & VGATE5 CARD_3V_MON or CARD_5V_MON FAULT# VTRIP VGATE3 & VGATE5 HEALTHY# & LOCAL_PCI_RST# tVTR PCI_RST# 2070 Fig03 2070 Fig02 Figure 2. Loss-of-Voltage Timing Sequence SUMMIT MICROELECTRONICS, Inc. 2070 Figure 3. Circuit Breaker Timing Sequence 9.1 5/27/03 9 SMH4042A Over-current Circuit Breaker The SMH4042A provides a circuit breaker function to protect against short circuit conditions or exceeding the supply limits. By placing a series resistor between the host supply and the CBI pins, the breakers will trip whenever the voltage drop across the series resistor is greater than 50mV for more than 16µs. The over-current detection circuit was designed to maximize protection while minimizing false alarms. The most critical period of time is during the power-on sequence when the backend circuits are first being energized. If the card has a faulty component or shorted traces, the time to shut off should be minimal. However, if the board has been operational for a long period of time the likelihood of a catastrophic failure occurring is quite low. Therefore, the SMH4042A employs two different sampling schemes. During power-up the device will sample the current every 500ns. If eight consecutive over-current conditions are detected the VGATE outputs will immediately be shut down. This provides an effective response time of 4µs. During normal operation, after the FETs have been turned on, the sampling rate will be adjusted to 2µs, thus providing an effective response time of 16µs. Also see Figure 3. RESET CONTROL While in the power sequencing mode, the reset outputs are the last to be released. When they are released all conditions of a successful power-up sequence must have been met: 1) VCC and HST_3V_MON are at or above their respective VTRIP levels; 2) BD_SEL# inputs are low; 3) CARD_3V_MON and CARD_5V_MON are at or above their respective trip levels; 4) PWR_EN is high; and 5) PCI_RST is high. The PCI-RST# input must be high for the reset outputs to be released. Assuming all of the conditions listed above have been met and PCI_RST# is high and tPURST has expired, a low input of greater than 40ns duration on the PCI_RST# input will initiate a reset cycle. The duration of the reset cycle will be determined by the PCI_RST# input. If PCI_RST# low is shorter than tPURST, the reset outputs will be driven active for tPURST. If PCI_RST# is longer than tPURST the reset outputs will remain active until PCI_RST# is released. Also see Figure 4. PCI_RST# tPRLPR tPURST tPURST LOCAL_PCI_RST# LOCAL_PCI_RST 2070 Fig04 Figure 4. Host-Initiated Reset Timing 10 2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. SMH4042A BUS INTERFACE GENERAL DESCRIPTION The I2C bus is a two-way, two-line serial communication between different integrated circuits. The two lines are: a serial Data line (SDA) and a serial Clock line (SCL). All Summit Microelectronics parts support a 100kHz clock rate, and some support the alternative 400kHz clock. tR tHIGH tF Check Table 2 for the value of fSCL. The SDA line must be connected to a positive supply by a pull-up resistor located on the bus. Summit parts have a Schmitt input on both lines. See Figure 5 and Table 2 for waveforms and timing on the bus. One bit of Data is transferred during each Clock pulse. The Data must remain stable when the Clock is high. tLOW SCL tSU:SDA tHD:DAT tHD:SDA tSU:DAT tSU:STO tBUF SDA In tAA tDH SDA Out 2070 Fig05 Figure 5. I2C Timing Diagram Symbol Parameter Conditions Min. Typ. Max. Units 100 kHz fSCL SCL clock frequency tLOW Clock low period 4.7 µs tHIGH Clock high period 4.0 µs tBUF Bus free time (1) 4.7 µs tSU:STA Start condition setup time 4.7 µs tHD:STA Start condition hold time 4.0 µs tSU:STO Stop condition setup time 4.7 µs tAA Clock edge to valid output SCL low to valid SDA (cycle n) 0.2 tDH Data Out hold time SCL low (cycle n+1) to SDA change 0.2 tR SCL and SDA rise time (1) 1000 ns tF SCL and SDA fall time (1) 300 ns tSU:DAT Data In setup time 250 ns tHD:DAT Data In hold time 0 ns TI Noise filter SCL and SDA t Write cycle time 0 Before new transmission Noise suppression Table 2. I2C AC Operating Characteristics 2070 9.1 5/27/03 µs µs 100 ns 5 WR Note 1 - Guaranteed by Design SUMMIT MICROELECTRONICS, Inc. 3.5 ms 2037 Table02 2.0 11 SMH4042A Start and Stop Conditions Both Data and Clock lines remain high when the bus is not busy. Data transfer between devices may be initiated with a Start condition only when SCL and SDA are high. A highto-low transition of the Data line while the Clock line is high is defined as a Start condition. A low-to-high transition of the Data line while the Clock line is high is defined as a Stop condition. See Figure 6. 1 SCL 2 3 9 8 SDA Trans SDA Rec ACK 2070 Fig07 Figure 7. Acknowledge Timing START Condition STOP Condition leave the Data line high for a NACK. This will cause the Summit part to stop sending data, and the Master will issue a Stop on the clock pulse following the NACK. SCL In the case of a Write to a Summit part the Master will send a Stop on the clock pulse after the last Acknowledge. This will indicate to the Summit part that it should begin its internal non-volatile write cycle. SDA In 2070 Fig06 Figure 6. I2C Start and Stop Timing Protocol The protocol defines any device that sends data onto the bus as a Transmitter, and any device that receives data as a Receiver. The device controlling data transmission is called the Master, and the controlled device is called the Slave. In all cases the Summit Microelectronic devices are Slave devices, since they never initiate any data transfers. Acknowledge Data is always transferred in 8-Bit bytes. Acknowledge (ACK) is used to indicate a successful data transfer. The Transmitting device will release the bus after transmitting eight bits. During the ninth clock cycle the Receiver will pull the SDA line low to Acknowledge that it received the eight bits of data (See Figure 7). The termination of a Master Read sequence is indicated by a non-Acknowledge (NACK), where the Master will leave the Data line high. In the case of a Read from a Summit part, when the last byte has been transferred to the Master, the Master will Basic Read and Write The first byte from a Master is always made up of a seven bit Slave address and the Read/Write bit. The R/W bit tells the Slave whether the Master is reading data from the bus or writing data to the bus (1 = Read, 0 = Write). The first four of the seven address bits are called the Device Type Identifier (DTI). The DTI for the SMH4042A is 1010BIN. The next two bits are used to select one-of-four possible devices on the bus. The next bit is the block select bit. The SMH4042A will issue an Acknowledge after recognizing a Start condition and its DTI. In the Read mode the SMH4042A transmits eight bits of data, then releases the SDA line, and monitors the line for an Acknowledge signal. If an Acknowledge is detected, and no Stop condition is generated by the Master, the SMH4042A will continue to transmit data. If an Acknowledge is not detected (NACK), the SMH4042A will terminate further data transmission. See Figure 9. In the Write mode the SMH4042A receives eight bits of data, then generates an Acknowledge signal. It will continue to generate ACKs until a Stop condition is generated by the Master. See Figure 10. SCL 1 2 3 4 5 6 7 8 9 SDA 1 0 1 0 x x x R/W ACK 2070 Fig08 Figure 8. Typical Master Address Byte Transmission 12 2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. SMH4042A Random Address Read Random address Read operations allow the Master to access any memory location in a random fashion. This operation involves a two-step process. First, the Master issues a write command which includes the start condition and the Slave address field (with the R/W bit set to Write) followed by the address of the word it is to read. This procedure sets the internal address counter of the SMH4042A to the desired address. After the word address Acknowledge is received by the Master, it immediately reissues a start condition followed by another Slave address field with the R/W bit set to Read. The SMH4042A will respond with an Acknowledge and then transmit the 8 data bits stored at the addressed location. At this point the Master sets SDA high (NACK) and generates a Stop condition. The SMH4042A discontinues data transmission and reverts to its standby power mode. Master S T A R T Sequential Read Sequential Reads can be initiated as either a current address Read or a random access Read. The first word is transmitted as with the other byte read modes (current address byte Read or random address byte Read). However, the Master now responds with an Acknowledge, indicating that it requires additional data from the SMH4042A. The SMH4042A continues to output data for each Acknowledge received. The Master terminates the sequential Read operation with a NACK and issues a Stop condition. During a sequential read operation the internal address counter is automatically incremented with each Acknowledge signal. For read operations all address bits are incremented, allowing the entire array to be read using a single Read command. After a count of the last memory address the address counter will roll-over and the memory will continue to output data. 1 0 1 0 x x x R x x x x x x x x SDA N A C K A C K R / W x x A C K Slave S T O P Optional x x 2070 Fig09 Figure 9. Basic Read Master SDA Slave S T A R T S T O P R / W 1 0 1 0 x x xW x x x x x x x x x x A C K A C K x x 2070 Fig10 A C K Figure 10. Basic Write SUMMIT MICROELECTRONICS, Inc. 2070 9.1 5/27/03 13 SMH4042A MEMORY OPERATION WRITE OPERATIONS Write Cycle In Progress The SMH4042A allows two types of Write operations to its a 512 x 8 array: byte Write and page Write. A byte Write operation writes a single byte during the nonvolatile Write period (tWR). The page Write operation allows up to 16 bytes in the same page to be written during tWR. Issue Start Byte Write After the slave address is sent (to identify the slave device, and a Read or Write operation), a second byte is transmitted which contains the 8 bit address of any one of the 512 words in the array. Upon receipt of the word address the SMH4042A responds with an Acknowledge. After receiving the next byte of data, it again responds with an Acknowledge. The master then terminates the transfer by generating a Stop condition, at which time the SMH4042A begins the internal write cycle. The SMH4042A inputs are disabled while the internal write cycle is in progress, and the device will not respond to any requests from the Master. Issue Stop Issue Slave Address and R/W = 0 ACK Returned No Yes Next Operation a Write? No Yes Page Write The SMH4042A is capable of a 16-byte page Write operation. It is initiated in the same manner as the byte-Write operation, but, instead of terminating the Write cycle after the first data word, the Master can transmit up to 15 more bytes of data. After the receipt of each byte the SMH4042A will respond with an Acknowledge. Issue Address Issue Stop Proceed With Write Await Next Command The SMH4042A automatically increments the address for subsequent data words. After the receipt of each word the low order address bits are internally incremented by one. The high order bits of the address byte remain constant. Should the Master transmit more than 16 bytes, prior to generating the Stop condition, the address counter will roll over and the previously written data will be overwritten. As with the byte-Write operation, all inputs are disabled during the internal write cycle. Refer to Figure 5 for the address, Acknowledge and data transfer sequence. READ OPERATIONS Acknowledge Polling When the SMH4042A is performing an internal Write operation it will ignore any new Start conditions. Since the device will only return an acknowledge after it accepts the Start, the part can be continuously queried until an acknowledge is issued, indicating that the internal write cycle is complete. See Flow Chart 2 for the proper sequence of operations for polling. Current Address Read The SMH4042A contains an internal address counter which maintains the address of the last word accessed, incremented by one. If the last address accessed (either a Read or Write) was to address location n, the next Read operation would access data from address location n+1 and increment the current address pointer. When the SMH4042A receives the Slave address field with the R/W 14 2070 2070 Flow02 Flow Chart 2. Polling There are two different read options: 1. Current Address Byte Read 2. Random Address Byte Read 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. SMH4042A bit set to “1” it issues an acknowledge and transmits the 8Bit word stored at address location n+1. The current address byte Read operation only accesses a single byte of data. The Master holds the SDA line high (NACK) and generates a Stop condition. At this point the SMH4042A discontinues data transmission. Random Address Read Random address Read operations allow the Master to access any memory location in a random fashion. This operation involves a two-step process. First, the Master issues a Write command which includes the Start condition and the Slave address field (with the R/W bit set to Write) followed by the address of the word it is to read. This procedure sets the internal address counter of the SMH4042A to the desired address. After the word address acknowledge is received by the Master, the Master immediately reissues a Start condition followed by another Slave address field with the R/W bit set to Read. The SMH4042A will respond with an Acknowledge and then transmit the 8 data bits stored at the addressed location. At this point the Master issues a NACK and generates the Stop condition. The SMH4042A discontinues data transmission and reverts to its standby power mode. SUMMIT MICROELECTRONICS, Inc. 2070 Sequential Read Sequential Reads can be initiated as either a current address Read or a random access Read. The first word is transmitted as with the other byte Read modes (current address byte Read or random address byte Read); however, the Master now responds with an Acknowledge, indicating that it requires additional data from the SMH4042A. The SMH4042A continues to output data for each Acknowledge received. The Master terminates the sequential Read operation with a NACK and a Stop. During a sequential Read operation the internal address counter is automatically incremented with each Acknowledge signal. For Read operations all address bits are incremented, allowing the entire array to be read using a single Read command. After a count of the last memory address the address counter will roll over and the memory will continue to output data. Data Download The SMH4042A supports a proprietary mode of operation specifically for the Hot Swap environment. After a power on reset the internal address pointer is reset to 00. The host or ASIC then only needs to issue a Read command and then sequentially clock out data starting at address 00. 9.1 5/27/03 15 SMH4042A APPLICATIONS DESIGN CONSIDERATIONS FOR A COMPACTPCI BOARD Figure 11 is a generic representation of a CompactPCI board and it illustrates how the SMH4042A is the key component in the board insertion/removal process. The illustrations that follow show in more detail how the various blocks interface to the SMH4042A. Backend Power SwitchingCircuits Bus Interface Backend Power Plane and Logic Current sense resistors P2 Precharge Circuit V(I/O) SGNL_VLD CBI_3 CBI_5 CARD_3V_MON 1Vref ENUM# V(I/O) 5V 3.3V HST_3V_MON V(I/O) CARD_5V_MON Current limiting resistors GND GND VGATE3 VGATE5 V(I/O) eP VCC5 BD_SEL2# eP GND BD_SEL# Capacitance 4.7µf each GND V(I/O) GND RESET LOCAL_PCI_RST# BD_SEL1# GND 3.3V GND, PCI_RST# HEALTHY# 5V 5V +12V, -12V PCI_RST# HEALTHY# SMH4042A P1 2070 Fig11 Figure 11. Diagram of Typical CompactPCI Board Power Busses It is important in the design of the board to ensure the backend logic is isolated from the power control circuits and other early power circuits such as FPGAs and the I/ O interface circuits. In Figure 12 the early power busses for 5V and 3V have series current limiting resistors. These values should be calculated so as to limit the inrush current that will initially charge the capacitive load of the early power circuits. As the card is inserted further, the medium length pins engage and short out the current 16 2070 limiting resistors. Note the placement of the sense (shunt) resistors. They are in series with the power FETs and no voltage drop will be detected across the resistor until VGATE is applied to the power FETs. The sense resistor values are determined by dividing 50mV by the current specification for that supply. It should be noted that there is an inherent delay from VGATE5 turning on to VGATE3 turning on. The typical delay is illustrated in Figure 13. 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. SMH4042A Power Control and Power Plane Isolation Early Power Circuits I/Os Pre-Charge Early Power Long Power Pin Vref VGATE5 CBI_5 SMH4042A Medium Power Pin VCC5 Backend Power Plane CARD_5V_MON CARD_3V_MON Early Power HST_3V_MON Long Power Pin CBI_3 VGATE3 Medium Power Pin Current Limit Resistor Sense Resistor Medium Ground Pin Long Ground Pins 2070 Fig12 Figure 12. Power Control and Power Plane Isolation 15 VOLTAGE (V) 10 VGATE3 VGATE5 5 0 0 10 20 30 40 50 60 TIME (ms) Figure 13. Typical Delay: VGATE5 to VGATE3 SUMMIT MICROELECTRONICS, Inc. 2070 9.1 5/27/03 17 SMH4042A POWER SWITCHING OPTIONS The figures below illustrate four possible methods for wiring the SMH4042A. In the upper left example both power FETs are connected to a single VGATE output. This should be used when the design requires the backend voltages to be powered-up simultaneously. In the upper right example both VGATE outputs are being used so that the 3.3V slew lags the 5V slew. The two bottom circuits illustrate the wiring for single power supply boards. Note how the VSEL pin is biased differently for the two applications. VCC VCC CBI_5 CBI_5 10Ω 10Ω VGATE5 5V ±5% 5A max VGATE5 47nF 5V ±5% 5A max CARD_5V_MON CARD_5V_MON VSEL 3.3V ±0.3V 7.6A max VSEL 3.3V ±0.3V 7.6A max CARD_3V_MON 10Ω CARD_3V_MON 10Ω VGATE3 VGATE3 47nF 47nF CBI_3 0.0065Ω CBI_3 HST_3V_MON 0.0065Ω HST_3V_MON Dual Voltage, Dual Slew Rate Implementation Dual Voltage, Single Slew Rate Implementation VCC VCC CBI_5 CBI_5 VGATE5 VGATE5 CARD_5V_MON CARD_5V_MON 10Ω 5V ±5% 5A max 47nF VSEL VSEL 3.3V ±0.3V 7.6A max CARD_3V_MON CARD_3V_MON 10Ω VGATE3 VGATE3 47nF CBI_3 CBI_3 0.0065Ω HST_3V_MON HST_3V_MON Single 3.3V Implementation Single 5V Implementation Figure 14. Four Power Switching Implementations 18 2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. SMH4042A I/O Buffers Depending upon the application requirements there are a number of silicon solutions that employ low on-resistance CMOS switches. Figure 15 shows one implementation using a QuickSwitch® from Quality Semiconductor. This particular device exhibits very Flat RON characteristics from 0 to 5V. The only drawback is the extra space required for the external pull-up resistors. Early Power SMH4042A – + 1VREF LMV321 SGNL_VLD# Bn An HOST PCI BUS LOCAL PCI BUS OE# Bx Ax IDTQS34XVH245 2070 Fig15 Figure 15. Bus Buffers with External Pull-ups Figure 16 shows another implementation, but the pull-up resistor structure is incorporated in the switch. The circuit also automatically switches the bias voltage out of the circuit as the CMOS switches are enabled. A potential advantage is the ability to place the interface closer to the edge of the card. The board designer should evaluate requirements and design goals to determine the best solution. The bus switches are available from both Texas Instruments and Pericom Semiconductor. Early Power SMH4042A – + 1VREF LMV321 SGNL_VLD# BIASV Bn An Ax SN74CBT6800 or PI5C6800 Bx HOST PCI BUS LOCAL PCI BUS ON# 2070 Fig16 Figure 16. Bus Buffers with Integrated Pull-ups SUMMIT MICROELECTRONICS, Inc. 2070 9.1 5/27/03 19 SMH4042A I/O Pre-charge is accurate and stable prior to the medium length pins making contact. The 1VREF output should be the reference input to a unity gain op amp circuit. Figure 17 is a typical implementation utilizing a common op amp. The CompactPCI specs require the add-in board to precharge the board’s I/Os before making contact with bus pins, and sets the pre-charge voltage at 1V ±0.1V. The SMH4042A provides an accurate 1V reference output that Early Power VCC5 SMH4042A + LMV321 To/From Backplane To/From Buffers or ASIC 1VREF Resistor Array – 2070 Fig17 Figure 17. I/O Pre-charge Circuit SPECIAL CONSIDERATIONS The example application shown in Figure 11 shows both of the BD_SEL inputs being used independently. These two inputs are effectively ANDed internally and they must both be low before any sequencing will proceed. In most design cases the BD_SEL1# connection to an injector switch is redundant and realistically can be grounded. The CompactPCI Hot Swap specification does provide a mechanism for implementing high availability systems using “Full Hot Swap” boards. This capability entails integrating the injector/ejector handle, the blue LED and a board status signal. Section 2.3.2 of the CompactPCI Hot Swap specification states the following. • “A signal (ENUM#) is provided to notify the system host that either a board has been freshly inserted or is about to be extracted.” • “A switch, actuated with the lower ejector handle of the board, is used to signal the insertion or impending extraction of a board.” 20 2070 • “A blue LED, located on the board is illuminated when it is permissible to extract a board.” Figure 18 illustrates a possible implementation of the circuits needed. It should be noted this will require a status register that works in conjunction with the switch logic to generate the ENUM# signal. Notice the blue LED circuit and the active high reset output used to activate a current boost circuit for the LED. The sequence of operations is as follows: • The long pins engage. • Power is supplied to the SMH4042A, the LED and the BD_SEL pull-up resistor. • V(I/O) is either the early 5V or the early 3V, dependent upon the interface operating levels. • The LED is illuminated by LOCAL_PCI_RST# going low. 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. SMH4042A • The medium length pins contact. • point. The ENUM# signal should not be active at this • The board is fully inserted and the injector switch is closed. • ENUM# is driven low. • BD_SEL# makes contact (optional: the pull-up on the board indicates to the host the presence of a board.) • The host responds to the ENUM# signal and drives BD_SEL# low. • This provides the last gating item to the SMH4042A before it will begin the power-on sequence. BD_SEL1# LOCAL_PCI_RST# LOCAL_PCI_RST Power On 3.9kΩ RLIM SMH4042A BD_SEL2# Platform Board 10kΩ PCI_RST# OC ENUM# CARD SWITCH Board Status 2070 Fig19 Figure 18. Full Hot Swap Board/Host Interface SUMMIT MICROELECTRONICS, Inc. 2070 9.1 5/27/03 21 SMH4042A 12V to Backend Logic SMH4042A 0.1µF 1N4148 DRVREN# 10Ω 330kΩ 0.33µF 4.7kΩ 12V –12V to Backend Logic 1.5kΩ 5V 1N4148 0.1µF 1N4148 10Ω 330kΩ 0.33µF 4.7kΩ –12V 2070 Fig19 Figure 19. Using DRVREN# to switch 12V and –12V to the Backend Logic 22 2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. SMH4042A Signal Source Early Power Platform LOCAL_PCI_RST# SMH4042A 1VREF SMH4042A Platform BD_SEL# VGATE3 & VGATE5 SMH4042A DRVREN# SMH4042A HEALTHY# SMH4042A Bus Power Platform Hot Swap Bd. Backend Power Long Pin Mid Length Pin Short Pin Insertion Process Operational Removal 2070 Fig 20 Figure 20. Typical CompactPCI Power On Sequence for a Non-High Availability System SUMMIT MICROELECTRONICS, Inc. 2070 9.1 5/27/03 23 SMH4042A Signal Source Early Power Platform SMH4042A LOCAL_PCI_RST# System Host BD_SEL# SMH4042A VGATE3 & VGATE5 Hot Swap Bd. Backend Power SMH4042A HEALTHY# PCI_RESET# System Host LED ON SMH4042A Hot Swap Bd. Ejector Switch Long Pin Mid Length Pin Short Pin 2070 Fig 21 Figure 21. Typical CompactPCI Power On Sequence for a Full Hot Swap Board Using the S39421 24 2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. SMH4042A of the CompactPCI implementation but they are now resident on the motherboard. The same circuits shown for switching the voltages on the card can also be used for controlling the slot voltages. Although the primary application for the SMH4042A is as a voltage controller for CompactPCI or VME boards, it is versatile enough to be used as a Hot Plug controller on a host PCI card. The functional blocks are similar to those Power Supply DRVREN# +12V and -12V MOSFETs 5V VGATE3 PWR_EN CBI 3 +5V and +3V MOSFETs 3.3V PCI ADD-IN CARD VGATE5 SMH4042A 12V –12V CBI 5 PCI_RST# CARD_3V_MON HOST LOGIC FAULT# CARD_5V_MON LOCAL_PCI_RST# PCI Bus BUFFER HEALTHY# [SGNL_VLD] BUFFERED PCI BUS SLOT CONTROL 2070 Fig22 Figure 22. Diagram for a PCI Hot Plug Slot Implementation SUMMIT MICROELECTRONICS, Inc. 2070 9.1 5/27/03 25 SMH4042A PACKAGES 28 PIN SOIC PACKAGE 0.697 - 0.713 (17.70 - 18.10) Ref. JEDEC MS-013 0.394 - 0.419 (10.00 - 10.65) Inches (Millimeters) 1 0.291 - 0.299 (7.40 - 7.60) 0.010 - 0.029 0.093 - 0.104 (2.35 - 2.65) ´45º (0.25 - 0.75) 0º to 8º max. 0.009 - 0.013 0.016 - 0.050 (0.23 - 0.32) (0.40 - 1.27) 0.05 0.004 - 0.012 (1.27) 0.013 - 0.020 (0.10 - 0.30) (0.33 - 0.51) 28 Pin SOIC 28 PIN SSOP PACKAGE 0.386 - 0.394 (9.80 - 10.00) 0.228 - 0.244 (5.79 - 6.20) Ref. JEDEC MO-137 Pin 1 0.150 - 0.157 (3.81 - 3.99) 0.053 - 0.069 (1.35 - 1.75) 0.059 MAX (1.50) 0.007 - 0.010 (0.18 - 0.25) 0º to 8º max. 0.016 - 0.050 (0.41 - 1.27) 26 2070 0.025 0.008 - 0.012 (0.635) (0.20 - 0.31) 9.1 5/27/03 0.004 - 0.010 (0.10 - 0.25) 28 Pin SSOP SUMMIT MICROELECTRONICS, Inc. SMH4042A ORDERING INFORMATION S u m m it P art N u m b er S U M M IT SM H4042AG S tatus T racking Code (B lank, M S , E S , 01, 02,...) (S um m it Use) xx AYYW W P ackage Designator P in 1 Date Code (Y Y W W ) Lot tracking code (Sum m it use) D rawing not to scale ORDERING INFORMATION SM H4042A G S u m m it P a rt N u m b e r Package G =28 L ea d S S O P S =2 8 Le ad S O IC V T R IP V C C 5 A =4 .3 75 V B =4 .6 25 V SUMMIT MICROELECTRONICS, Inc. 2070 9.1 5/27/03 A G M V T R IP O F F S E T M =+50 m V N =-50 m V V T R IP H S T _ 3 V _ M O N G =2.6 5 V H =2 .8 0V K =2 .9 5V L =3.10 V 27 SMH4042A NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. This document supersedes all previous versions. © Copyright 2003 SUMMIT Microelectronics, Inc. I2C is a trademark of Philips Corporation. PICMG & CompactPCI are trademarks of the PCI Industrial Computer Manufacturer's Group. 28 2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc.