SUMMIT SMT4214

SMT4214
Preliminary Information1 (See Last Page)
Expandable Four-Rail Tracking Manager
FEATURES & APPLICATIONS
INTRODUCTION
• Programmable Tracking Function
• Programmable Voltage Monitoring of 4 or more
Independent Supplies
• Programmable Under-Voltage Thresholds
• Provides Soft Start, Reset, IRQ and Force
Shutdown functions
• Minimizes Supply Differential During Power-on
and Power-off
• Operates From Any One of Four Supply
Voltages
• Easily Expandable to Control up to 32 Supplies
• Packaged in a 28 Lead SSOP
The SMT4214 is a fully integrated programmable
voltage manager IC, providing supervisory functions
and tracking control for up to four independent power
supplies. The four internal managers perform the
following functions: Monitor source (bus-side) voltages
for under-voltage conditions, monitor back end (cardside) voltages for under-voltage conditions, insure
voltage of the card-side tracks within the specified
parametric limits, and provides supply status
information to a host processor.
The
SMT4214
incorporates
nonvolatile
programmable circuits for setting all of the monitored
thresholds for each manager. Individual functions are
also programmable allowing interrupts or reset
conditions to be generated by user-defined
combinations of events.
Applications
• Multi-voltage supply rail manager for
•
Telecom Infrastructure
•
Compact PCI
•
Servers
• Multi-voltage Network Processors, DSPs,
ASICs
Programming of configuration and control values
by the user can be simplified with the interface adapter
(SMX3200) and Windows GUI software obtainable
from Summit Microelectronics.
SIMPLIFIED APPLICATIONS DRAWING
+5.0V
+5.0V
+3.3V
+3.3V
5.0V
3.3V
+2.7V
+2.5V
MR#
SCL
SDA
+2.7V
2.7V
+2.5V
2.5V
LINK#
IRQ#
_C
G
VG
RST #
A
P
FS#
VRLINK
LINK#
FS#
VO A
VIA
VO C
VIC
VGAT E C
VO B
VGAT E B
VIB
AP
_C
D
VD
VIA
VGAT E A
VO A
VO D
VID
Early GND
SMT4214 - Master
VGAT E D
SCL
MR#
SDA
PW R_ON#
SEAT ED#
VRLINK
VGAT E A
1.8V
SMT4214
Slaves
PWR_ON#
RST#
RST# Slave
IRQ_CLR#
IRQ_CLR#
IRQ#
Short Pin GND
Note 1
RST# M aster
RST# Master
---
t1 ---
RST# Slave
--- t2 ---
+1.8V
+1.8V
Power supply and system start-up initialization using multiple SMT4214s. Two power supply
channels are set to ‘softstart’ and three are set to track.
The above drawing illustrates the use of the SMT4214 in a multi-device application. It should be noted this is just an example and the specific component
values are purposely not shown. Note 1 - Several pins have internal resistors so external resistors are optional (see the Internal Functional Block
Diagram). If external resistors are used they should be tied to VDD_CAP on the Master.
© SUMMIT Microelectronics, Inc. 2004 • 1717 Fox Drive • San Jose CA 95131 • Phone 408 436-9890 • FAX 408 436-9897
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2061 2.2 09/15/05
1
SMT4214
Preliminary Information
GENERAL DESCRIPTION
The SMT4214 is a fully integrated power supply
manager designed for use on a distributed power or
multi-supply rail circuit card. The supplies can be
resident on the circuit card in the form of LDO’s or DCto-DC converters or the supplied voltages can be
present on the backplane of the system. In either
configuration, the SMT4214 will monitor both the raw
voltages at their source and also on the circuit side of
the power MOSFETs it is controlling.
A key function of the SMT4214 is the MOSFET
control. The device can be programmed to turn on the
MOSFET’s with a controlled MOSFET gate slew rate
in a soft start mode.
Alternatively it can be
programmed so that the MOSFETs are turned on so
that the voltages being applied to the circuitry are
‘tracked.’
Each supply on the card is assigned its own
manager on the SMT4214. If there are more than four
supplies, the SMT4214 can be linked with other
SMT4214’s through the use of the PWR_ON#, LINK#,
VRLINK and FS# pins.
The individual managers are programmed to
monitor their respective voltage supplies. The undervoltage threshold is programmable in 20mV
increments to monitor voltages within the range of
0.9V to 6.0V.
Under-voltage conditions can be
programmed to assert IRQ#, RST# or FS#.
DETAILED DEVICE OPERATION
SUPPLY MANAGERS
The electrical placement of the SMT4214, and
the associated MOSFET’s, on a printed circuit card
effectively divides the board into two electrical
domains; the bus-side and the card-side. The bus-side
constitutes the power supply sources either from the
backplane or on-board LDOs or DC-to-DC converters.
The card-side is comprised of the components that are
powered by the voltage sources on the output side of
the MOSFET’s.
The SMT4214 has four identical supply managers
each comprised of a programmable bus-side voltage
threshold comparator and a secondary comparator for
monitoring card-side voltages and programmable logic
to determine device reactions to changes in the
detected thresholds.
Figure 1 illustrates the functional segments of the
individual managers. The curved resistive element is
a symbolic representation of a non-volatile DAC.
When using the SMX3200 (dongle) and GUI software
the selected threshold level is programmed into the
Summit Microelectronics, Inc
SMT4214, effectively adjusting the output of the DAC
to the requested threshold detection level. Two
different voltage potentials for each supply are
measured, the pre-MOSFET threshold VI (bus-side
voltage) and the post-MOSFET threshold VO (cardside voltage). The VI threshold is set by a non-volatile
DAC. The VO threshold is set to 200mV below the VI
threshold or VI-200mV.
VI
VO
V REF
Offset
+
-
UV
+
Figure 1. Supply Manager
An under-voltage condition is defined as either VI
or VO dropping below its programmed threshold. A
programmable under-voltage filter requires that, after
the soft start and tracking are complete, an undervoltage condition must remain for a filter interval,
tFILTER, before any action is taken.
SOFT START
If a channel is set to soft start, its VGATE output
will ramp at a constant slew rate of 500V/s until it
reaches its maximum value. This type of operation
would commonly be used where a bus voltage ( e.g.,
5V) is first switched to a DC-to-DC converter or group
of LDOs; and then their outputs would be switched in a
tracking mode to the card-side logic.
All unused channels must be programmed to softstart mode. The thresholds for unused channels
should be set to minimum, and the VO and VI inputs
should be tied to VDD_CAP.
TRACKING
The tracking operation normally requires that at
least two channels are programmed to track.
However, a single channel can be set to track and is
compared against an internally set tracking model.
During tracking, the card-side voltages are monitored
to minimize the differential voltage between any of
these voltages until they reach their respective
thresholds.
In the tracking mode, the ramp rates are
inherently adaptive with a maximum of 500V/s. That
is, if there is any difference between the VO inputs in
the linear region, the VGATE outputs are adjusted to
minimize the differential.
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SMT4214
Preliminary Information
enabled and if power-on is not completed (all VGATE
outputs above their minimum programmed output
voltage) within a power-on limit interval (tPWRON), the
soft start and tracking operations will cease and FS#
will be asserted, shutting down all VGATE outputs.
After this shutdown, the device will not perform a
power-on operation until the PWR_ON# pin is toggled.
POWER-OFF
Once the SMT4214 has completed the power-on
operation, the power-off operation can be initiated by
bringing the PWR_ON# pin high. This pin can be
toggled high either externally or internally with an IIC
power-off command.
Once the power-off operation is initiated there is
a delay of tTRKDN = VDD/(500V/s). At this point the
SMT4214 will begin the discharging of the VGATE
output of the highest tracked channel. Once the VO
inputs of all tracked channels are within 100mV of
ground, all VGATE outputs will be clamped to ground.
RESET OPERATION (See Figure 2)
During power-on the RST# output will be low until
all selected managers detect their respective VO’s are
at or above the programmed threshold and the
tracking function is complete. RST# will remain active
for the reset timeout period (tPRTO) after the last VO
reaches its programmed threshold and the tracking
function is complete. RST# will also be held low from
the beginning of a power-off operation until the end of
a power-on operation.
POWER-ON
The power-on operation is initiated by taking the
PWR_ON# pin low. This pin can either be hardwired
low for an automatic power-on or it can be pulled low
after the device receives power. This pin can also be
pulled low using an I2C power-on command.
Two conditions must be met before the part
begins the power-on operation. FS# must be high; if
FS# is low, the SMT4214 will not power on. The
SEATED# pin must also be low for the seated delay
interval, tSEATED, before the device will power on.
Once the power-on operation is initiated the
SMT4214 will wait until all of the VI’s for the
designated soft start channels have reached their
programmed thresholds and VGG_CAP is at the
programmed output voltage (PVGG = 10.5V or 14V). At
this point the VGATE outputs of the soft start channels
will ramp up and turn on their corresponding card-side
voltages. When the VGATE outputs of the soft start
channels have ramped above their programmed
output voltage levels (PVVG = 10.5V or 14V) and the
respective card-side voltages are above their
programmed and fixed offset thresholds, soft start is
complete.
Once the soft start is complete the SMT4214 will
wait until all of the VI’s of the tracking channels are
above their programmed thresholds and then begin
tracking. The tracking operation ends when the
VGATE outputs of the tracking channels ramp up to
their maximum voltage. If the tracking time limit is
PVIT
VO
tPRTO
tPRTO
tDUVRS
RST#
tDMRRS
tPRTO
MR#
Figure 2. Timing relation between VO, RST# and MR#
P VIT
VI or VO
t DUVIR
t PRTO
IRQ#
t DCLIR
IRQ_CLR#
RST#
Figure 3. Timing relation between VI/VO, IRQ#, IRQ_CLR# and RST#
Summit Microelectronics, Inc
2061 2.2 09/15/05
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SMT4214
Preliminary Information
If enabled in the configuration register, RST# will
be driven low by any under-voltage condition. RST#
will remain asserted for a reset timeout period, tPRTO,
after the under-voltage condition has cleared.
RST# can be forced low by driving the manual
reset input (MR#) low. RST# will remain low so long
as the MR# input is active and stay low for tPRTO after
MR# returns high. The manual reset input is used to
drive the RST# output low and to enable write
operations to the configuration registers. It has no
affect on any other outputs or device operations.
IRQ OPERATION (See Figure 3)
The IRQ# output is disabled throughout the
power-on and power-off operations; from when power
is first applied until the VI inputs and VO inputs are
above their programmed thresholds and from the
beginning of a power-off until the end of a power-on
operation. If enabled in the configuration register,
IRQ# will be driven low by any under-voltage
condition. Once asserted, the IRQ output is latched
until cleared by removing the under-voltage condition
and asserting IRQ_CLR#. Refer to Figure 3 for an
illustration of the relationship of these conditions and
signals.
FORCE SHUTDOWN (See Figure 4)
The force shutdown function can be initiated
either externally or internally. The FS# pin is always
configured as an I/O and will always be enabled. If the
FS# pin is taken low the VGATE outputs will
immediately be clamped to ground.
The force shutdown function can be configured
as an internally initiated function when an undervoltage condition is detected. The force shutdown can
be initiated internally when an under-voltage condition
is sampled at the end of tracking or on an undervoltage condition after tracking is complete. In either
case, the FS# pin will be driven low and latched until
either the power is cycled or the PWR_ON# pin is
toggled. Refer to Figure 4,for an illustration of the
basic relation between VI, VO, FS# and VGATE.
MULTI-DEVICE OPERATION
Multiple SMT4214’s can be used on the same
board if more than four supplies need to be monitored
and controlled. One SMT4214 must be configured as
the master and the others must be configured as
slaves. The device configured as the master must
have a supply voltage that is greater than or equal to
the supply voltages of its slave devices.
The
SMT4214 provides four signals for easy interfacing;
PWR_ON#, FS#, VRLINK and LINK#.
PWR_ON# is an I/O.
This pin should be
connected together on each of the SMT4214s to
coordinate the power-on and power-off operation.
PWR_ON# can be toggled by an external host or by
the master SMT4214 in response to a command
received on the I2C bus.
FS# is an I/O, therefore, all FS# pins in a multidevice application must be tied together. One or more
of the SMT4214’s could be configured to generate a
force shutdown if an under-voltage condition is
detected.
When a device is configured as a master its
VRLINK pin will be configured as an output; all other
devices in the system are slaves with VRLINK pins
configured as inputs. As an output, the VRLINK
provides an analog signal that is the ramp reference
used to track the card-side voltages. The slave
devices will use this input as their own ramp reference.
In this manner, tracking is coordinated between all of
the devices.
The LINK# pin is an I/O that is used only during a
power-on or power-off operation and all the devices
will have their LINK# pins connected together. It is
through this pin that the tracking function is
coordinated. As an example: device 1 is the master
and is supplying the ramp reference to devices 2 and
3. If Channel A of device 3 falls behind the ramp
reference, device 3 will assert its LINK# output thus
halting the ramp on the card-side voltages of devices
1, 2 and 3 until channel A of device 3 can catch-up.
The master and slave devices must have at least one
of their four channels configured to track.
P VIT
VI or VO
FS# IN
FS# OUT
t DUVFS
VGATEx
tDFSVG
VGATEx
Externally triggered FS# action
tDUVVG
Internally triggered FS# action
Figure 4. Timing relation between VI/VO, FS# out and VGATE and the relation between FS# in and VGATE
Summit Microelectronics, Inc
2061 2.2 09/15/05
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SMT4214
Preliminary Information
FAULT STATUS REGISTERS
The SMT4214 has one volatile fault status register.
When an IRQ# is generated the cause of the interrupt
is recorded in the fault register. The fault source is
indicated as a ‘1’ in the assigned bit location (Figure
5). The fault status register is overwritten each time an
IRQ# is generated. The fault status register is always
available for reading except for when a volatile write is
in progress. The conditions for overwriting (clearing)
the fault condition is dependent upon the device
configuration with regard to the programmable ‘active
writing state’ of the MR# input. Clearing the fault status
registers is not necessary as the last fault condition
overwrites any information previously stored. If
clearing the registers is desired, it is accomplished by
forcing a write to those registers while no fault
conditions exist.
Fault recording is disabled when the PWR_ON# input
is high.
7
6
5
4
3
2
1
0
PW R_ON# State
RST # Pin State
IRQ# Pin State
VGAT E Pin State
VO D State
VO C State
VO B State
VO A State
Fault Status Register Address 06
SERIAL INTERFACE
The SMT4214 uses the industry standard I2C, 2-wire
serial data interface. This interface provides access to
the configuration registers, the volatile fault registers
and I2C Power-On/Off command. The interface has
three address inputs (A0, A1, A2) allowing up to eight
devices on the same bus. This allows multiple devices
on the same board or multiple boards in a system to
be controlled with two signals; SDA and SCL.
The configuration and volatile fault registers share the
same fixed device type identifier, 1001[bin].
The configuration and fault registers may be read
regardless of the state of MR#. MR# input has to be
low and the PWR_ON# pin high in order to write to the
configuration registers.
Device configuration utilizing the Windows based
SMT4214 graphical user interface (GUI) is highly
recommended. The software is available from the
Summit website (www.summitmicro.com). Using the
GUI in conjunction with this datasheet and Application
Note 28, simplifies the process of device prototyping
and the interaction of the various functional blocks. A
programming Dongle (SMX3200) is available from
Summit to communicate with the SMT4214. The
Dongle connects directly to the parallel port of a PC
and programs the device through a cable using the I2C
bus protocol.
Figure 5. Fault Status register bit allocation
Summit Microelectronics, Inc
2061 2.2 09/15/05
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23
Summit Microelectronics, Inc
2061 2.2 09/15/05
4
FS#
5
7
SEATED#
PW R_O N#
10
11
VO C
VO D
25
VIC
26
12
VO B
VID
24
VIB
VO A 13
VIA
Supply M anager D
Supply M anager C
Supply M anager B
Supply M anager A
GND
27
VDD
Control
100K Ω nom .
3 plcs.
2
Sequence
Enable Logic
Force
Shutdow n
Arbitration
M R#
16
100K Ω nom.
VDD_CAP
100K Ω nom.
5 plcs.
Bus Interface
Configuration
Registers and
Status Register
100K Ω nom .
Charge Pum p &
VGATE Control
IRQ & RST
Logic
LINK#
VRLINK
22
21
1
28
9
8
SDA
SCL
A1
A0
VGG_CAP
VGATE D
17
6
VG ATE C
VGATE B
19
18
VG ATE A
RST#
IRQ #
IRQ _CLR#
20
14
15
3
Preliminary Information
SMT4214
INTERNAL FUNCTIONAL BLOCK DIAGRAM
6
SMT4214
Preliminary Information
PIN DESCRIPTIONS
Pin
Number
Pin
Type
Pin Name
1
I/O
SDA
2
I
MR#
3
I
IRQ_CLR#
4
I/O
FS#
5
I/O
PWR_ON#
6
PWR
VGG_CAP
7
I
SEATED#
8
I
A0
9
I
A1
10
I
VOD
11
I
VOC
12
I
VOB
13
I
VOA
14
O
RST#
Summit Microelectronics, Inc
Pin Description
SDA is the bi-directional serial data pin. It is configured as an open drain output.
SDA is internally connected to VDD_CAP through a 100kΩ pull-up resistor. In
multiple device systems, an external pull-up should be connected to the highest
supply
The Manual Reset input is an active low input, internally connected to VDD_CAP
through a 100kΩ pull-up resistor. Taking MR# low will force the RST# output
low. MR# must be forced low when writing to the configuration registers.
Interrupt Clear is an active low input. Forcing IRQ_CLR# low will clear the IRQ#
output provided that it is not being driven by an under-voltage condition.
IRQ_CLR# is internally connected to VDD_CAP through a 100kΩ pull-up
resistor.
Force Shutdown is an active low open-drain I/O internally connected to
VDD_CAP through a 100kΩ pull-up resistor. FS# can be asserted either by an
outside signal or by a programmable under-voltage condition. If FS# is brought
low, the SMT4214 will immediately take the VGATE outputs to 0V. If multiple
SMT4214’s are used on a single board, the FS# outputs can be tied together. In
this configuration it is possible for a fault condition on one SMT4214 to shutdown
all of the SMT4214’s on a system.
The Power-On input must be low for the SMT4214 to begin turning on the
VGATE outputs. PWR_ON# is internally connected to VDD_CAP through a
100kΩ pull-up resistor, therefore its normal state is not active. PWR_ON# must
be held in its inactive state while writing to the configuration registers. Once the
power-on operation has completed, de-asserting the PWR_ON# input will force
the ‘tracked’ channels to power down and then clamp all VGATE outputs to
ground.
VGG_CAP is a charge storage connection for the charge pump. This capacitor
provides current to the VGATE outputs under varying load conditions. VGG_CAP
should nominally be 1µF.
The SEATED# is an active low input, internally connected to VDD_CAP through
a 100kΩ pull-up resistor. The SEATED# input is effectively an enable input that
must be low for tSEATED before the power-on operation can proceed. It is
generally tied to the ‘short pin’ in a staggered pin connector. When the card is
removed, SEATED# will go high and will initiate a power-off operation.
The address pins are biased either to VDD_CAP or GND and provide a
mechanism for assigning a unique bus address to the SMT4214. AO and A1 are
internally connected to VDD_CAP through a 100kΩ pull-up resistor
The Voltage Output monitor inputs are used to monitor the ‘card-side’ voltages
for the individual managers. See Figure 8 for additional external component
recommendations.
Reset is an active low open-drain output. It will be driven low whenever the MR#
input is low. RST# can be programmed so that it is asserted on an under-voltage
condition.
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SMT4214
Preliminary Information
PIN DESCRIPTIONS CONT’D
Pin
Number
Pin
Type
Pin Name
15
O
IRQ#
16
PWR
VDD_CAP
17
18
19
O
O
O
VGATED
VGATEC
VGATEB
20
O
VGATEA
21
I/O
VRLINK
22
I/O
LINK#
23
24
25
I
I
I
VIA
VIB
VIC
26
I
VID
27
PWR
GND
28
I
SCL
Pin Description
Interrupt is an active low open-drain output. It can be programmed so that it is
driven low on an under-voltage condition. It is cleared by removing any undervoltage conditions and asserting IRQ_CLR#.
VDD_CAP is a charge storage connection to the SMT4214’s internal power
supply. For most applications this is tied to a 10µF capacitor. A smaller 0.1µF
can be added in parallel for additional noise decoupling
The VGATE outputs are used to control the “turn-on” of the card-side voltages by
providing a high side voltage to a power MOSFET. The VGATE output voltages
are programmable as either 10.5V or 14.5V depending on the type of MOSFET
gate drive needed to fully enhance the device. See Figure 8 for additional
external component recommendations.
Voltage Ramp Link is an I/O and is used in a multi-SMT4214 application. If the
SMT4214 is designated as the master its VRLINK will become an output
providing the ramp reference of the card-side voltages for the slave SMT4214’s.
If the SMT4214 is designated as a slave its VRLINK will become the input for the
VRLINK of the master.
Link is an active low open-drain I/O internally connected to VDD_CAP through a
100kΩ pull-up resistor. In a multi-SMT4214 application the LINK# pin of all the
devices can be tied together to synchronize tracking. The LINK# I/O is active only
during a power-on or power-off operation. If one of the devices is falling behind in
tracking of the card-side voltages, it will assert its LINK# output and temporarily
halt the ramping of the VGATE voltages of the other devices.
The Voltage Inputs provide two functions. Internally they are diode-OR’ed;
therefore, the input with the highest voltage will act as the device’s VDD supply.
They are also the bus-side (unswitched) voltage monitoring inputs to the
individual supply managers. See Figure 8 for additional external component
recommendations.
GND is the ground for both the analog and digital portions of the internal circuitry.
SCL is the serial clock input, used for clocking data into or out of the SMT4214.
SCL is internally connected to VDD through a 100kΩ pull-up resistor. In multiple
device systems, an external pull-up should be connected to the highest supply.
PACKAGE PIN CONFIGURATION
28 Lead SSOP
SDA
SCL
GND
PIN 1
MR#
IRQ_CLR#
VID
FS#
VIC
VIB
PW R_ON#
VGG_CAP
SEAT ED#
A0
SM T4214
A1
VGAT E A
VO D
VGATE B
VO C
VGAT E C
VO B
VGAT E D
VO A
VDD_CAP
RST#
Summit Microelectronics, Inc
VIA
LINK#
VRLINK
15
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IRQ#
8
SMT4214
Preliminary Information
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Temperature Under Bias .................... -55°C to +125°C
Storage Temperature.......................... -65°C to +150°C
Terminal Voltage with Respect to GND:
VI & VO Inputs ……………….………..…..-0.3V to 7.0V
VGATE Outputs………………………………..……...16V
All Others .........……………………………..-0.3V to 7.0V
Output Short Circuit Current .....………………….100mA
Lead Solder Temperature (10 secs) .....………….300°C
Junction Temperature.........................….......…...150°C
ESD Rating per JEDEC…………………………..2000V
Latch-Up testing per JEDEC……………......+/- 100mA
Temperature Range (Industrial)...........–40°C to +85°C
(Commercial) ..............0°C to +70°C
Note - The device is not guaranteed to function outside its operating
rating. Stresses listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of the specification is
not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability. Devices are
ESD sensitive. Handling precautions are recommended.
RELIABILITY CHARACTERISTICS
Data Retention…………………………..…..100 Years
Endurance…………………….……….100,000 Cycles
Supply Voltage………………….………2.7V to 6.0V 1/
Package Thermal Resistance (θ JA)
28 Lead SSOP…………………………………80oC/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020
Notes: 1/ For reliable operation the VDD_CAP node voltage must
be equal to or greater than 2.7V (voltage level measured
on pin 16).
DC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Notes
Min.
Typ.
Max
VI
Supply Voltage VIA, VIB, VIC or
VID
IDD (ON)
Power Supply Current
PVIT
PVOT
Programmable VI Threshold
VO Threshold
PVVG
Programmable VGATE Output
VVG OFF
IVG
SRVG
VGATE Output
VGATE Drive Current
VGATE Slew Rate
VTRKR
Tracking Differential Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
VOL
RPull-Up
Output Low Voltage
Input Pullup Resistors
Device supply voltage defined by the
highest of the four VI inputs. Note 1/
Active Current VGATE Outputs
enabled
8-bit resolution 20mV/bit
VIX-VOX
Option 1 (MOSFETs on)
Option 2 (MOSFETs on)
VGATE sinking 2mA
MOSFET switches enabled
Allowable differential between VO
pins programmed for tracking
VI = 2.7V
VI = 5.0V
VI = 2.7V
VI = 5.0V
Open Drain Outputs, ISINK = 2mA
See Pin Descriptions
2.7
0.9
180
13
10
0
200
14
10.5
20
500
100
0.9xVI
0.7xVI
-0.1
-0.1
0
50
6.0
V
2
mA
6.0
220
V
mV
V
V
V
µA
V/s
0.4
80
250
mV
VI
VI
V
V
V
V
V
kΩ
0.1xVI
0.3xVI
100
Unit
0.4
165
Notes: 1/ - At least one of the VI inputs needs to be at or above 2.7V for proper device operation.
Summit Microelectronics, Inc
2061 2.2 09/15/05
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SMT4214
Preliminary Information
AC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) See
Figure 2, 3, 4 and 5 Timing diagrams.
Symbol
Description
Conditions
Min
Typ
Max Unit
tPRTO = 25ms
Programmable Reset Time-Out
tPRTO = 50ms
-25
tPRTO
tPRTO
+25
%
Period
tPRTO = 100ms
tPRTO = 200ms
tUVFILT = OFF
Programmable UV Filter Time
tUVFILT = 0.2ms
-25
tUVFILT
tUVFILT
+25
%
Interval
tUVFILT = 1.6ms
tUVFILT = 12.8ms
tSEATED
Seated Delay Interval
tSEATED = 25ms
-25
tSEATED
+25
%
tPWRON
Power-On Limit Interval
tPWRON = 200ms
-25
tPWRON
+25
%
tDFIRQ
Delay from fault detection to IRQ#
1
µs
tDFRST
Delay from fault detection to RST#
1
µs
Delay from assertion of MR# to
tDMRRST
100
ns
RST# Active
Delay from VIX valid to VGATEX
tDVIVG
VGG_CAP fully charged
10
µs
activated
tDUVFS
Delay UV to FS#
1
µs
tDUVVG
Delay UV to VGATE low
1
µs
Delay from assertion of FS# to
VGATE Capacitance =
tDFSVG
100
µs
VGATE clamped to ground.
10nF
Delay from PWR_ON# deasserted to
VDD/(500V/s)
tTRKDN
s
VGATEX deactivated.
TIMING DIAGRAMS
FS#
PW R_ON#
t TRKDN
SEATED#
t DFSVG
Soft Start
VGATEs
Tracking
VGATEs
t SEATED
t PW RON
Figure 5 - Timing relationship of de-asserting the enabling inputs on the VGATE outputs.
Summit Microelectronics, Inc
2061 2.2 09/15/05
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SMT4214
Preliminary Information
I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS - 100kHz
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) See
Figure 6 Timing diagram.
Symbol
Description
Conditions
Min
Typ
Max Units
fSCL
SCL Clock Frequency
0
tLOW
Clock Low Period
4.7
µs
tHIGH
Clock High Period
4.0
µs
tBUF
Bus Free Time
4.7
µs
tSU:STA
Start Condition Setup Time
4.7
µs
tHD:STA
Start Condition Hold Time
4.0
µs
tSU:STO
Stop Condition Setup Time
4.7
tAA
Clock Edge to Data Valid
SCL low to valid SDA (cycle n)
0.2
tDH
Data Output Hold Time
SCL low (cycle n+1) to SDA
change
0.2
tR
SCL and SDA Rise Time
Note 1/
1000
ns
tF
SCL and SDA Fall Time
Note 1/
300
ns
tSU:DAT
Data In Setup Time
250
ns
tHD:DAT
Data In Hold Time
0
ns
TI
Noise Filter SCL and SDA
tWR
Write Cycle Time
Before New Transmission
Note 1/
100
KHz
µs
3.5
µs
µs
Noise suppression
100
VGG_CAP Capacitor =1uF,
VGG_CAP=10.5V
ns
100
ms
Note: 1/ - Guaranteed by Design.
TIMING DIAGRAMS
tR
tF
tSU:SDA
t HD:SDA
t W R (For W rite O peration Only)
tHIGH
t LOW
SCL
SDA
tSU:DAT
tSU:STO
tBUF
(IN)
tAA
SDA
tHD:DAT
t DH
(OUT)
Figure 6 . Basic I2C Serial Interface Timing
Summit Microelectronics, Inc
2061 2.2 09/15/05
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SMT4214
Preliminary Information
PROGRAMMING INFORMATION
sending the configuration register address pointer; the
SMT4214 responds with an acknowledge; the host
then clocks in the data. Only one configuration register
can be written per data transfer. After the last byte is
clocked in, a stop condition must be issued for the
nonvolatile write operation to proceed. The SMT4214
requires an I2C read immediately after a successful
write to prevent the generation of a high voltage pulse
on the VGG_CAP pin. A start command will achieve
the required result.
SERIAL INTERFACE
Access to the configuration registers and memory
array is carried out over an industry standard 2-wire
serial interface (I2C). SDA is a bi-directional data line
and SCL is the clock input. Data is clocked in on the
rising edge of SCL and clocked out by the falling edge
of SCL. All data transfers begin with the MSB. During
data transfers SDA must remain stable while SCL is
high. Data are transferred in 8-bit packets with an
intervening clock period in which an acknowledge is
provided by the device receiving data.
READ
The address pointer for the registers can only be
changed by a write command. If a read command is
issued without address conditioning, the data that is
clocked out will be from a location pointed to by the
last written (or read) address incremented by 1.
In order to read data from a specific location a false
write command is issued. The sequence is: issue a
start and a device address with a write command; wait
for an acknowledge; send the array or register
address; wait for an acknowledge; issue a new start
and device address with a read command; wait for an
acknowledge then proceed to clock out data. For
register reads, only a single location can be read with
each command sequence. All read operations are
concluded by issuing a stop condition. Refer to Figure
8 for an illustration of the read sequence.
The SCL high period (tHIGH) is used for generating start
and stop conditions that precede and end most
transactions on the serial bus. A high-to-low transition
of SDA during tHIGH is a start condition and a low-tohigh transition of SDA during tHIGH is a stop condition.
The interface protocol allows operation of multiple
devices and types of devices on a single bus through
the use of unique device addressing. The address
byte is comprised of a 4-bit device type identifier, a 3bit bus address and a single bit indicating that the
operation is a read or a write. The configuration and
fault status registers are accessible with a separate
device type identifier of 1001[bin]. The bus address is
defined by the state (‘0’ or ‘1’) of the A0, A1 pins and
A2 virtual address bit. The serial data stream must
match the state of these pins.
WRITE
MR#, PWR_ON# AND THE SERIAL INTERFACE
When reading the status registers, the state of the
MR# input is ignored. When writing the configuration
registers, MR# must be low and the PWR_ON# pin
high.
Writing to the configuration registers is illustrated in
Figures 7. A start condition followed by the address
byte is provided by the host; the SMT4214 responds
with an acknowledge; the host then responds by
S
T
A
R
T
M aster
Bus Address =
Address Pins
1
SDA
0
0
1
A
2
A
1
A
0
S
T
O
P
Configuration
Register
Address
X
W
X
X
X
C
3
C
2
C
1
C
0
A
C
K
SM T4004
D
6
D
7
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 7. Write configuration register sequence.
M aster
SDA
S
T
A
R
T
Bus Address =
Address Pins
1
0
0
1
A
2
A
1
A
0
X
W
A
C
K
SM T4004
S
T
A
R
T
Configuration
Register
Address
X
X
X
C
3
C
2
C
1
C
0
N
A
C
K
Bus Address =
Address Pins
1
A
C
K
0
0
1
A
2
A
1
A
0
D
7
R
D
6
D
5
D
4
D
3
D
2
D
1
S
T
O
P
D
0
A
C
K
Figure 8. Read Configuration register or status register sequence.
Summit Microelectronics, Inc
2061 2.2 09/15/05
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SMT4214
Preliminary Information
DEVELOPMENT HARDWARE & SOFTWARE
The Windows GUI software will generate the data
and send it in I2C serial bus format so that it can be
directly downloaded to the SMT4214 via the
programming Dongle and cable. An example of the
connection interface is shown in Figure 9A and 9B.
When design prototyping is complete, the
software can generate a HEX data file that should then
be transmitted to Summit for approval. Summit will
then assign a unique customer ID to the HEX code
and program production devices before the final
electrical test operations. This will ensure proper
device operation in the end application.
The end user can obtain the Summit SMX3200
programming
system
for
device
prototype
development. The SMX3200 system consists of a
programming Dongle, cable and Windows GUI
software. It can be ordered on the website or from a
local representative. The latest revisions of all
software and an application brief describing the
SMX3200 is available from the website (see below).
The SMX3200 programming Dongle/cable
interfaces directly between a PC’s parallel port and the
target application. The device is then configured onscreen via an intuitive graphical user interface
employing drop-down menus.
Top view of straight 0.1" x 0.1 closed-side
connector. SMX3200 interface cable connector
D1
VDD_CAP
R1 4.7k Ω
PW R_ON#
R2
SMT4214
M R#
SDA
SCL
Pin 10, Reserved
Pin 8, Reserved
Pin 6, MR#
Pin 4, SDA
Pin 2, SCL
D2
Pin 9, 5V
Pin 7, 10V
Pin 5, Reserved
Pin 3, GND
Pin 1, GND
4.7k Ω
10
8
6
4
2
9
7
5
3
1
C1
0.1 µ F
C2
0.1 µ F
GND
Com m on
Ground
Figure 9A – SMX3200 Programmer and I2C serial bus connections to program the SMT4214. For the
SMT4214, the PWR_ON# pin must be high in order to program the device. It can be done optionally through
the SMX3200 programmer and R1/R2 or through an external control signal or switch. The SMX3200 should
be disconnected after programming the part. If the PWR_ON# is hardwired to ground, this method will not
work. Normally SDA and SCL signals require on board pull-up resistors, however, both the SMT4214 and
the SMX3200 have internal pull-up resistors. D1 and D2 (1N4148) are needed between the Dongle Supplies
and the VDD_CAP and PWR_ON# pins so that there will be no contention between the two supplies. C1 and
C2 are for noise bypassing.
The latest revisions of all software and an application brief describing the SMX3200 is available from the website at:
http://www.summitmicro.com/tech_support/program_kit/SMX3200.htm
Summit Microelectronics, Inc
2061 2.2 09/15/05
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SMT4214
Preliminary Information
DEVELOPMENT HARDWARE & SOFTWARE (Cont.)
D1
5.6V
Zener
VDD_CAP
R1
D2
PW R_ON#
R2
4.7k Ω
4.7k Ω
D3
S1
SM T4214
GND
10
8
6
4
2
M R#
SDA
SCL
9
7
5
3
1
C1
0.1 µ F
C2
0.1 µ F
Com m on
Ground
Figure 9B – An alternative connection between the SMX3200 Programmer and SMT4214 I2C serial bus
connections. Although this alternative requires additional components, it will work regardless of the
position of the external PWR_ON# control signal or switch (S1). The zener diode (D3) provides further
protection by clamping the output voltage at 5.6V.
APPLICATIONS INFORMATION
An example master/slave application circuit is
shown in Figure 10A and 10B. Additional optional
noise bypassing components are shown for the VIX
and VOX pins. These components consist of ferrite
bead inductors and capacitors.
They may be
necessary in very noisy systems where tight
undervoltage tolerances are needed.
All unused channels must be programmed to softstart mode. The thresholds for unused channels
should be set to minimum, and the VO and VI inputs
should be tied to the highest voltage VI input.
The VGATE output pins require series resistors to
drive the gates of the power MOSFETs.
Gate
capacitors (C23 thru C30) are also recommended to
prevent initial MOSFET turn-on during the SMT4214
power on sequence. To minimize transient power
Summit Microelectronics, Inc
surges in hot-swappable line card designs, place a
0.01µF (10nF), 25V, ceramic capacitor on each
VGATE output pin to ground.
The VGATE output level is programmable to either
10.5V or 14V depending on the type of MOSFET. To
minimize the voltage drop across the MOSFET, it
needs to be fully enhanced to minimize RDS(ON).
However, some MOSFETs have maximum VGS
specifications of 15V while others are 20V. For
improved tracking performance with the SMT4214, it is
recommended to use the lower rated VGS devices
with the VGATE output levels set to 10.5V instead of
14V. The industry trend for power MOSFETs is
toward lower VGS specs while also maintaining low
RDS(ON) specifications.
2061 2.2 09/15/05
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SMT4214
Preliminary Information
APPLICATIONS INFORMATION (Cont.)
LAYOUT CONSIDERATIONS
When a power MOSFET is off, the trace from the
supply to the VIX input of the SMT4214 carries very
little current. As that MOSFET turns on the trace will
carry more current possibly causing a voltage drop
across the trace. If this voltage drop is severe, the VIX
input will droop below the UV trip point and the supply
will stay below the trip point even when the MOSFET
is fully enhanced. Therefore, the internal ramp model
of the SMT4214 will halt indefinitely. Subsequent
higher voltage channels will also halt with the internal
ramp model causing their corresponding VGATE
outputs to halt. This leaves the MOSFETs on but not
fully enhanced and therefore with higher rDS(ON) and
Summit Microelectronics, Inc
more power dissipation. In order to prevent this
situation it is recommended that the sense lines of the
power supply be connected close to the power
MOSFET as the power supply will then compensate
for any voltage drop along the trace. The trace should
also be designed to adequately handle the required
current with minimal voltage drop.
The Tracking Time Limit feature in the Windows GUI
should be enabled to prevent tracking from hanging-up
and allowing the MOSFETs to get hot. Lowering the
UV trip points will also solve the problem, but could
leave the output voltages lower than expected.
2061 2.2 09/15/05
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SMT4214
Preliminary Information
APPLICATIONS INFORMATION (Cont.)
Figure 10A – Example application using two SMT4214s connected in a Master/Slave configuration. The
Master is shown above, the Slave is shown in Figure 10B.
Summit Microelectronics, Inc
2061 2.2 09/15/05
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SMT4214
Preliminary Information
APPLICATIONS INFORMATION (cont.)
Figure 10B – Example application using two SMT4214s connected in a Master/Slave configuration. The Slave
is shown above, the Master is shown in Figure 10A
Summit Microelectronics, Inc
2061 2.2 09/15/05
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SMT4214
Preliminary Information
DEFAULT CONFIGURATION REGISTER SETTINGS – SMT4214G-115
Register
Hex Contents
Configured as:
R00
B4
Channel A UV Trip Point = 4.5V
R01
69
Channel B UV Trip Point = 3.0V
R02
41
Channel C UV Trip Point = 2.2V
R03
28
Channel D UV Trip Point = 1.7V
R04
F1
Channel A,B,C, and D set to track
Tracking time limit enabled
RST# timeout interval set to 25ms
Device set as Master
R05
21
VGATE output level = 10.5V
UV cause RST# after tracking enabled
UV cause IRQ# after tracking disabled
Filter time = 0ms
Virtual address A2 set to high
UV does not cause a FS# after tracking is complete (steady state)
UV does not cause a FS# at the end of tracking filter time interval
R06
00
Volatile register, all status bits are low
The default device ordering number is SMT4214G-115. It is programmed with the register contents as shown above
and tested over the commercial temperature range.
Application Note 28 contains a complete description of the Windows GUI and the default
settings of each of the 6 individual Configuration Registers.
Summit Microelectronics, Inc
2061 2.2 09/15/05
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SMT4214
Preliminary Information
PACKAGE
28 Lead SSOP Package
Summit Microelectronics, Inc
2061 2.2 09/15/05
19
SMT4214
Preliminary Information
PART MARKING
Summit Part Number
SUMMIT
SMT4214G
Status Tracking Code
(Blank, MS, ES, 01, 02,...)
(Summit Use)
xx
Annn L AYYWW
Pin 1
Date Code (YYWW)
Lot tracking code (Summit use)
100% Sn, RoHS compliant
Part Number suffix (Contains Customer specific programming
and ordering requirements. The default device ordering number
is not marked on the device)
Drawing not to scale
Product Tracking Code (Summit use)
ORDERING INFORMATION
Summit
Part
Number
SMT4214
G
C
nnn
L
Environmental Attribute
L = 100% Sn, RoHS compliant
Part Number Suffix (see page 18)
Package
Temp Range
Specific requirements are contained in the suffix
G=28 Lead SSOP C=Commercial
Blank=Industrial
NOTICE
NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization.
Revision 2.2 - This document supersedes all previous versions. . Data Sheet updates can be accessed by “right” or “left” mouse clicking on the
link: http://www.summitmicro.com/prod_select/summary/smt4214.htm
Device Errata sheets can be accessed by “right” or “left” mouse clicking on the link: http://www.summitmicro.com/errata/SMT4214
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design,
performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license
under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained
herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this
publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or
omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or
malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness.
Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that:
(a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc.
is adequately protected under the circumstances.
© Copyright 2004 SUMMIT MICROELECTRONICS, Inc.
PROGRAMMABLE POWER FOR A DIGITAL WORLD™
I2C is a trademark of Philips Corporation.
Summit Microelectronics, Inc
2061 2.2 09/15/05
20