ETC TSL1401R

TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
128 × 1 Sensor-Element Organization
400 Dots-Per-Inch (DPI) Sensor Pitch
High Linearity and Uniformity
Wide Dynamic Range . . . 4000:1 (72 dB)
Output Referenced to Ground
Low Image Lag . . . 0.5% Typ
Operation to 8 MHz
Single 3-V to 5-V Supply
Rail-to-Rail Output Swing (AO)
No External Load Resistor Required
Replacement for TSL1401
DIP PACKAGE
(TOP VIEW)
SI 1
8 NC
CLK 2
7 GND
AO 3
6 GND
VDD 4
5 NC
NC – No internal connection
Description
The TSL1401R linear sensor array consists of a 128 × 1 array of photodiodes, associated charge amplifier
circuitry, and an internal pixel data-hold function that provides simultaneous-integration start and stop times for
all pixels. The pixels measure 63.5 µm (H) by 55.5 µm (W) with 63.5-µm center-to-center spacing and 8-µm
spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI)
signal and a clock.
Functional Block Diagram
Pixel 1
Pixel
2
Integrator
Reset
Pixel
3
4
Pixel
128
VDD
Analog
Bus
3
Output
Buffer
_
AO
+
Sample/
Output
6, 7
GND
Switch Control Logic
Hold
CLK
SI
Q1
2
Q2
Q3
Q128
Gain
Trim
128-Bit Shift Register
1
The LUMENOLOGY Company
Copyright 2002, TAOS Inc.
Texas Advanced Optoelectronic Solutions Inc.
800 Jupiter Road, Suite 205 Plano, TX 75074 (972)
673-0759
www.taosinc.com
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TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
AO
3
Analog output.
CLK
2
Clock. The clock controls charge transfer, pixel output, and reset.
GND
6, 7
Ground (substrate). All voltages are referenced to the substrate.
NC
5, 8
No internal connection.
SI
1
Serial input. SI defines the start of the data-out sequence.
VDD
4
Supply voltage. Supply voltage for both analog and digital circuits.
Detailed Description
The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog
switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the
integration time.
The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle
is initiated by clocking in a logic 1 on SI. For proper operation, after meeting the minimum hold time condition,
SI must go low before the next rising edge of the clock. An internal signal, called Hold, is generated from the
rising edge of SI and transmitted to analog switches in the pixel circuit. This causes all 128 sampling capacitors
to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is
clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a
charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first
18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19th clock. On the
129th clock rising edge, the SI pulse is clocked out of the shift register and the analog output AO assumes a
high impedance state. Note that this 129th clock pulse is required to terminate the output of the 128th pixel, and
return the internal logic to a known state. A subsequent SI pulse may be presented as early as the 130th clock
pulse, thereby initiating another pixel output cycle.
AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail
output voltage swing. With VDD = 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V
for saturation light level. When the device is not in the output phase, AO is in a high-impedance state.
The voltage developed at analog output (AO) is given by:
Vout = Vdrk + (Re) (Ee)(tint)
where:
Vout
Vdrk
Re
Ee
tint
is
is
is
is
is
the analog output voltage for white condition
the analog output voltage for dark condition
the device responsivity for a given wavelength of light given in V/(µJ/cm2)
the incident irradiance in µW/cm2
integration time in seconds
A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device.
The TSL1401R is intended for use in a wide variety of applications, including: image scanning, mark and code
reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and optical
linear and rotary encoding.
Copyright 2002, TAOS Inc.
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TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
Absolute Maximum Ratings†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3V
Input clamp current, IIK (VI < 0) or (VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA to 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 mA to 25 mA
Voltage range applied to any output in the high impedance or power-off state, VO . . . –0.3 V to VDD + 0.3 V
Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 mA to 25 mA
Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 mA to 40 mA
Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 mA to 25 mA
Maximum light exposure at 638 nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mJ/cm2
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to 85°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions (see Figure 1 and Figure 2)
MIN
NOM
Supply voltage, VDD
3
5
5.5
V
Input voltage, VI
0
VDD
V
High-level input voltage, VIH
Low-level input voltage, VIL
2
VDD
V
Wavelength of light source, λ
Clock frequency, fclock
Sensor integration time, tint
Setup time, serial input, tsu(SI)
Hold time, serial input, th(SI) (see Note 1)
MAX
0
0.8
400
1000
nm
5
8000
kHz
0.018
100
ms
20
0
V
ns
0
Operating free-air temperature, TA
UNIT
ns
70
°C
NOTE 1: SI must go low before the rising edge of the next clock pulse.
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TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms,
RL = 330 Ω, Ee = 11 µW/cm2 (unless otherwise noted) (see Note 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.6
2
2.4
V
0.1
0.2
V
±4%
±7.5%
Vout
Analog output voltage (white, average over 128 pixels)
See Note 3
Vdrk
Analog output voltage (dark, average over 128 pixels)
Ee = 0
PRNU
Pixel response nonuniformity
See Note 4
Nonlinearity of analog output voltage
See Note 5
±0.4%
Output noise voltage
See Note 6
1
Re
Responsivity
See Note 7
25
35
4.8
Analog output saturation voltage
VDD = 5 V, RL = 330 Ω
4.5
Vsat
VDD = 3 V, RL = 330 Ω
2.5
2.8
SE
Saturation exposure
DSNU
Dark signal nonuniformity
All pixels, Ee = 0, See Note 9
IL
Image lag
See Note 10
IDD
Supply current
IIH
High-level input current
VI = VDD
IIL
Low-level input current
VI = 0
Ci
Input capacitance
0
VDD = 5 V, See Note 8
136
VDD = 3 V, See Note 8
78
0.02
UNIT
FS
mVrms
45
V/
(µJ/cm 2)
V
nJ/cm 2
0.05
V
0.5%
VDD = 5 V, Ee = 0
2.8
4.5
VDD = 3 V, Ee = 0
2.6
4.5
mA
1
µA
1
µA
5
pF
NOTES: 2. All measurements made with a 0.1 µF capacitor connected between VDD and ground.
3. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
4. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
5. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
6. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
7. Re(min) = [Vout(min) – Vdrk(max)] ÷ (Ee × tint)
8. SE(min) = [Vsat(min) – Vdrk(min)] × 〈Ee × tint) ÷ [Vout(max) – Vdrk(min)]
9. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination.
10. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
IL V out (IL) V drk
V out (white) V drk
100
Timing Requirements (see Figure 1 and Figure 2)
MIN
tsu(SI)
Setup time, serial input (see Note 11)
th(SI)
Hold time, serial input (see Note 11 and Note 12)
tw
tr, tf
NOM
MAX
UNIT
20
ns
0
ns
Pulse duration, clock high or low
50
ns
Input transition (rise and fall) time
0
500
ns
NOTES: 11. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns.
12. SI must go low before the rising edge of the next clock pulse.
Dynamic Characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figures 7 and 8)
PARAMETER
ts
TEST CONDITIONS
Analog output settling time to ±1%
Copyright 2002, TAOS Inc.
RL = 330 Ω,
CL = 10 pF
TYP
120
MAX
UNIT
ns
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MIN
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TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
TYPICAL CHARACTERISTICS
CLK
SI
Internal
Reset
Integration
18 Clock Cycles
tint
Not Integrating
Integrating
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ
129 Clock Cycles
AO
Hi-Z
Hi-Z
Figure 1. Timing Waveforms
tw
1
2
128
129
5V
2.5 V
CLK
0V
tsu(SI)
SI
5V
50%
0V
th(SI)
ts
AO
Pixel 1
Pixel 128
Figure 2. Operational Waveforms
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TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
TYPICAL CHARACTERISTICS
NORMALIZED IDLE SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
PHOTODIODE SPECTRAL RESPONSIVITY
1
2
IDD — Normalized Idle Supply Current
TA = 25°C
Relative Responsivity
0.8
0.6
0.4
0.2
0
300
1.5
1
0.5
0
400
500
600
700
800
900
1000 1100
0
10
20
Figure 3
50
60
70
Figure 4
DARK OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
WHITE OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
2
0.10
VDD = 5 V
tint = 0.5 ms to 15 ms
tint = 0.5 ms
tint = 1 ms
VDD = 5 V
0.09
1.5
Vout — Output Voltage
Vout — Output Voltage — V
40
TA – Free-Air Temperature – °C
λ – Wavelength – nm
1
0.08
tint = 15 ms
tint = 5 ms
tint = 2.5 ms
0.07
0.5
0
0.06
0
10
20
30
40
60
50
TA – Free-Air Temperature – °C
70
0
10
20
30
40
60
50
TA – Free-Air Temperature – °C
Figure 5
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Figure 6
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TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
TYPICAL CHARACTERISTICS
SETTLING TIME
vs.
LOAD
SETTLING TIME
vs.
LOAD
600
600
VDD = 3 V
Vout = 1 V
VDD = 5 V
Vout = 1 V
500
470 pF
Settling Time to 1% — ns
Settling Time to 1% — ns
500
400
220 pF
300
200
100 pF
100
470 pF
400
220 pF
300
200
100 pF
100
10 pF
10 pF
0
0
200
400
600
800
RL — Load Resistance – 1000
0
0
200
400
600
800
RL — Load Resistance – Figure 7
The LUMENOLOGY Company
1000
Figure 8
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TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
MECHANICAL INFORMATION
This dual-in-line package consists of an integrated circuit mounted on a lead frame and encapsulated in an electrically
nonconductive clear plastic compound.
0.440 (11,18)
0.420 (10,67)
Centerline of Pin 1 Nominally
Lies Between Pixels 5 and 6.
C
7 L 6
8
5
0.017 (0,43)
CL Pixels
0.260 (6,60)
0.240 (6,61)
C
L Package
1
0.30 (0,76) NOM
0.260 (6,60)
0.240 (6,10)
0.075 (1,91)
0.060 (1,52)
2
3
4
C
L Pin 1
0.310 (7,87)
0.290 (7,37)
0.016 (0,41)
0.014 (0,36)
Die Thickness
0.10 (2,54)
8°
10°
0.130 (3,30)
0.120 (3,05)
0.053 (1,35)
0.043 (1,09)
0.175 (9,78)
0.155 (7,75)
Seating Plane
8°
100°
90°
8°
0.012 (0,30)
0.008 (0,20)
0.060 (1,52)
0.040 (1,02)
0.025 (0,64)
0.015 (0,38)
0.150 (3,81)
0.125 (3,18)
NOTES: A. All linear dimensions are in inches and (millimeters).
B. Index of refraction of clear plastic is 1.55.
C. This drawing is subject to change without notice.
Figure 9. Packaging Configuration
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TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this
document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.
TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product
design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consquential or incidental damages.
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
LUMENOLOGY is a registered trademark, and TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are trademarks of
Texas Advanced Optoelectronic Solutions Incorporated.
The LUMENOLOGY Company
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TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
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