ams AG

TAOS Inc.
is now
ams AG
The technical content of this TAOS datasheet is still valid.
Contact information:
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8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
e-Mail: [email protected]
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TSL201CL
64 1 LINEAR SENSOR ARRAY
r
r
64 × 1 Sensor-Element Organization
200 Dots-Per-Inch (DPI) Sensor Pitch
High Linearity and Uniformity
Wide Dynamic Range . . . 2000:1 (66 dB)
Output Referenced to Ground
Low Image Lag . . . 0.5% Typ
Operation to 5 MHz
Single 5-V Supply
Replacement for TSL201, TSL201R, and
TSL201R−LF
RoHS Compliant
D
CL PACKAGE
(TOP VIEW)
SI 1
8 NC
CLK 2
7 GND
AO 3
6 GND
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D
D
D
D
D
D
D
D
D
TAOS146 − APRIL 2012
VDD 4
5 NC
NC − No internal connection
Description
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Package Drawing is Not to Scale
The TSL201CL linear sensor array consists of a 64 × 1 array of photodiodes and associated charge amplifier
circuitry. The pixels measure 120 μm (H) by 68 μm (W) with 125-μm center-to-center spacing and 57-μm
spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI)
signal and a clock.
The TSL201CL is intended for use in a wide variety of applications including mark detection and code reading,
optical character recognition (OCR) and contact imaging, edge detection and positioning as well as optical linear
and rotary encoding.
Functional Block Diagram
Pixel 1
S1
_
Pixel
3
Pixel
64
Analog
Bus
2
1
3
S2
Sample/
Output
ni
ch
Te
2
SI
Q1
3
AO
6, 7
GND
Q2
RL
(External
330 W
Load)
Gain
Trim
Switch Control Logic
CLK
4
VDD
Output
Amplifier
ca
+
Pixel
2
1 Integrator
Reset
2
Q3
Q64
64-Bit Shift Register
1
The LUMENOLOGY r Company
Copyright E 2012, TAOS Inc.
r
Texas Advanced Optoelectronic Solutions Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S (972)
r 673-0759
www.taosinc.com
1
TSL201CL
64 1 LINEAR SENSOR ARRAY
TAOS146 − APRIL 2012
Terminal Functions
TERMINAL
NO.
AO
3
Analog output.
CLK
2
Clock. The clock controls charge transfer, pixel output, and reset.
GND
6, 7
Ground (substrate). All voltages are referenced to the substrate.
SI
1
Serial input. SI defines the start of the data-out sequence.
VDD
4
Supply voltage. Supply voltage for both analog and digital circuits.
Detailed Description
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DESCRIPTION
NAME
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The sensor consists of 64 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During
the integration period, a sampling capacitor connects to the output of the integrator through an analog switch.
The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration
time. The integration time is the interval between two consecutive output periods.
The output and reset of the integrators is controlled by a 64-bit shift register and reset logic. An output cycle is
initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2) †. As the SI pulse
is clocked through the 64-bit shift register, the charge on the sampling capacitor of each pixel is sequentially
connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes
low, the pixel integrator is reset. On the 65th clock rising edge, the SI pulse is clocked out of the shift register
and the output assumes a high-impedance state. Note that this 65th clock pulse is required to terminate the
output of the 64th pixel and return the internal logic to a known state. A subsequent SI pulse can be presented
as early as the 66th clock pulse, thereby initiating another pixel output cycle.
The voltage developed at analog output (AO) is given by:
Vout = Vdrk + (Re) (Ee) (tint)
is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(μJ/cm2)
is the incident irradiance in μW/cm2
is integration time in seconds
ca
where:
Vout
Vdrk
Re
Ee
tint
ni
AO is driven by a source follower that requires an external pulldown resistor (330-Ω typical). The output is
nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device
is not in the output phase, AO is in a high impedance state.
For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.
Te
†
ch
A 0.1 μF bypass capacitor should be connected between VDD and ground as close as possible to the device.
Copyright E 2012, TAOS Inc.
The LUMENOLOGY r Company
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2
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TSL201CL
64 1 LINEAR SENSOR ARRAY
TAOS146 − APRIL 2012
Absolute Maximum Ratings†
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Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3V
Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA to 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 mA to 25 mA
Voltage range applied to any output in the high impedance or
power-off state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3V
Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 mA to 25 mA
Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 mA to 40 mA
Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 mA to 25 mA
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to 85°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
ESD tolerance, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡
Not recommended for solder reflow.
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†
Recommended Operating Conditions (see Figure 1 and Figure 2)
Supply voltage, VDD
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
Input voltage, VI
High-level input voltage, VIH
0
VDD
V
2
VDD
V
Low-level input voltage, VIL
Wavelength of light source, λ
0
0.8
V
400
1000
nm
5
5000
kHz
Sensor integration time, tint
Operating free-air temperature, TA
0.013
100
ms
0
70
°C
Load resistance, RL
300
4700
Ω
470
pF
Clock frequency, fclock
Te
ch
ni
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Load capacitance, CL
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TSL201CL
64 1 LINEAR SENSOR ARRAY
TAOS146 − APRIL 2012
Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms,
RL = 330 Ω, Ee = 16.5 μW/cm2 (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
1.6
2
2.4
V
50
120
mV
± 4%
± 7.5%
Analog output voltage (white, average over 64 pixels)
see Note 1
Vdrk
Analog output voltage (dark, average over 64 pixels)
Ee = 0
PRNU
Pixel response nonuniformity
See Notes 2 & 3
Nonlinearity of analog output voltage
See Note 3
± 0.4%
Output noise voltage
See Note 4
1
0
Re
Responsivity (See Note 5)
18
SE
Saturation exposure
Vsat
Analog output saturation voltage
DSNU
Dark signal nonuniformity
All pixels, Ee = 0
IL
Image lag
See Note 8
IDD
Supply current, output idle
IIH
High-level input current
IIL
Low-level input current
Ci(SI)
Input capacitance, SI
Ci(CLK)
Input capacitance, CLK
23
See Note 6
142
2.5
3.4
25
FS
mVrms
V/
(μJ/cm 2)
nJ/cm 2
V
120
mV
lv
See Note 7
UNIT
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PARAMETER
Vout
0.5%
3.4
5
mA
1
μA
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VI = VDD
VI = 0
1
μA
5
pF
5
pF
NOTES: 1. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
2. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
3. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
4. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
5. Re(min) = [Vout(min) − Vdrk(max)] ÷ (Ee × tint)
6. Minimum saturation exposure is calculated using the minimum Vsat, the maximum Vdrk, and the maximum Re.
7. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination.
8. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
IL +
V out (IL) * V drk
V out (white) * V drk
100
ca
Timing Requirements (see Figure 1 and Figure 2)
MIN
Setup time, serial input (see Note 9)
th(SI)
Hold time, serial input (see Note 9 and Note 10)
tw
Pulse duration, clock high or low
tr, tf
Input transition (rise and fall) time
0
NOM
MAX
UNIT
20
ns
0
ns
50
ns
500
ns
ch
ni
tsu(SI)
Te
NOTES: 9. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns.
10. SI must go low before the rising edge of the next clock pulse.
Dynamic Characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)
ts
PARAMETER
TEST CONDITIONS
Analog output settling time to ± 1%
Copyright E 2012, TAOS Inc.
RL = 330 Ω,
CL = 10 pF
TYP
185
MAX
UNIT
ns
The LUMENOLOGY r Company
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4
MIN
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TSL201CL
64 1 LINEAR SENSOR ARRAY
TAOS146 − APRIL 2012
TYPICAL CHARACTERISTICS
CLK
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
65 Clock Cycles
AO
Hi-Z
Hi-Z
2.5 V
tsu(SI)
SI
2.5 V
1
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Figure 1. Timing Waveforms
CLK
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SI
2
64
65
2.5 V
5V
2.5 V
0V
5V
2.5 V
0V
th(SI)
ts
AO
ts
Pixel 1
Pixel 64
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Figure 2. Operational Waveforms
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5
TSL201CL
64 1 LINEAR SENSOR ARRAY
TAOS146 − APRIL 2012
TYPICAL CHARACTERISTICS
ANALOG OUTPUT SETTLING TIME
vs
LOAD CAPACITANCE AND RESISTANCE
PHOTODIODE SPECTRAL RESPONSIVITY
1
600
500
0.6
0.2
400
100 pF
300
10 pF
200
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0.4
220 pF
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ts — Settling Time to 1% — ns
0.8
Relative Responsivity
470 pF
VDD = 5 V
Vout = 1 V
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TA = 25°C
100
0
300
400
500
600
700
800
900
1000 1100
λ − Wavelength − nm
0
0
200
400
600
800
1000
1200
RL − Load Resistance − Ω
Figure 4
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Figure 3
Copyright E 2012, TAOS Inc.
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TSL201CL
64 1 LINEAR SENSOR ARRAY
TAOS146 − APRIL 2012
APPLICATION INFORMATION
Power Supply Considerations
For optimum device performance, power-supply lines should be decoupled by a 0.01-μF to 0.1-μF capacitor
with short leads mounted close to the device package.
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Integration Time
The integration time of the linear array is the period during which light is sampled and charge accumulates on
each pixel’s integrating capacitor. The flexibility to adjust the integration period is a powerful and useful feature
of the TAOS TSL2xx linear array family. By changing the integration time, a desired output voltage can be
obtained on the output pin while avoiding saturation for a wide range of light levels.
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Each pixel of the linear array consists of a light-sensitive photodiode. The photodiode converts light intensity
to a voltage. The voltage is sampled on the Sampling Capacitor by closing switch S2 (position 1) (see the
functional block diagram on page 1). Logic controls the resetting of the Integrating Capacitor to zero by closing
switch S1 (position 2).
At SI input (Start Integration), pixel 1 is accessed. During this event, S2 moves from position 1 (sampling) to
position 3 (holding). This holds the sampled voltage for pixel 1. Switch S1 for pixel 1 is then moved to position
2. This resets (clears) the voltage previously integrated for that pixel so that pixel 1 is now ready to start a new
integration cycle. When the next clock period starts, the S1 switch is returned to position 1 to be ready to
start integrating again. S2 is returned to position 1 to start sampling the next light integration. Then the next pixel
starts the same procedure. The integration time is the time from a specific pixel read to the next time that pixel
is read again. If either the clock speed or the time between successive SI pulses is changed, the integration time
will vary. After the final (nth) pixel in the array is read on the output, the output goes into a high-impedance mode.
A new SI pulse can occur on the (n+1) clock causing a new cycle of integration/output to begin. Note that the
time between successive SI pulses must not exceed the maximum integration time of 100 msec.
The minimum integration time for any given array is determined by time required to clock out all the pixels in
the array and the time to discharge the pixels. The time required to discharge the pixels is a constant. Therefore,
the minimum integration period is simply a function of the clock frequency and the number of pixels in the array.
A slower clock speed increases the minimum integration time and reduces the maximum light level for saturation
on the output. The minimum integration time shown in this data sheet is based on the maximum clock frequency
of 5 MHz.
The minimum integration time can be calculated from the equation:
where:
n
is the number of pixels
ni
n
1
ǒmaximum clock
Ǔ
frequency
ca
T int(min) +
ch
In the case of the TSL201CL, the minimum integration time would be:
T int(min) + 200 ns
64 + 12.8 ms
Te
It is important to note that not all pixels will have the same integration time if the clock frequency is varied while
data is being output.
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TSL201CL
64 1 LINEAR SENSOR ARRAY
TAOS146 − APRIL 2012
APPLICATION INFORMATION
It is good practice on initial power up to run the clock (n+1) times after the first SI pulse to clock out indeterminate
data from power up. After that, the SI pulse is valid from the time following (n+1) clocks. The output will go into
a high-impedance state after the n+1 high clock edge. It is good practice to leave the clock in a low state when
inactive because the SI pulse required to start a new cycle is a low-to-high transition.
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The integration time chosen is valid as long as it falls in the range between the minimum and maximum limits
for integration time. If the amount of light incident on the array during a given integration period produces a
saturated output (Max Voltage output), then the data is not accurate. If this occurs, the integration period should
be reduced until the analog output voltage for each pixel falls below the saturation level. The goal of reducing
the period of time the light sampling window is active is to lower the output voltage level to prevent saturation.
However, the integration time must still be greater than or equal to the minimum integration period.
lv
If the light intensity produces an output below desired signal levels, the output voltage level can be increased
by increasing the integration period provided that the maximum integration time is not exceeded. The maximum
integration time is limited by the length of time the integrating capacitors on the pixels can hold their accumulated
charge. The maximum integration time should not exceed 100 ms for accurate measurements.
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Although the linear array is capable of running over a wide range of operating frequencies up to a maximum
of 5 MHz, the speed of the A/D converter used in the application is likely to be the limiter for the maximum clock
frequency. The voltage output is available for the whole period of the clock, so the setup and hold times required
for the analog-to-digital conversion must be less than the clock period.
Copyright E 2012, TAOS Inc.
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TSL201CL
64 1 LINEAR SENSOR ARRAY
TAOS146 − APRIL 2012
APPLICATION INFORMATION: HARDWARE
PCB Pad Layout
Suggested PCB pad layout guidelines for the CL package are shown in Figure 5.
1.3
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Pin 1
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1.4
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2.5
0.8
0.8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
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Figure 5. Suggested CL Package PCB Layout
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TSL201CL
64 1 LINEAR SENSOR ARRAY
TAOS146 − APRIL 2012
PACKAGE INFORMATION
TOP VIEW
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0.120
(Note B)
3.0 0.2
7.943 (Note B)
Photodiode Array
(Not to Scale)
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9.4 0.2
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Pin 1
SIDE VIEW
END VIEW
0.22
BOTTOM
VIEW
CL of Solder Contact
CL of Pixel 1 (Note C)
1.2 0.2
Photodiode Array
(Not to Scale)
0.026 Nominal
Pin 1
0.8
0.95
0.6
0.95
0.274
Nominal
CL of Package
ca
1.8
CL of Photodiode Array Area (Note C)
2.5
1.0
Pb
ni
0.6
7.5 0.08
Te
ch
NOTES: A. All linear dimensions are in millimeters. Dimension tolerance is ± 0.05 mm unless otherwise noted.
B. Nominal photodiode array dimension. The array is made up of 64 pixels with pixel #1 closer to Pin 1. Each pixel is 68 μm wide
by 120 μm high, spaced on 125 μm centers.
C. The die is centered within the package within a tolerance of ± 0.05 mm.
D. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.56.
E. Contact finish is soft gold plated.
F. This package contains no lead (Pb).
G. This drawing is subject to change without notice.
Copyright E 2012, TAOS Inc.
Figure 6. Package CL Configuration
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TSL201CL
64 1 LINEAR SENSOR ARRAY
TAOS146 − APRIL 2012
CARRIER TAPE AND REEL INFORMATION
TOP VIEW
2.00
4.00
8.00
1.50
+ 0.10
− 0.00
1.75
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B
16.00
+ 0.30
− 0.10
1.50
+ 0.25
− 0.00
A
B
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7.50
DETAIL B
DETAIL A
8 Max
7 Max
0.30
0.02
3.45
9.85
1.53
Bo
Ko
ch
ni
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Ao
Te
NOTES: A.
B.
C.
D.
E.
F.
G.
All linear dimensions are in millimeters. Dimension tolerance is ± 0.10 mm unless otherwise noted.
The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481−B 2001.
Each reel is 178 millimeters in diameter and contains 1000 parts.
TAOS packaging tape and reel conform to the requirements of EIA Standard 481−B.
In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
This drawing is subject to change without notice.
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Figure 7. Package CL Carrier Tape
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TSL201CL
64 1 LINEAR SENSOR ARRAY
TAOS146 − APRIL 2012
SOLDERING INFORMATION
The CL package has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate.
Table 1. Solder Reflow Profile
PARAMETER
REFERENCE
DEVICE
Average temperature gradient in preheating
tsoak
2 to 3 minutes
Time above 217°C (T1)
t1
Max 60 sec
Time above 230°C (T2)
t2
Max 50 sec
Time above Tpeak −10°C (T3)
t3
Max 10 sec
Tpeak
260°C
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Peak temperature in reflow
Temperature gradient in cooling
Tpeak
lv
Soak time
2.5°C/sec
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The solder reflow profile describes the expected maximum heat exposure of components during the solder
reflow process of product on a PCB. Temperature is measured on top of component. The components should
be limited to a maximum of three passes through this solder reflow profile.
Max −5°C/sec
Not to scale — for reference only
T3
T2
ca
Temperature (C)
T1
Time (sec)
t3
ni
t2
t1
Figure 8. Solder Reflow Profile Graph
Te
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tsoak
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TSL201CL
64 1 LINEAR SENSOR ARRAY
TAOS146 − APRIL 2012
STORAGE INFORMATION
Moisture Sensitivity
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Optical characteristics of the device can be adversely affected during the soldering process by the release and
vaporization of moisture that has been previously absorbed into the package. To ensure the package contains
the smallest amount of absorbed moisture possible, each device is dry-baked prior to being packed for shipping.
Devices are packed in a sealed aluminized envelope called a moisture barrier bag with silica gel to protect them
from ambient moisture during shipping, handling, and storage before use.
The CL package has been assigned a moisture sensitivity level of MSL 5a and the devices should be stored
under the following conditions:
5°C to 50°C
60% maximum
6 months from the date code on the aluminized envelope — if unopened
24 hours or fewer
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Temperature Range
Relative Humidity
Total Time
Opened Time
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Rebaking will be required if the devices have been stored unopened for more than 6 months or if the aluminized
envelope has been open for more than 24 hours. If rebaking is required, it should be done at 60°C for 24 hours.
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TSL201CL
64 1 LINEAR SENSOR ARRAY
TAOS146 − APRIL 2012
PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.
LEAD-FREE (Pb-FREE) and GREEN STATEMENT
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Pb-Free (RoHS) TAOS’ terms Lead-Free or Pb-Free mean semiconductor products that are compatible with the current
RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous
materials. Where designed to be soldered at high temperatures, TAOS Pb-Free products are suitable for use in specified
lead-free processes.
Green (RoHS & no Sb/Br) TAOS defines Green to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and
Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).
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Important Information and Disclaimer The information provided in this statement represents TAOS’ knowledge and
belief as of the date that it is provided. TAOS bases its knowledge and belief on information provided by third parties,
and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate
information from third parties. TAOS has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and
chemicals. TAOS and TAOS suppliers consider certain information to be proprietary, and thus CAS numbers and other
limited information may not be available for release.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this
document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.
TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product
design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages.
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TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
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LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced
Optoelectronic Solutions Incorporated.
Copyright E 2012, TAOS Inc.
The LUMENOLOGY r Company
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www.taosinc.com