TI TPS65010RGZ

TPS65010
www.ti.com
SLVS149A – JUNE 2003 – REVISED JANUARY 2004
POWER AND BATTERY MANAGEMENT IC
FOR Li-ION POWERED SYSTEMS
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Linear Charger Management for Single Li-Ion
or Li-Polymer Cells
Dual Input Ports for Charging From USB or
From Wall Plug, Handles 100-mA / 500-mA
USB Requirements
Charge Current Programmable Via External
Resistor
1 A, 95% Efficient Step-Down Converter for
I/O and Peripheral Components (VMAIN)
400 mA, 90% Efficient Step-Down Converter
for Processor Core (VCORE)
2x 200-mA LDOs for I/O and Peripheral
Components, LDO Enable via Bus
Serial Interface Compatible With I2C, Supports
100-kHz, 400-kHz Operation
LOW_PWR Pin to Lower or Disable Processor
Core Supply Voltage in Deep Sleep Mode
70-µA Quiescent Current
1% Reference Voltage
Thermal Shutdown Protection
APPLICATIONS
•
•
•
All Single Li-Ion Cell Operated Products
Requiring Multiple Supplies Including:
– PDA
– Cellular/Smart Phone
– Internet Audio Player
– Digital Still Camera
Digital Radio Player
Split Supply DSP and µP Solutions
DESCRIPTION
The TPS65010 is an integrated power and battery
management IC for applications powered by one
Li-Ion or Li-Polymer cell, and which require multiple
power rails. The TPS65010 provides two highly
efficient, step-down converters targeted at providing
the core voltage and peripheral, I/O rails in a processor-based system. Both step-down converters enter a low power mode at light load for maximum
efficiency across the widest possible range of load
currents. The LOW_PWR pin allows the core converter to lower its output voltage when the application
processor goes into deep sleep. The TPS65010 also
integrates two 200-mA LDO voltage regulators, which
are enabled via the serial interface. Each LDO
operates with an input voltage range between 1.8 V
and 6.5 V, allowing them to be supplied from one of
the step-down converters or directly from the battery.
The TPS65010 also has a highly integrated and
flexible Li-Ion linear charger and system power management. It offers integrated USB-port and
ac-adapter supply management with autonomous
power-source selection, power FET and current
sensor, high accuracy current and voltage regulation,
charge status, and charge termination.
The TPS65010 charger automatically selects the
USB-Port or the ac-adapter as the power source for
the system. In the USB configuration, the host can
increase the charge current from the default value of
maximum 100 mA to 500 mA via the interface. In the
ac-adapter configuration an external resistor sets the
maximum value of charge current.
The battery is charged in three phases: conditioning,
constant current, and constant voltage. Charge is
normally terminated based on minimum current. An
internal charge timer provides a safety backup for
charge termination. The TPS65010 automatically
restarts the charge if the battery voltage falls below
an internal threshold. The charger automatically enters sleep mode when both supplies are removed.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of Phillips.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2004, Texas Instruments Incorporated
TPS65010
www.ti.com
SLVS149A – JUNE 2003 – REVISED JANUARY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
The serial interface can be used for dynamic voltage scaling, for collecting information on and controlling the
battery charger status, for optionally controlling 2 LED driver outputs, a vibrator driver, masking interrupts, or for
disabling/enabling and setting the LDO output voltages. The interface is compatible with the fast/standard mode
I2C™ specification allowing transfers at up to 400 kHz.
ORDERING INFORMATION
(1)
TA
PACKAGE
PART NUMBER (1)
-40°C to 85°C
7 mm × 7 mm, 48-pin QFN
TPS65010RGZ
The RGZ package is available in tape and reel. Add R suffix (TPS65010RGZR) to order quantities of 2500 parts per reel. Add T suffix
(TPS65010RGZT) to order quantities of 250 parts per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNIT
Input voltage on VAC pin with respect to AGND
20 V
Input voltage range on all other pins except AGND/PGND pins with respect to AGND
-0.3 V to 7 V
HBM and CBM capabilities at pins VIB, PG, and LED2
1 kV
Current at AC, VBAT, VINMAIN, L1, PGND1
1800 mA
Peak current at all other pins
1000 mA
Continuous power dissipation
See Dissipation Rating Table
Operating free-air temperature, TA
-40°C to 85°C
Maximum junction temperature, TJ
125°C
Storage temperature, Tstg
-65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE DISSIPATION RATINGS (1)
AMBIENT TEMPERATURE
(1)
(2)
2
MAX POWER DISSIPATION FOR Tj= 125°C (2)
25°C
3W
55°C
2.1 W
DERATING FACTOR ABOVE TA = 55°C
30 mW/°C
The TPS65010 is housed in a 48-pin QFN package with exposed leadframe on the underside. This 7 mm × 7 mm package exhibits a
thermal impedance (junction-to-ambient) of 33 K/W when mounted on a JEDEC high-k board.
Consideration needs to be given to the maximum charge current when the assembled application board exhibits a thermal impedance
which differs significantly from the JEDEC high-k board.
TPS65010
www.ti.com
SLVS149A – JUNE 2003 – REVISED JANUARY 2004
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
V(AC)
Supply voltage from ac adapter
4.5
5.5
V
V(USB)
Supply voltage from USB
4.4
5.25
V
V(BAT)
Voltage at charger output/battery
2.5
CI(AC)
Input capacitor at ac input
1
µF
CI(USB)
Input capacitor at USB input
1
µF
CI(BAT)
Input capacitor at VBAT output
VI(MAIN),VI(CORE),VCC
Input voltage range step-down convertors
2.5
6.0
V
VO(MAIN)
Output voltage range for main step-down
convertor
2.5
3.3
V
VI(CORE)
Output voltage range for core step-down
convertor
0.85
1.6
VI(LDO1), VI(LDO2)
Input voltage range for LDOs
1.8
6.5
VO(LDO1-2)
Output voltage range for LDOs
0.9
VI(LDO1-2)
IO(L1)
Maximum output current at L1
L(L1)
Inductor at L1
4.2
0.1
Input capacitor at
Input capacitor at VINMAIN
CI(CORE)
Input capacitor at VINCORE
CO(1)
Output capacitor at VMAIN
IO(L2)
Maximum output current at L2
L(L2)
Inductor at L2
CO(2)
Output capacitor at VCORE
V
V
mA
VCC (1)
CI(MAIN)
µF
1000
(1)
CI(VCC)
V
(1)
(1)
(1)
6.8
µH
1
µF
22
µF
10
µF
22
µF
400
mA
(1)
(1)
(1)
10
µH
10
µF
1
µF
CI(1-2)
Input capacitor at VINLDO1, VINLDO2
CO(1-2)
Output capacitor at VLDO1-2
IO(LDO1,2)
Maximum output current at VLDO1,2
200
TA
Operating ambient temperature
-40
85
°C
TJ
Operating junction temperature
-40
125
°C
R(CC)
Resistor from VI(main),VI(core) to VCC used for
filtering, CI(VCC) = 1 µF
100
Ω
(1)
(1)
2.2
µF
mA
10
See applications section for more information
ELECTRICAL CHARACTERISTICS
VI(MAIN) = VI(CORE) = VCC = VI(LDO1) = VI(LDO2) = 3.6 V, TA = -40°C to 85°C, typical values are at TA = 25°C battery charger
specifications are valid in the range 0°C < TA < 85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2
VCC
V
0
0.8
V
1.0
µA
0.8 VCC
6
V
0
0.4
Control Signals: LOW_PWR, SCLK, SDAT (Input)
VIH
High level input voltage
IIH = 20 µA
VIL
Low level input voltage
IIL = 10 µA
IIB
Input bias current
(1)
0.01
Control Signals: PB_ONOFF, HOT_RESET, BATT_COVER
VIH
High level input voltage
IIH = 20 µA (1)
VIL
Low level input voltage
IIL = 10 µA
R(pb_onoff)
Pulldown resistor at PB_ONOFF
1000
kΩ
R(hot_reset)
Pullup resistor at HOT_RESET,
connected to VCC
1000
kΩ
R(batt_cover)
Pulldown resistor at BATT_COVER
t(glitch)
De-glitch time at all 3 pins
(1)
2000
38
56
V
kΩ
77
ms
If the input voltage is higher than VCC, an additional input current, limited by an internal 10-k resister, flows.
3
TPS65010
www.ti.com
SLVS149A – JUNE 2003 – REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS (continued)
VI(MAIN) = VI(CORE) = VCC = VI(LDO1) = VI(LDO2) = 3.6 V, TA = -40°C to 85°C, typical values are at TA = 25°C battery charger
specifications are valid in the range 0°C < TA < 85°C unless otherwise noted
PARAMETER
t(batt_cover)
TEST CONDITIONS
Delay after t(glitch) (PWRFAIL goes low)
before supplies are disabled when
BATT_COVER goes low.
MIN
TYP
MAX
1.68
2.4
3.2
UNIT
ms
CONTROL SIGNALS: MPU_RESET, PWRFAIL, RESPWRON, INT, SDAT (output)
VOH
High level output voltage
VOL
Low level output voltage
6
td(mpu_nreset)
Duration of low pulse at MPU_RESET
td(nrespwron)
Duration of low pulse at RESPWRON after
VLDO1 is in regulation
IIL = 10 mA
0
0.3
100
CHGCONFIG<7> = 0(Default)
CHGCONFIG<7> = 1
V
V
µs
800
1000
1200
49
69
89
ms
td(uvlo)
Time between UVLO going active
(PWRFAIL going low) and supplies being
disabled
1.68
2.4
3.2
ms
td(overtemp)
Time between chip overtemperature condition being recognized (PWRFAIL going
low) and supplies being disabled
1.68
2.4
3.2
ms
58
µA
25
µA
SUPPLY PIN: VCC
I(Q)
IO(SD)
Operating quiescent current
VI = 3.6 V, current into Main + Core + VCC
Shutdown supply current
VI = 3.6 V, BATT_COVER = GND,
Current into Main + Core + VCC
15
VMAIN STEP-DOWN CONVERTER
VI
Input voltage range
IO
Maximum output current
2.5
IO(SD)
Shutdown supply current
BATT_COVER = GND
0.1
1
µA
rDS(on)
P-channel MOSFET on-resistance
VI(MAIN) = VGS = 3.6 V
110
210
mΩ
Ilkg(p)
P-channel leakage current
V(DS) = 6.0 V
1
µA
rDS(on)
N-channel MOSFET on-resistance
VI(MAIN) = VGS = 3.6 V
110
200
mΩ
Ilkg(N)
N-channel leakage current
V(DS) = 6.0 V
1
µA
IL
P-channel current limit
2.5 V< VI(MAIN) < 6.0 V
1.4
1.75
2.1
A
fS
Oscillator frequency
1
1.25
1.5
MHz
2.5 V
2.75 V
VO(MAIN)
Fixed output voltage
3.0 V
3.3 V
R(VMAIN)
4
0%
3%
VI(MAIN) = 2.7 V to 6.0 V;
0 mA ≤ IO≤ 1000 mA
3%
3%
VI(MAIN) = 2.95 V to 6.0 V; IO= 0 mA
0%
3%
VI(MAIN) = 2.95 V to 6.0 V;
0 mA ≤ IO≤ 1000 mA
3%
3%
VI(MAIN) = 3.2 V to 6.0 V; IO= 0 mA
0%
3%
VI(MAIN) = 3.2 V to 6.0 V;
0 mA ≤ IO≤ 1000 mA
3%
3%
VI(MAIN) = 3.5 V to 6.0 V; IO= 0 mA
0%
3%
VI(MAIN) = 3.5 V to 6.0 V;
0 mA ≤ IO≤ 1000 mA
3%
3%
VI(MAIN) = VO(MAIN) + 0.5 V (min. 2.5 V) to
6.0 V, IO = 10 mA
Load regulation
IO = 10 mA to 1000 mA
V
mA
VI(MAIN) = 2.7 V to 6.0 V; IO= 0 mA
Line regulation
VMAIN discharge resistance
6.0
1000
0.5
%/V
0.12
%/A
400
Ω
TPS65010
www.ti.com
SLVS149A – JUNE 2003 – REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS (continued)
VI(MAIN) = VI(CORE) = VCC = VI(LDO1) = VI(LDO2) = 3.6 V, TA = -40°C to 85°C, typical values are at TA = 25°C battery charger
specifications are valid in the range 0°C < TA < 85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCORE STEP-DOWN CONVERTER
VI
Input voltage range
2.5
IO
Maximum output current
400
IO(SD)
Shutdown supply current
BATT_COVER = GND
0.1
1
µA
rDS(on)
P-channel MOSFET on-resistance
VI(CORE) = VGS = 3.6 V
275
530
mΩ
Ilkg(p)
P-channel leakage current
VDS = 6.0 V
0.1
1
µA
rDS(on)
N-channel MOSFET on-resistance
VI(CORE) = VGS = 3.6 V
275
500
mΩ
Ilkg(N)
N-channel leakage current
VDS = 6.0 V
IL
P-channel current limit
2.5 V< VI(CORE) < 6.0 V
fS
Oscillator frequency
0.85 V
1.0 V
1.1 V
VO(CORE)
Fixed output voltage
1.2 V
1.3 V
1.4 V
1.5 V
1.6 V
R(VCORE)
6.0
0.1
1
µA
600
700
900
mA
1
1.25
1.5
MHz
VI(CORE) = 2.5 V to 6.0 V;
IO= 0 mA, CO= 22 µF
0%
3%
VI(CORE) = 2.5 V to 6.0 V;
0 mA ≤ IO≤ 400 mA, CO= 22 µF
3%
3%
VI(CORE) = 2.5 V to 6.0 V;
IO= 0 mA, CO= 22 µF
0%
3%
VI(CORE) = 2.5 V to 6.0 V;
0 mA ≤ IO≤ 400 mA, CO= 22 µF
3%
3%
VI(CORE) = 2.5 V to 6.0 V;
IO= 0 mA, CO= 22 µF
0%
3%
VI(CORE) = 2.5 V to 6.0 V;
0 mA ≤ IO≤ 400 mA, CO= 22 µF
3%
3%
VI(CORE) = 2.5 V to 6.0 V; IO= 0 mA
0%
3%
VI(CORE) = 2.5 V to 6.0 V; 0 mA ≤ IO≤ 400
mA
3%
3%
VI(CORE) = 2.5 V to 6.0 V; IO= 0 mA
0%
3%
VI(CORE) = 2.5 V to 6.0 V;
0 mA ≤ IO≤ 400 mA
3%
3%
VI(CORE) = 2.5 V to 6.0 V; IO= 0 mA
0%
3%
VI(CORE) = 2.5 V to 6.0 V;
0 mA ≤ IO≤ 400 mA
3%
3%
VI(CORE) = 2.5 V to 6.0 V; IO= 0 mA
0%
3%
VI(CORE) = 2.5 V to 6.0 V;
0 mA ≤ IO≤ 400 mA
3%
3%
VI(CORE) = 2.5 V to 6.0 V; IO= 0 mA
0%
3%
VI(CORE) = 2.5 V to 6.0 V;
0 mA ≤ IO≤ 400 mA
3%
3%
Line regulation
VI(CORE) = VO(MAIN) + 0.5 V
(min. 2.5 V) to 6.00 V, IO = 10 mA
Load regulation
IO = 10 mA to 400 mA
V
mA
1
%/V
0.002
VCORE discharge resistance
%/mA
Ω
400
VLDO1 and VLDO2 LOW-DROPOUT REGULATORS
VI
Input voltage range
1.8
6.5
VO
LDO1 output voltage range
0.9
VINLDO1
Vref
Reference voltage
485
VO
LDO2 output voltage range
500
1.8
Full-power mode
200
Low-power mode
30
IO
Maximum output current
I(SC)
LDO1 & LDO2 short-circuit current limit
VLDO1 = GND, VLDO2 = GND
Dropout voltage
IO= 200 mA, VINLDO1,2 = 1.8 V
3.0
V
mV
V
mA
650
mA
300
mV
±3%
Total accuracy
Line regulation
515
V
VINLDO1,2 = VLDO1,2 + 0.5 V
(min. 2.5 V) to 6.5 V, IO = 10 mA
0.75
%/V
5
TPS65010
www.ti.com
SLVS149A – JUNE 2003 – REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS (continued)
VI(MAIN) = VI(CORE) = VCC = VI(LDO1) = VI(LDO2) = 3.6 V, TA = -40°C to 85°C, typical values are at TA = 25°C battery charger
specifications are valid in the range 0°C < TA < 85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
Load regulation
MIN
TYP
IO = 10 mA to 200 mA
MAX
%/mA
Load change from 10% to 90%
Regulation time
UNIT
0.011
0.1
Low-power mode
0.1
ms
I(QFP)
LDO quiescent current (each LDO)
Full-power mode
16
30
µA
I(QLPM)
LDO quiescent current (each LDO)
Low-power mode
12
18
µA
IO(SD)
LDO shutdown current (each LDO)
0.1
1
µA
Ilkg(FB)
Leakage current feedback
0.01
0.1
µA
MAX
UNIT
ELECTRICAL CHARACTERISTICS
Battery Charger, VO(REG) + V(DO-MAX) ≤ V(CHG) = V(AC) or V(USB), I(TERM) < IO≤ 1 A, 0°C < TA< 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
V(AC)
Input voltage range
4.5
5.5
V(USB)
Input voltage range
4.35
5.25
ICC(VCHG)
Supply current
V(CHG) > V(CHG)min
ICC(SLP)
Sleep current
Sum of currents into VBAT pin,
V(CHG) < V(SLP-ENTRY),
0°C≤ TJ ≤ 85°C
ICC(STBY)
Standby current
V
1.2
2
mA
2
5
µA
200
400
Current into USB pin
40
Current into AC pin
V
µA
VOLTAGE REGULATOR
VO
VDO
Output voltage
V(CHG)min ≥ 4.5 V
4.20
4.25
Dropout voltage (V(AC) - VBAT)
VO(REG) + V(DO-MAX) ≤ V(CHG),
IO(OUT) = 1 A
500
800
Dropout voltage (V(USB) - VBAT)
VO(REG) + V(DO-MAX)≤ V(CHG),
IO(OUT) = 0.5 A
300
500
Dropout voltage (V(USB) - VBAT)
VO(REG) + V(DO-MAX) ≤ V(CHG),
IO(OUT) = 0.1 A
100
150
4.15
V
mV
CURRENT REGULATION
Output current range for ac operation (1)
IO(AC)
VCHG ≥ 4.5V, VI(OUT) > V(LOWV),
V(AC) - VI(BAT)> V(DO-MAX)
Output current set voltage for ac operation at ISET
pin. 100% output current I2C register
CHGCONFIG<4:3> = 11
V(SET)
KSET
IO(USB)
R(ISET)
75% output current I2C register CHGCONFIG<4:3> =
10
50% output current
01
I2C
register CHGCONFIG<4:3> =
32% output current
00
I2C
register CHGCONFIG<4:3> =
Output current set factor for ac operation
Output current range for USB operation
Resistor range at ISET pin
KSET V
I
(1)
6
O(AC)
R
(SET)
(ISET)
Vmin ≥ 4.5V, VI(BAT) > V(LOWV), V(AC) VI(BAT) > V(DO-MAX)
100 mA < IO < 1000 mA
100
1000
2.45
2.50
2.55
1.83
1.91
1.99
1.23
1.31
1.39
0.76
0.81
0.86
310
330
350
V(CHG)min ≥ 4.35 V, VI(BAT) > V(LOWV),
V(USB) - VI(BAT)> V(DO-MAX),
I2C register CHGCONFIG<2> = 0
80
V(CHG)min ≥ 4.5 V, VI(BAT) > V(LOWV),
VUSB - VI(BAT) > V(DO-MAX),
I2C register CHGCONFIG<2> = 1
400
500
825
8250
mA
V
mA
100
mA
Ω
TPS65010
www.ti.com
SLVS149A – JUNE 2003 – REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS (continued)
Battery Charger, VO(REG) + V(DO-MAX) ≤ V(CHG) = V(AC) or V(USB), I(TERM) < IO≤ 1 A, 0°C < TA< 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PRECHARGE CURRENT REGULATION, SHORT-CIRCUIT CURRENT, AND BATTERY DETECTION CURRENT
V(LOWV)
Precharge to fast-charge transition threshold,
voltage on VBAT pin.
V(CHG)min ≥ 4.5V
2.8
3.0
3.2
V
Deglitch time
V(CHG)min ≥ 4.5 V, VI(OUT) decreasing
below threshold; 100-ns fall time,
10-mV overdrive
250
375
500
ms
100
mA
270
mV
0 ≤ VI(OUT) < V(LOWV), t < t(PRECHG)
(2)
I(PRECHG)
Precharge current
I(DETECT)
Battery detection current
V(SET-PRECHG)
Voltage at ISET pin
10
200
0 ≤ VI(OUT) < V(LOWV), t < t(PRECHG)
240
255
µA
CHARGE TAPER AND TERMINATION DETECTION
(3)
I(TAPER)
Taper current detect range
VI(OUT) > V(RCH), t < t(TAPER)
10
100
mA
V(SET_TAPER)
Voltage at ISET pin for charge TAPER detection
VI(OUT) > V(RCH), t < t(TAPER)
235
250
265
mV
V(SET_TERM)
Voltage at ISET pin for charger termination
detection (4)
VI(OUT) > V(RCH)
11
18
25
mV
Deglitch time for I(TAPER)
V(CHG)min ≥ 4.5V, charging current
increasing or decreasing above and
below; 100-ns fall time, 10-mV
overdrive
250
375
500
ms
Deglitch time for I(TERM)
V(CHG)min ≥ 4.5 V, charging current
decreasing below;100-ns fall time,
10-mV overdrive
250
375
500
ms
TEMPERATURE COMPARATOR
V(LTF)
Low (cold) temperature threshold
2.475
2.50
2.525
V(HTF)
High (hot) temperature threshold
0.485
0.5
0.515
V
I(TS)
TS current source
95
102
110
µA
250
375
500
ms
VO(REG)
-0.115
VO(REG)
-0.1
VO(REG)
-0.085
250
375
500
ms
Deglitch time for temperature fault
V
BATTERY RECHARGE THRESHOLD
V(RCH)
Recharge threshold
V(CHG)min≥ 4.5 V
V
Deglitch time
V(CHG)min ≥ 4.5 V, VI(OUT) decreasing
below threshold; 100 ns fall time,
10 mV overdrive
t(PRECHG)
Precharge timer
V(CHG)min ≥ 4.5 V
1500
1800
2160
sec
t(TAPER)
Taper timer
V(CHG)min≥ 4.5 V
1500
1800
2160
sec
t(CHG)
Charge timer
V(CHG)min≥ 4.5 V
15000
18000
21600
sec
TIMERS
SLEEP AND STANDBY
V(SLP-ENTRY)
Sleep-mode entry threshold, PG output = high
2.3 V≤ VI(OUT) ≤ VO(REG)
V(SLP_EXIT)
Sleep-mode exit threshold,PG output = low
2.3 V≤ VI(OUT) ≤ VO(REG)
Deglitch time for sleep mode entry and exit
AC or USB decreasing below
threshold; 100-ns fall time, 10-mV
overdrive
t(USB_DEL)
Delay between valid USB voltage being applied and
start of charging process from USB
V(CHG) ≤
VI(OUT)
+150 mV
V(CHG) ≥
VI(OUT)+19
0 mV
200
V
V
375
375
500
ms
ms
KSET V
I
(PRECHG)
(SET_PRECHG)
R
(ISET)
(2)
KSET V
I
(TAPER)
R
(3)
KSET V
I
(4)
(TERM)
R
(SET_TAPER)
(ISET)
(SET_TERM)
(ISET)
7
TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS (continued)
Battery Charger, VO(REG) + V(DO-MAX) ≤ V(CHG) = V(AC) or V(USB), I(TERM) < IO≤ 1 A, 0°C < TA< 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.27
2.5
2.75
UNIT
CHARGER POWER-ON-RESET, UVLO, AND V(IN) RAMP RATE
V(CHGUVLO)
Charger undervoltage lockout
V(CHG) decreasing
Hysteresis
V(CHGOVLO)
27
Charger overvoltage lockout
V(AC) increasing
6.6
Hysteresis
V
mV
V
0.5
V
CHARGER OVERTEMPERATURE SUSPEND
T(suspend)
Temperature at which charger suspends
operation
T(hyst)
Hysteresis of suspend threshold
145
°C
20
°C
LOGIC SIGNALS DEFMAIN, DEFCORE, PS_SEQ, IFLSB
VIH
High level input voltage
IIH = 20 µA
VCC-0.5
VCC
VIL
Low level input voltage
IIL = 10 µA
0
0.4
V
IIB
Input bias current
1.0
µA
0.3
V
0.01
V
LOGIC SIGNALS GPIO1-4
VOL
Low level output voltage
IOL = 1 mA, configured as an open
drain output
VOH
High level output voltage
Configured as an open drain output
6
V
VIL
Low level input voltage
0
0.8
V
VIH
High level input voltage
2
VCC (5)
V
II
Input leakage current
1
µA
rDS(on)
Internal NMOS
VOL = 0.3 V
Ω
150
LOGIC SIGNALS PG, LED2
VOL
Low level output voltage
VOH
High level output voltage
V(PG)
IOL = 20 mA
0.5
V
6
V
V(BAT) + xx
mV
PG threshold voltage USB and AC
V
VIBRATOR DRIVER VIB
VOL
Low level output voltage
VOH
High level output voltage
IOL = 100 mA
0.3
0.5
V
6
V
THERMAL SHUTDOWN
T(SD)
Thermal shutdown
Increasing junction temperature
°C
160
UNDERVOLTAGE LOCK OUT
V(UVLO)
Undervoltage lockout
threshold
V(UVLO) 2.5 V
-3%
3%
V(UVLO) 2.75 V
-3%
3%
-3%
3%
V(UVLO) 3.0 V
Default value
V(UVLO_HYST)
Filter resistor = 10R in series
with VCC, VCC decreasing
V(UVLO) 3.25 V
UVLO comparator hysteresis
VCC rising
-3%
3%
150
200
POWER GOOD
(5)
8
VMAIN, VCORE, VLDO1, VLDO2
decreasing
-12%
-10%
-8%
VMAIN, VCORE, VLDO1, VLDO2
increasing
-7%
-5%
-3%
If the input voltage is higher than VCC an additional current, limited by an internal 10-kΩ resistor, flows.
mV
TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
SERIAL INTERFACE TIMING REQUIREMENTS
MIN MAX UNIT
Clock frequency, fMAX
400
Clock high time, twH(HIGH)
600
Clock low time, twL(LOW)
kHz
ns
1300
ns
DATA and CLK rise time, tR
300
ns
DATA and CLK fall time, tF
300
ns
Hold time (repeated) START condition (after this period the first clock pulse is generated), th(STA)
600
ns
Setup time for repeated START condition, th(DATA)
600
ns
0
ns
Data input setup time, tsu(DATA)
100
ns
STOP condition setup time, tsu(STO)
600
ns
1300
ns
Data input hold time, th(DATA)
Bus free time, t(BUF)
PIN ASSIGNMENTS
LOW_PWR
INT
PWRFAIL
RESPWRON
MPU_RESET
HOT_RESET
SCLK
SDAT
IFLSB
NC
GPIO1
GPIO2
RGZ PACKAGE
(TOP VIEW)
36 35 34 33 32 31 30 29 28 27 26
37
38
39
40
41
42
43
44
45
46
47
48
1
25
24
23
22
21
20
19
18
17
16
15
14
13
2 3 4 5 6 7 8 9 10 11 12
VLDO1
VFB_LDO1
VINLDO1
AGND1
VLDO2
VINLDO2
GPIO3
GPIO4
PGND1_B
PGND1_A
PS_SEQ
VMAIN
DEFCORE
LED2
VIB
L2
VINCORE
VCC
VINMAIN_A
VINMAIN_B
L1_A
L1_B
PG
DEFMAIN
ISET
TS
BATT_COVER
AC
VBAT_A
VBAT_B
USB
AGND2
AGND3
PGND2
PB_ONOFF
VCORE
NC - No internal connection
9
TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
PIN ASSIGNMENTS (continued)
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
CHARGER SECTION
AC
40
I
Charger input voltage from ac adapter. The AC pin can be left open or can be connected to
ground if the charger is not used.
USB
43
I
Charger input voltage from USB port. The USB pin can be left open or can be connected to
ground if the charger is not used.
ISET
37
I
External charge current setting resistor connection for use with ac adapter
VBAT_A
41
I
Sense input for the battery voltage. Connect directly with the battery.
VBAT_B
42
O
Power output of the battery charger. Connect directly with the battery.
TS
38
I
Battery temperature sense input
PG
11
O
Indicates when a valid power supply is present for the charger (open drain)
AGND2
44
Analog ground connection. All analog ground pins are connected internally on the chip.
NC
27
Connect this pin to GND.
PowerPAD™
-
Connect the PowerPAD to GND
SWITCHING REGULATOR SECTION
AGND3
45
VINMAIN_A,
VINMAIN_B
7,8
L1_A, L1_B
9,10
Analog ground connection. All analog ground pins are connected internally on the chip.
I
Input voltage for VMAIN step-down converter. This must be connected to the same voltage
supply as VINCORE and VCC.
Switch pin of VMAIN converter. The VMAIN inductor is connected here.
VMAIN
13
I
VMAIN feedback voltage sense input, connect directly to VMAIN
VCC
6
I
Power supply for digital and analog circuitry of MAIN and CORE dc-dc converters. This
must be connected to the same voltage supply as VINCORE and VINMAIN. Also supplies
serial interface block
PGND1_A,
PGND1_B
VINCORE
Power ground for VMAIN converter
15,16
5
L2
4
VCORE
48
PGND2
46
I
Input voltage for VCORE step-down converter. This must be connected to the same voltage
supply as VINMAIN and VCC.
Switch pin of VCORE converter. The VCORE inductor is connected here.
I
VCORE feedback voltage sense input, connect directly to VCORE
Power ground for VCORE converter
LDO REGULATOR SECTION
AGND1
21
VINLDO1
22
I
Analogue ground connection. All analog ground pins are connected internally on the chip.
Input voltage for LDO1
VLDO1
24
O
Output voltage for LDO1
VFB_LDO1
23
I
Feedback input from external resistive divider for LDO1
VINLDO2
19
I
Input voltage for LDO2
VLDO2
20
O
Output and feedback voltage for LDO2
LED2
2
O
LED driver, with blink rate programmable via serial interface
VIB
3
O
Vibrator driver, enabled via serial interface
DRIVER SECTION
CONTROL AND I2C SECTION
PS_SEQ
14
I
Sets power-up/down sequence of step-down converters
PB_ONOFF
47
I
Push button enable pin, also used to wake-up processor from low power mode
BATT_COVER
39
I
Indicates if battery cover is in place
HOT_RESET
31
I
Push button reset input used to reboot or wake-up processor via TPS65010
MPU_RESET
32
O
Open drain reset output generated by user activated HOT_RESET
RESPWRON
33
O
Open drain system reset output, generated according to the state of the LDO1 output
voltage
10
TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
PIN ASSIGNMENTS (continued)
Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
CHARGER SECTION
PWRFAIL
O
Open drain output. Active low when UVLO comparator indicates low VBAT condition or
when shutdown is about to occur due to an overtemperature condition or when the battery
cover is removed (BATT_COVER has gone low).
O
Indicates a charge fault or termination, or if any of the regulator outputs are below the lower
tolerance level, active low (open drain)
34
INT
35
LOW_PWR
36
I
Input signal indicating deep sleep mode, VCORE is lowered to predefined value or disabled
DEFMAIN
12
I
Input signal indicating default VMAIN voltage, 0 = 3.0 V, 1 = 3.3 V
DEFCORE
1
I
Input signal indicating default VCORE voltage, 0 = 1.5 V, 1 = 1.6 V
SCLK
30
I
Serial interface clock line
SDAT
29
I/O
IFLSB
28
I
GPIO1
26
I/O
General-purpose open-drain input/output
GPIO2
25
I/O
General-purpose open-drain input/output
GPIO3
18
I/O
General-purpose open-drain input/output
GPIO4
17
I/O
General-purpose open-drain input/output
Serial interface data/address
LSB of serial interface address used to distinguish two devices with the same address
11
TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
FUNCTIONAL BLOCK DIAGRAM
MAX(AC,USB,VBAT)
AC
USB
VBAT
PG
Linear Charge Controller
ISET
TS
SCLK
SDAT
AGND2
Serial
Interface
IFLSB
Thermal
Shutdown
VINMAIN
PS_SEQ
LOW_PWR
PB_ONOFF
BATT_COVER
HOT_RESET
VMAIN
Control
Step-Down
Converter
RESPWRON
MPU_RESET
INT
PWRFAIL
GPIO1
GPIO2
GPIO3
GPIO4
VIB
L1
VMAIN
DEFMAIN
PGND1
VCC
AGND3
VINCORE
UVLO
VREF
OSC
L2
VCORE
VCORE
Step-Down
Converter
DEFCORE
PGND2
GPIOs
VINLDO1
VLDO1
200 mA LDO
VLDO1
VFB_LDO1
AGND1
LED2
VINLDO2
VLDO2
VLDO2
200 mA LDO
12
TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Efficiency
vs Output current
Quiescent current
vs Input voltage
1-4
Switching frequency
vs Temperature
Output voltage
vs Output current
LDO1 Output voltage
vs Output current
9
LDO2 Output voltage
vs Output current
10
5
6
7, 8
Line transient response (main)
11
Line transient response (core)
12
Line transient response (LDO1)
13
Line transient response (LDO2)
14
Load transient response (main)
15
Load transient response (core)
16
Load transient response (LDO1)
17
Load transient response (LDO2)
18
Output Voltage Ripple (PFM)
19
Output Voltage Ripple (PWM)
20
Startup timing
21
Dropout voltage
vs Output current
PSRR (LDO1 and LDO2)
vs Frequency
EFFICIENCY
vs
OUTPUT CURRENT
100
90
90
80
VO = 3.3 V
EFFICIENCY
vs
OUTPUT CURRENT
100
Main:
VI = 3.8 V,
TA = 25°C,
PFWM = 1
90
70
50
40
30
Main:
VI = 3.8 V,
TA = 25°C,
FPWM = 0
20
10
0.10
1
10
100
IO - Output Current - mA
Figure 1.
1k
10 k
60
VO = 3.3 V
Efficiency - %
60
VO = 2.5 V
50
40
40
30
20
10
10
1
10
100
IO − Output Current − mA
Figure 2.
1k
10 k
VO = 0.85 V
50
20
0.10
VO = 1.2 V
60
30
0
0.01
VO = 1.6 V
80
70
VO = 2.5 V
Efficiency − %
Efficiency - %
70
0
0.01
24
EFFICIENCY
vs
OUTPUT CURRENT
100
80
22, 23
0
0.01
Core:
VI = 3.8 V,
TA = 25°C,
FPWM = 0
0.10
1
10
100
1k
IO - Output Current - mA
Figure 3.
13
TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
EFFICIENCY
vs
OUTPUT CURRENT
QUIESCENT CURRENT
vs
INPUT VOLTAGE
70
VO = 1.2 V
60
50
VO = 0.85 V
40
30
VI = 4.2 V
1.225
TA = 85°C
50
40
TA = -40°C
TA = 25°C
30
20
20
10
10
0
0.10
1
10
100
2.5
1k
3
3.5
4
4.5
5
VI - Input Voltage - V
IO − Output Current − mA
LD01 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
LD01 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
LDO1 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.652
MAIN
FPWM = 1
VO = 3.3 V
TA = 25°C
1.642
1.632
VI = 6 V
3
CORE
FPWM = 1
VO = 1.6 V
TA = 25°C
VI = 3.3 V
VI = 3.6 V
1.622
VI = 5 V
1.612
3.301
1.602
3.281
VI = 4.2 V
1.592
1.582
VI = 4.2 V
3.241
VI = 3.6 V
3.221
1.572
10
1k
100
10 k
100 k
1.552
0
1k
100
10 k
2.70
VO = 2.5 V
2.60
2.50
2.40
2.30
VI LDO1 = 3.8 V
TA = 25°C
2
0.01
0.1
10
100
1
IO Output Current - mA
1000
Figure 7.
Figure 8.
Figure 9.
LDO2 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
LINE TRANSIENT RESPONSE
(MAIN)
LINE TRANSIENT RESPONSE
(CORE)
CH1 = VI
VO = 3 V
2.9
VO - LDO2 Output Voltage - V
100 k
IO Output Current - mA
3.1
2.7
2.5
2.3
CH2 = VO
2.1
1.9
VI = 3.6 V to 4.2 V, VO = 1.6 V,
IL = 400 mA, TA = 25°C
CH1 = VI
VI = 3.6 to 4.2 V, VO = 3.3 V,
IL = 500 mA TA = 25°C
VOLDO2 = 3.8 V
TA = 25°C
CH2 = VO
VO = 1.8 V
0.1
1
10
100
1000
500 µs/div
500 µs/div
IO - Output Current - mA
Figure 10.
14
VO = 2.8 V
2.80
2.10
VI = 6 V
10
2.90
2.20
VI = 5 V
1.562
VI = 3.3 V
IO Output Current - mA
1.7
0.01
1.200
Figure 6.
3.321
3.201
0
1.205
Figure 5.
3.341
3.261
1.210
1.195
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85
TA - Free-Air Temperature - °C
6
500 mV/div
3.361
1.215
50 mV/div
3.381
VI = 3.3 V
Figure 4.
VO - LDO1 Output Voltage - V
VO - LDO1 Output Voltage - V
3.401
5.5
VO - LDO1 Output Voltage - V
0
0.01
1.220
500 mV/div
Efficiency − %
70
60
Figure 11.
Figure 12.
50 mV/div
80
1.230
VCC, + Vcore,+ Vmain
VO = 1.6 V
Core:
VI = 3.8 V,
TA = 25°C,
PFWM = 1
Quiescent Current - µ A
90
f - Switching Frequency - MHz
100
SWITCHING FREQUENCY
vs
TEMPERATURE
TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
CH1 = VI
CH2 = VO
10 mV/div
CH2 = VO
100 µs/div
500 µs/div
500 µs/div
Figure 14.
Figure 15.
LINE TRANSIENT RESPONSE
(MAIN)
LINE TRANSIENT RESPONSE
(LDO1)
LINE TRANSIENT RESPONSE
(LDO2)
VI = 3.8 V, VI LDO = 3.3 V,
VO = 1.8 V, IL = 2 mA to 180 mA,
TA = 25°C
200 mA/div
CH2 = VO
100 µs/div
100 µs/div
Figure 17.
Figure 18.
OUTPUT RIPPLE (PFM)
OUTPUT RIPPLE (PWM)
STARTUP TIMING
CH4 = Iinductor Core
5 µs/div
VI = 3.8 V, TA = 25°C
VO Main = 3.3 V IL Main = 100 mA,
VO Core = 1.6 V, IL Core = 40 mA
Figure 19.
100 mA/div
CH2 = VO Core
CH1 = VO Main
CH3 = Iinductor Main
100 mA/div
CH1 = VO Main
CH3 = Icoil Main
CH2 = VO Core
CH2 = VO Core
CH4 = Icoil Core
CH4 = Iinductor Core
500 ns/div
VI = 3.8 V, TA = 25°C
VO Main = 3.3 V RL Main = 500 mA,
VO Core = 1.6 V, RL Core = 400 mA
Figure 20.
100 mA/div
CH1 = VO Main
20 mV/div
CH3 = Iinductor Main
20 mV/div
Figure 16.
200 mA/div
50 mV/div
100 µs/div
CH4 = IO
100 mV/div
200 mV/div
CH2 = VO
VI = 3.8 V, VI LDO = 3.3 V,
VO = 2.8 V, IL = 2 mA to 180 mA,
TA = 25°C
CH2 =VO
100 mV/div
500 mA/div
VI = 3.8 V, VO = 3.3 V,
IL = 100 mA to 1000 mA,
TA = 25°C
CH4 = IO
200 mA/div
Figure 13.
CH4 = IO
50 mV/div
CH4 = IO
CH2 = VO
10 mV/div
500 mV/div
CH1 = VI
VI = 3.8 V, VO = 1.6 V,
IL = 40 mA to 400 mA,
TA = 25°C
500 mA/div
VI = 3.3 to 3.8 V, VO = 1.8 V,
RL = 100 mA to 1000 mA,
TA = 25°C
VI = 3.3 to 3.8 V, VO = 2.8 V,
IL = 100 mA, TA = 25°C
LINE TRANSIENT RESPONSE
(CORE)
100 mV/div
LINE TRANSIENT RESPONSE
(LDO2)
500 mV/div
LINE TRANSIENT RESPONSE
(LDO1)
500 µs/div
VI = 3.8 V, VO Main = 3.3 V,
RL Main = 1 A, VO Core = 1.6 V,
RL Core = 400 mA, TA = 25°C
Figure 21.
15
TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
0.25
0.045
70
LDO2 VO = 1.8 V
LDO2 VO = 3 V
0.15
0.1
LDO1 VO = 2.8 V
Dropout Voltage - V
0.04
LDO2 VO = 1.8 V
60
0.03
LDO1 VO = 2.8 V
LDO Output Current 10 mA
0.025
0.02
50
40
30
LDO1 VO = 2.5 V
0.015
20
0.05
LDOIN = 3.3 V
LDO2 VO = 3 V
0.035
PSRR - dB
0.2
Dropout Voltage - V
80
0.05
LDO1 VO = 2.5 V
LDO Output Current 200 mA
0.01
Normal Mode
TA = 25°C
0
0
20 40 60 80 100 120 140 160 180 200
IO - Output Current - mA
Figure 22.
16
PSRR (LDO1, LDO2)
vs
FREQUENCY
Low Power Mode
TA = 25°C
0.005
0
0
3
6
9 12 15 18 21 24 27 30
IO - Output Current - mA
Figure 23.
10
0
1k
10k
100k
f - Frequency - Hz
Figure 24.
1M
10M
TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
APPLICATION INFORMATION
AC Adapter
AC
BATT+
1 µF
X5R
VBAT
USB port
1 µF
X5R
0.1 µF
BATT−
USB
TPS65010
ISET
TS
TEMP
PG
GND
PS_SEQ
GND
DEFCORE
VBAT
DEFMAIN
VBAT
CHARGER
POWER GOOD
LED2
VCC
10 R
1 µF
X5R
BATT_COVER
VINCORE
VCORE 1.5 V
L2
VBAT
PB_ONOFF
GND
HOT_RESET
10 µH
22 µF
X5R
10 µF
X5R
VCORE
VINMAIN
VMAIN 3.3 V
LOW_PWR
VBAT
L1
6.2 µH
22 µF
X5R
VMAIN
CHARGER/REG INTERRUPT
GPIO1
INT
GPIO2
nPOR
GPIO3
RESPWRON
GPIO4
MPU_RESET
VBAT
1 µF
X5R
VIB
VMAIN
1 µF
VINLDO1
VMAIN
1 µF
VINLDO2
GND/VCC
PWRFAIL
VLDO2
VLDO1
IFLSB
RESET to MPU
Battery Fail, Battery Cover
Removed, Over Temp.
2.2 µF
X5R
2.2 µF
X5R
VFB_LDO1
SDAT
1M Each
SCL
SDA
SCLK
PGND
AGND
Figure 25. Typical Application Circuit
The VCORE and VMAIN converter are always enabled in a typical application. The VCORE output voltage can
be disabled or reduced from 1.5 V to a lower, preset voltage under processor control. When the processor enters
the sleep mode, a high signal on the LOW_PWR pin initiates the change
VCORE typically supplies the digital part of the audio codec. When the processor is in sleep or low power mode,
the audio codec is powered off, so the VCORE voltage can be programmed to lower voltages without a problem.
A typical audio codec (e.g., TI AIC23) consumes about 20-mA to 30-mA current from the VCORE power supply.
17
TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
APPLICATION INFORMATION (continued)
It is recommended to supply LDO1 from VMAIN as shown in Figure 25. If this is not done, then subsequent to a
UVLO, OVERTEMP, or BATT_COVER = 0 condition, the RESPWRON signal goes high before the VCORE rail
has ramped and stabilized. Therefore, the processor core does not receive a power on reset signal.
AC Adapter
Touchscreen
Controller
AC
BATT+
VBAT
USB port
BATT−
USB
USB DP, Camera i/f
TPS65010
TS
ISET
TEMP
PG
CHARGER
POWER GOOD
GND
PS_SEQ
GND
VBAT
DEFCORE
DEFMAIN
LED2
VCC
OMAP1510
VBAT
BATT_COVER
VBAT
PB_ONOFF
GND
HOT_RESET
VINCORE
VCORE 1.5V
L2
VDD, VDD1,
VDD2, VDD3
VCORE
VINMAIN
LOW_PWR
VBAT
VMAIN 3.3V
VDDSHV2,8
L1
VMAIN
GPIO1
INT
CHARGER/REG INTERRUPT
GPIO
GPIO2
GPIO3
RESPWRON
GPIO4
MPU_RESET
VBAT
VIB
VMAIN
VMAIN
GND/VCC
PWRFAIL
nPOR
RESPWRON
RESET to MPU
MPU_RESET
Battery Fail, Battery Cover
Removed, Overtemp
FIQ_PWRFAIL
VINLDO1
VLDO2
VDDSHV4,5
VLDO1
VDDSHV1,3,6,7,9
VINLDO2
IFLSB
VFB_LDO1
SDAT
SCL
SDA
SCLK
PGND
ARMIO_5/LOW_POWER
AGND
ARMIO,LCD,
Keyboard, USB
Host, SDIO
SDRAM, FLASH i/f
@ 1.8 V/2.8 V
Figure 26. Typical Application Circuit in Low Power Mode
18
TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
DETAILED DESCRIPTION
BATTERY CHARGER
The TPS65010 supports a precision Li-Ion or Li-Polymer charging system suitable for single-cells with either
coke or graphite anodes. Charging the battery is possible even without the application processor being powered
up. The TPS65010 starts charging when an input voltage on either ac or USB input is present, which is greater
than the charger UVLO threshold. See Figure 27 for a typical charge profile.
PreConditioning
Phase
Current Regulation
Phase
Voltage Regulation and Charge
Termination Phase
Regulation Voltage
Regulation Current
Charge Voltage
Minimum Charge
Voltage
Charge Current
Preconditioning
and Taper Detect
t(PRECHG)
t(CHG)
t(TAPER)
Figure 27. Typical Charging Profile
Autonomous Power Source Selection
Per default the TPS65010 attempts to charge from the ac input. If ac input is not present, the USB is selected. If
both inputs are available, the ac input has priority. The charge current is initially limited to 100 mA when charging
from the USB input. This can be increased to 500 mA via the serial interface. The charger can be completely
disabled via the interface, and it is also possible just to disable charging from the USB port. The start of the
charging process from the USB port is delayed in order to allow the application processor time to disable USB
charging, for instance if a USB OTG port is recognized. The recommended input voltage for charging from the ac
input is 4.5 V < VAC < 5.5 V. However, the TPS65010 is capable of withstanding (but not charging from) up to 20
V. Charging is disabled if VAC is greater than typically 6.6 V.
Temperature Qualification
The TPS65010 continuously monitors battery temperature by measuring the voltage between the TS and AGND
pins. An internal current source provides the bias for most common 10K negative-temperature coefficient
thermistors (NTC) (see Figure 28). The IC compares the voltage on the TS pin against the internal V(LTF) and
V(HTF) thresholds to determine if charging is allowed. Once a temperature outside the V(LTF) and V(HTF) thresholds
is detected the IC immediately suspends the charge. The IC suspends charge by turning off the power FET and
holding the timer value (i.e., timers are not reset). Charge is resumed when the temperature returns to the
normal range.
The allowed temperature range for 103AT type thermistor is 0°C to 45°C. However the user may modify these
thresholds by adding two external resistors. See Figure 29.
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TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
DETAILED DESCRIPTION (continued)
bqTINY II
I(TS)
TS
LTF
Pack+
V(LTF)
HTF
+
Pack–
V(HTF)
NTC
TEMP
Battery Pack
Figure 28. TS Pin Configuration
bqTINY II
I(TS)
TS
LTF
Pack+
V(LTF)
HTF
+
Pack–
V(HTF)
RT1 TEMP
RT2
NTC
Battery Pack
Figure 29. TS Pin Threshold
Battery Preconditioning
On power up, if the battery voltage is below the V(LOWV) threshold, the TPS65010 applies a precharge current,
I(PRECHG), to the battery. This feature revives deeply discharged cells. The charge current during this phase is one
tenth of the value in current regulation phase which is set with IO(out) = KSET × V(SET)/R(SET). The load current in
preconditioning phase must be lower than I(PRECHG) and must allow the battery voltage to rise above V(LOWV)
within t(Prechg). VBAT_A is the sense pin to the voltage comparator for the battery voltage. This allows a power on
sense measurement if the VBAT_A and VBAT_B pins are connected together at the battery.
The TPS65010 activates a safety timer, t(PRECHG), during the conditioning phase. If V(LOWV) threshold is not
reached within the timer period, the TPS65010 turns off the charger and indicates the fault condition in the
CHGSTATUS register. In the case of a fault condition, the TPS65010 reduces the current to I(DETECT). I(DETECT)is
used to detect a battery replacement condition. Fault condition is cleared by POR or battery replacement or via
the serial interface.
Battery Charge Current
TPS65010 offers on-chip current regulation. When charging from an ac adapter, a resistor connected between
the ISET1 and AGND pins determines the charge rate. A maximum of 1-A charger current from the ac adapter is
allowed. When charging from a USB port either a 100-mA or 500-mA charge rate can be selected via the serial
interface, default is 100 mA max. Two bits are available in the CHGCONFIG register in the serial interface to
reduce the charge current in 25% steps. These only influence charging from the ac input and may be of use if
charging is often suspended due to excessive junction temperature in the TPS65010 (e.g., at high ac input
voltages) and low battery voltages.
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TPS65010
www.ti.com
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DETAILED DESCRIPTION (continued)
Battery Voltage Regulation
The voltage regulation feedback is through the VBAT pin. This pin is tied directly to the positive side of the
battery pack. The TPS65010 monitors the battery-pack voltage between the VBAT and AGND pins. The
TPS65010 is offered in a fixed-voltage version of 4.2 V.
As a safety backup, the TPS65010 also monitors the charge time in the fast-charge mode. If taper current is not
detected within this time period, t(CHG), the TPS65010 turns off the charger and indicates FAULT in the
CHGSTATUS register. In the case of a FAULT condition, the TPS65010 reduces the current to I(DETECT). I(DETECT)
is used to detect a battery replacement condition. Fault condition is cleared by POR via the serial interface. Note
that the safety timer is reset if the TPS65010 is forced out of the voltage regulation mode. The fast-charge timer
is disabled by default to allow charging during normal operation of the end equipment. It is enabled via the
CHGCONFIG register.
Charge Termination and Recharge
The TPS65010 monitors the charging current during the voltage regulation phase. Once the taper threshold,
I(TAPER), is detected the TPS65010 initiates the taper timer, t(TAPER). Charge is terminated after the timer expires.
The TPS65010 resets the taper timer in the event that the charge current returns above the taper threshold,
I(TAPER). After a charge termination, the TPS65010 restarts the charge once the voltage on the VBAT pin falls
below the V(RCH) threshold. This feature keeps the battery at full capacity at all times. The fast charge timer and
the taper timer must be enabled by programming CHGCONFIG(5)=1. A thermal suspend will suspend the fast
charge and taper timers.
In addition to the taper current detection, the TPS65010 terminates charge in the event that the charge current
falls below the I(TERM) threshold. This feature allows for quick recognition of a battery removal condition. When a
full battery is replaced with an empty battery, the TPS65010 detects that the VBAT voltage is below the recharge
threshold and starts charging the new battery. The taper and termination bits are cleared in the CHGSTATUS
register and if the INT pin is still active due to these two interrupt sources, then it is de-asserted. Depending on
the transient seen at the VCC pin, all registers may be set to their default values and require reprogramming with
any nondefault values required, such as enabling the fast charge timer and taper termination; this should only
happen if VCC drops below approximately 2 V.
Sleep Mode
The TPS65010 charger enters the low-power sleep mode if both input sources are removed from the circuit. This
feature prevents draining the battery during the absence of input power.
PG Output
The open-drain power good (PG) output indicates when a valid power supply is present for the charger. This can
be either from the ac adapter input or from the USB. The output turns ON when a valid voltage is detected. A
valid voltage is detected whenever the voltage on either pin AC or pin USB rises above the voltage on VBAT
plus 100 mV. This output is turned off in the sleep mode. The PG pin can be used to drive an LED or
communicate to the host processor. A voltage greater than the V(CHGOVLO) threshold (typ 6.6 V) at the AC input is
not valid and does not activate the PG output. The PG output is held in high impedance state if the charger is in
reset by programming CHGCONFIG(6)=1.
The PG output can also be programmed via the LED1_ON and LED1_PER registers in the serial interface. It can
then be programmed to be permanently on, off, or to blink with defined on- and period-times. PG is controlled per
default via the charger.
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TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
DETAILED DESCRIPTION (continued)
Thermal Considerations for Setting Charge Current
The TPS65010 is housed in a 48-pin QFN package with exposed leadframe on the underside. This 7 mm × 7
mm package exhibits a thermal impedance (junction-to-ambient) of 33 K/W when mounted on a JEDEC high-k
board with zero air flow.
AMBIENT TEMPERATURE
MAX POWER DISSIPATION FOR Tj= 125°C
DERATING FACTOR ABOVE TA = 55°C
25°C
3W
30 mW/°C
55°C
2.1 W
Consideration needs to be given to the maximum charge current when the assembled application board exhibits
a thermal impedance, which differs significantly from the JEDEC high-k board. The charger has a thermal
shutdown feature, which suspends charging if the TPS65010 junction temperature rises above a threshold of
145°C. This threshold is set 15°C below the threshold used to power down the TPS65010 completely.
STEP-DOWN CONVERTERS, VMAIN AND VCORE
The TPS65010 incorporates two synchronous step-down converters operating typically at 1.25 MHz fixed
frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents the
converters automatically enter power save mode and operate with pulse frequency modulation (PFM). The main
converter is capable of delivering 1-A output current and the core converter is capable of delivering 400 mA.
The converter output voltages are programmed via the VDCDC1 and VDCDC2 registers in the serial interface.
The main converter defaults to 3.0-V or 3.3-V output voltage depending on the DEFMAIN configuration pin, if
DEFMAIN is tied to ground the default is 3.0 V, if it is tied to VCCthe default is 3.3 V. The core converter defaults
to either 1.5 V or 1.6 V depending on whether the DEFCORE configuration pin is tied to GND or to VCC
respectively. Both the main and core output voltages can subsequently be reprogrammed after start-up via the
serial interface. In addition, the LOW_PWR pin can be used either to lower the core voltage to a value defined in
the VDCDC2 register when the application processor is in deep sleep mode or to disable the core converter. An
active signal at LOW_PWR is ignored if the ENABLE_LP bit is not set in the VDCDC1 register.
The step-down converter outputs (when enabled) are monitored by power good comparators, the outputs of
which are available via the serial interface. The outputs of the dc-dc converters can be optionally discharged
when the dc-dc converters are disabled.
During PWM operation the converters use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
The current limit comparator also turns off the switch in case the current limit of the P-channel switch is
exceeded. After the dead time preventing current shoot through, the N-channel MOSFET rectifier is turned on
and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off the
N-channel rectifier and turning on the P-channel switch.
The error amplifier, together with the input voltage, determines the rise time of the saw tooth generator, and
therefore, any change in input voltage or output voltage directly controls the duty cycle of the converter giving a
very good line and load transient regulation.
The two dc-dc converters operate synchronized to each other, with the MAIN converter as the master. A 270°
phase shift between the MAIN switch turn on and the CORE switch turn on decreases the input RMS current and
smaller input capacitors can be used. This is optimized for a typical application where the MAIN converter
regulates a Li-Ion battery voltage of 3.7 V to 3.3 V and the CORE from 3.7 V to 1.5 V
Power Save Mode Operation
As the load current decreases, the converter enters the power save mode operation. During power save mode
the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to
maintain high efficiency.
In order to optimize the converter efficiency at light load the average current is monitored and if in PWM mode
the inductor current remains below a certain threshold, then power save mode is entered. The typical threshold
can be calculated as follows:
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TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
V
I
(skipmain)
I(MAIN)
17 V
I
(skipcore)
I(CORE)
42 (1)
During the power save mode the output voltage is monitored with the comparator by the thresholds comp low
and comp high. As the output voltage falls below the comp low threshold, set to typically 0.8% above the nominal
Vout, the P-channel switch turns on. The converter then runs at 50% of the nominal switching frequency. If the
load is below the delivered current then the output voltage rises until the comp high threshold is reached,
typically 1.6% above the nominal Vout, whereupon all switching activity ceases, hence reducing the quiescent
current to a minimum until the output voltage has dropped below comp low again. If the load current is greater
than the delivered current, then the output voltage falls until it crosses the nominal output voltage threshold
(comp low 2 threshold), whereupon power save mode is exited and the converter returns to PWM mode.
These control methods reduce the quiescent current to typically to 12-µA per converter and the switching
frequency to a minimum achieving the highest converter efficiency. Setting the comparator thresholds to typically
0.8% and 1.6% above the nominal output voltage at light load current results in a dynamic voltage positioning
achieving lower absolute voltage drops during heavy load transient changes. This allows the converters to
operate with a small output capacitor of just 10 µF for the core and 22 µF for the main output and still have a low
absolute voltage drop during heavy load transient changes. Refer to Figure 30 for detailed operation of the power
save mode. The power save mode can be disabled through the I2C interface to force the converters to stay in
fixed frequency PWM mode.
PFM Mode at Light Load
1.6%
Comp High
0.8%
Comp Low
VO
Comp Low 2
PFM Mode at Medium to Full Load
Figure 30. Power Save Mode Thresholds and Dynamic Voltage Positioning
Forced PWM
The core and main converters are forced into PWM mode by setting bit 7 in the VDCDC1 register. This feature is
used to minimize ripple on the output voltages.
Dynamic Voltage Positioning
As described in the power save mode operation sections and as detailed in Figure 13, the output voltage is
typically 1.2% above the nominal output voltage at light load currents as the device is in power save mode. This
gives additional headroom for the voltage drop during a load transient from light load to full load. During a load
transient from full load to light load the voltage overshoot is also minimized due to active regulation turning on the
N-channel rectifier switch.
Soft Start
Both converters have an internal soft start circuit that limits the inrush current during start-up. The soft start is
implemented as a digital circuit increasing the switch current in 4 steps up to the typical maximum switch current
limit of 700 mA (core) and 1.75 A (main). Therefore, the start-up time mainly depends on the output capacitor
and load current.
23
TPS65010
SLVS149A – JUNE 2003 – REVISED JANUARY 2004
www.ti.com
100% Duty Cycle Low Dropout Operation
The TPS65010 converters offer a low input to output voltage difference while maintaining operation with the use
of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly
useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole
battery voltage range. i.e., The minimum input voltage to maintain regulation depends on the load current and
output voltage and is calculated as:
V
I(min)
V
O(max)
I
O(max)
DS(on) max RL
r
(2)
with:
• IO(max) = maximum output current plus inductor ripple current
• rDS(on)max= maximum P-channel switch rDSon.
• RL = DC resistance of the inductor
• VO(max)= nominal output voltage plus maximum output voltage tolerance
Active Discharge When Disabled
When the CORE and MAIN converters are disabled, due to an UVLO, BATT_COVER or OVERTEMP condition,
it is possible to actively pull down the outputs. This feature is disabled per default and is individually enabled via
the VDCDC1 and VDCDC2 registers in the serial interface. When this feature is enabled, the core and main
outputs are discharged by a 400-Ω (typical) load.
Power Good Monitoring
Both the MAIN and CORE converters have power good comparators. Each comparator indicates when the
relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these
comparators are available in the REGSTATUS register via the serial interface. A maskable interrupt is generated
when any voltage rail drops below the 10% threshold. The comparators are disabled when the converters are
disabled.
Overtemperature Shutdown
The MAIN and CORE converters are automatically shut down if the temperature exceeds the trip point (see the
electrical characteristics). This detection is only active if the converters are in PWM mode, either by setting
FPWM = 1, or if the output current is high enough that the device runs in PWM mode automatically.
LOW-DROPOUT VOLTAGE REGULATORS
The low-dropout voltage regulators are designed to operate with low value ceramic input and output capacitors.
They operate with input voltages down to 1.8 V. The LDOs offer a maximum dropout voltage of 300 mV at rated
output current. Each LDO sports a current limit feature. Both LDOs are enabled per default, both LDOs can be
disabled or programmed via the serial interface using the VREGS1 register. The LDO outputs (when enabled)
are monitored by power good comparators, the outputs of which are available via the serial interface. The LDOs
also have reverse conduction prevention when disabled. This allows the possibility to connect external regulators
in parallel in systems with a backup battery.
Power Good Monitoring
Both the LDO1 and LDO2 linear regulators have power good comparators. Each comparator indicates when the
relevant output voltage has dropped 10% below it's target value, with 5% hysteresis. The outputs of these
comparators are available in the REGSTATUS register via the serial interface. An interrupt is generated when
any voltage rail drops below the 10% threshold. The LDO2 comparator is disabled when LDO2 is disabled. The
LDO1 power good comparator is always active since it generates the system reset signal, RESPWRON, see the
System Reset and Control Signal Section below. This also allows the possibility to monitor VLDO1, even if it is
provided by an external regulator.
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TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
Enable and Sequencing
Enabling and sequencing of the dc-dc converters and LDOs is described in the power-up sequencing section.
The OMAP1510 processor from Texas Instruments requires that the core power supply is enabled before the I/O
power supply, which means that the CORE converter should power up before the MAIN converter. This is
achieved by connecting PS_SEQ to GND.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit for the four regulators on TPS65010 prevents the device from malfunctioning at
low input voltages and from excessive discharge of the battery. Basically it prevents the converter from turning
on the power switch or rectifier FET under undefined conditions. The undervoltage threshold voltage is set by
default to 3.25 V. After power-up, the threshold voltage can be reprogrammed through the serial interface. The
undervoltage lockout comparator compares the voltage on the VCC pin with the UVLO threshold. When the VCC
voltage drops below this threshold, the TPS65010 sets the PWRFAIL pin low and after a time t(UVLO) disables the
voltage regulators in the sequence defined by PS_SEQ. The same procedure is followed when the TPS65010
detects that its junction temperature has exceeded the overtemperature threshold, typically 160°C, with a delay
t(overtemp). The TPS65010 automatically restarts when the UVLO (or overtemperature) condition is no longer
present.
The battery charger circuit has a separate UVLO circuit with a threshold of typically 2.5 V, which is compared
with the voltage on AC and USB supply pins.
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TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
POWER-UP SEQUENCING
The TPS65010 power-up sequencing is designed to allow the maximum flexibility without generating excessive
logistical or system complexity. The relevant control pins are described in the following table:
Table 1. Control Pins
INPUT/OUTPUT
FUNCTION
PS_SEQ
PIN NAME
I
Input signal indicating power up and down sequence of the switching converters. PS_SEQ = 0 forces the
core regulator to ramp up first and down last. PS_SEQ = 1 forces the main regulator to ramp up first and
down last.
DEFCORE
I
Defines the default voltage of the VCORE switching converter. DEFCORE = 0 defaults VCORE to 1.5 V,
DEFCORE = VCC defaults VCORE to 1.6 V.
DEFMAIN
I
Defines the default voltage of the VMAIN switching converter. DEFMAIN = 0 defaults VMAIN to 3.0 V,
DEFMAIN = VCC defaults VMAIN to 3.3 V.
LOW_PWR
I
The LOW_PWR pin is used to lower VCORE to the preset voltage in the VDCDC2 register when the
processor is in deep sleep mode. Alternatively VCORE can be disabled in low power mode if the
LP_COREOFF bit is set in the VDCDC2 register. LOW_PWR is ignored if the ENABLE LP bit is not set
in the VDCDC1 register. The TPS65010 uses the rising edge of the internal signal formed by a logical
AND of LOW_PWR and ENABLE LP to enter low power mode. TPS65010 is forced out of low power
mode by de-asserting LOW_PWR, by resetting ENABLE LP to 0, by activating the PB_ONOFF pin or by
activating the HOT_RESET pin. There are two ways to get the device back into low power mode: a)
toggle the LOW_PWR pin, or b) toggle the low power bit when the LOW_PWR pin is held high.
PB_ONOFF
I
PB_ONOFF can be used to exit the low power mode and return the core voltage to the value before low
power mode was entered. If PB_ONOFF is used to exit the low power mode, then the low power mode
can be reentered by toggling the LOW_PWR pin or by toggling the low power bit when the LOW_PWR
pin is held high. A 1-MΩ pulldown resistor is integrated in TPS65010. PB_ONOFF is internally
de-bounced by the TPS65010. A maskable interrupt is generated when PB_ONOFF is activated.
HOT_RESET
I
The HOT_RESET pin has a very similar functionality to the PB_ONOFF pin. In addition it generates a
reset (MPU_RESET) for the MPU when the VCORE voltage is in regulation. HOT_RESET does not alter
any TPS65010 settings unless low power mode was active in which case it is exited. A 1-MΩ pullup
resistor to VCC is integrated in TPS65010. HOT_RESET is internally de-bounced by the TPS65010.
BATT_COVER
I
The BATT_COVER pin is used as an early warning that the main battery is about to be removed.
BATT_COVER = VCC indicates that the cover is in place, BATT_COVER = 0 indicates that the cover is
not in place. TPS65010 generates a maskable interrupt when the BATT_COVER pin goes low. PWRFAIL
is also held low when BATT_COVER goes low. This feature may be disabled, by tying BATT_COVER
permanently to VCC. The TPS65010 shuts down the main and the core converters, and sets the LDOs
into low power mode. A 2-MΩ pulldown resistor is integrated in the TPS65010 at the BATT_COVER pin.
BATT_COVER is internally de-bounced by the TPS65010.
RESPWRON
O
RESPWRON is held low while the switching converters (and any LDO's defined as default on) are
starting up. It is determined by the state of LDO1's output voltage; when this is good then RESPWRON
is high, when VLDO1 is low then RESPWRON is low. RESPWRON is held low for tn(RESPWRON) sec after
VLDO1 has settled.
MPU_RESET
O
MPU_RESET can be used to reset the processor if the user activates theHOT_RESET button. The
MPU_RESET output is active for t(MPU_nRESET) sec. It also forces TPS65010 to leave low power mode.
MPU_RESET is also held low as long as RESPWRON is held low.
PWRFAIL
O
PWRFAIL indicates when VCC < V(UVLO), when the TPS65010 is about to shut down due to an internal
overtemperature condition or when BATT_COVER is low. PWRFAIL is also held low as long as
RESPWRON is held low.
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TPS65010
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
Figure 31 shows the state diagram for the TPS65010 power sequencing. The charger function is not shown in
the state diagram since this function is independent of these states.
Monitored permanently
NO
POWER
Main battery
power applied
(i)
(ii)
Bias circuitry
enabled.
LDOs enabled
0
VCC>UVLO,
Tj<Tshtdwn,
BATT_COVER
high ?
Yes
Reset
PWRFAIL
timer
No
Set PWRFAIL low
Start PWRFAIL
timer if not running
Value
PS_SEQ ?
1
Boot VCORE
converter
Boot VMAIN
converter
Boot VMAIN
converter
Boot VCORE
converter
PWRFAIL
timer done ?
**Converter
Sequencing
No
Yes
Shut down VCORE, VMAIN. Set
RESPWRON, INT, MPU_RESET
low, Reset RESPWRON timer
SHUT
DOWN
LOW_PWR
de−asserted,
PB_ONOFF
button pressed
LOW
POWER
MODE
LOW_PWR
asserted *
ON
VCC>UVLO,
Tj<Tshtdwn,
BATT_COVER
high ?
HOT_RESET
button pressed
No
Yes
Reset PWRFAIL timer
Start RESPWRON
timer if not running
No
VCORE
voltage good ?
RESPWRON
timer done ?
Yes
Release
MPU_RESET
Set MPU_RESET
low, start
MPU_RESET time
No
Yes
Converter
Sequencing **
No
Return to previous
state: ON or
LOW POWER
MPU_RESET
timer done ?
Yes
Monitored permanently
* ENABLE_LP bit must be set;
see Power States Description
Routine (i) shows the behavior under normal operating
conditions when no errors such as low VCC voltage or high
junction temperature are present.
Routine (ii) shows the behavior when either the VCC voltage
drops too low, the TPS65010 junction temperature rises too
high or if the BATT_COVER input pin goes low.
Routine (iii) shows the power on reset routine, which is
triggered when the LDO1 output voltage drops 10% below its
nominal target voltage.
Routines (ii) & (iii) go into effect as soon as their trigger
conditions apply, hence they can interrupt routine (i) at any
point. Routine (ii) has priority over routine (iii) with regard to
control of /RESPWRON and the /RESPWRON timer.
(iii)
LDO1 voltage
good ?
Yes
No
TPS65010 holds
RESPWRON,
PWRFAIL, INT
MPU_RESET low
Reset
RESPWRON timer
Start RESPWRON
timer if not running
RESPWRON
timer done ?
No
Yes
Release
RESPWRON,
PWRFAIL, INT
MPU_RESET.
Figure 31. TPS65010 Power-On State Diagram
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TPS65010 Power States Description
State 1: No Power
There are no batteries connected to the TPS65010. When main power is applied, the bandgap reference, LDOs,
and UVLO comparator start up. The RESPWRON, PWRFAIL, INT and MPU_RESET signals are held low. When
BATT_COVER goes high (de-bounced internally by the TPS65010), indicating that the battery cover has been
put in place and if VCC > UVLO, the power supplies are ramped in the sequence defined by PS_SEQ.
RESPWRON, PWRFAIL, INT and MPU_RESET are released when the RESPWRON timer has timed out after
tn(RESPWRON) sec. If VCC remains valid and no OVERTEMP condition occurs then the TPS65010 arrives in State
2: ON. If VCC < UVLO the TPS65010 keeps the bandgap reference and UVLO comparator active such that
when VCC>UVLO (during battery charge) the supplies are automatically activated.
State 2: ON
In this state, TPS65010 is fired up and ready to go. The switching converters can have their output voltages
programmed, the LDOs can be disabled or programmed. TPS65010 can exit this state either due to an
overtemperature condition, by an undervoltage condition at VCC, by BATT_COVER going low, or by the
processor programming low power mode. State 2 is left temporarily if the user activates the HOT_RESET pin.
State 3: Low Power Mode
This state is entered via the processor setting the ENABLE_LP bit in the serial interface and then raising the
LOW_PWR pin. The TPS65010 actually uses the rising edge of the internal signal formed by a logical AND of
the LOW_PWR and ENABLE LP signals to enter low power mode. The VMAIN switching converter remains
active, but the VCORE converter may be disabled in low power mode via the serial interface by setting the
LP_COREOFF bit in the VDCDC2 register. If left enabled, the VCORE voltage is set to the value predefined by
the CORELP0/1 bits in the VDCDC2 register. The LDO1OFF/nSLP and LDO2OFF/nSLP bits in the VREGS1
register determine whether the LDOs are turned off or put in a reduced power mode (transient speed-up circuitry
disabled in order to minimize quiescent current) in low power mode. All TPS65010 features remain addressable
via the serial interface. TPS65010 can exit this state either due to an undervoltage condition at VCC, due to
BATT_COVER going low, due to an OVERTEMP condition, by the processor deasserting the LOW_POWER pin
or by the user activating the HOT_RESET pin or the PB_ONOFF pin.
State 4: Shutdown
This state is entered automatically when either the VCC voltage is below UVLO the threshold, or if the TPS65010
junction temperature is too high, or if the BATT_COVER pins goes low. The shutdown state is left when the error
condition no longer applies.
Table 2 indicates the typical quiescent current consumption in each power state.
Table 2. TPS65010 Typical Current Consumption
STATE
28
TOTAL QUIESCENT
CURRENT
QUIESCENT CURRENT BREAKDOWN
1
0
2
30 µA-70 µA
VMAIN (12 µA) + VCORE (12 µA) + LDOs (20 µA each, max 2) + UVLO + reference + PowerGood
3
30 µA-55 µA
VMAIN (12 µA) + VCORE (12 µA) + LDOs (10 µA each, max 2) + UVLO + reference + PowerGood
4
13 µA
UVLO + reference circuitry
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VCC
REFSYS
EN
UVLO
BATT COVER
ENABLE
SUPPLIES
VCORE
t(GLITCH)
98%
VCORE
VMAIN
VLDO1
95%
VLDO1
VLDO2
RESPWRON
MPU_RESET
PWRFAIL INT
tn(NRESPWRON)
Figure 32. State 1 to State 2 Transition (PS_SEQ=0, VCC > VUVLO + HYST)
Valid for LDO1 supplied from VMAIN as described earlier in this Application Section.
If 2.4 ms after application, VCC is still below the default UVLO threshold (3.425 V for VCC rising), then start up is
as shown in Figure 33.
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UVLO threshold
VCC
REFSYS
EN
BATT COVER
t GLITCH
UVLO
ENABLE
SUPPLIES
VCORE
t NRESPWRON
98%
VCORE
VMAIN
VLDO1
95%
VLDO1
VLDO2
RESPWRON
MPU_RESET
PWRFAIL/INT
t NRESPWRON
Figure 33. State1-State4-State 2 Transition (Power up behavior when VCC ramp is longer than 2.4 ms)
Valid for LDO1 supplied from VMAIN as described earlier in this Application Section.
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VCC
UVLO Threshold With 175-mV Hysteresis
UVLO
PWRFAIL
INT
ENABLE
SUPPLIES
t UVLO
t NRESPWRON
98%
VCORE
VCORE
VMAIN
VMAIN
~0.8V
95%
VLDO1
VLDO1
VLDO2
RESPWRON
MPU_RESET
t NRESPWRON
Figure 34. State2-State4-State 2 Transition
Valid for LDO1 supplied from VMAIN as described earlier in this Application Section.
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ENABLE
LOW_POWER
LDO2
OSS/SLP
LOW_POWER
VMAIN
VCORE
95% VCORE
VLDO1
VLDO2
95% VLDO2
INT
Figure 35. State 2 to State 3 Transition. VCORE Lowered, LDO2 Disabled. Subsequent State 3 to State 2
Transition When LOW POWER Is Deasserted.
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PB_ONOFF
PB_ONOFF
DEGLITCH
tGLITCH
VCORE
VMAIN
VLDO1
VLDO2
INT
Figure 36. State 3 to State 2 Transition. PB_ONFF Activated (See Interrupt Management Section for INT
Behavior)
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HOT_RESET
HOT_RESET
DEGLITCH
tGLITCH
VCORE
95% VCORE
VMAIN
VLDO1
VLDO2
95% VLDO2
INT
MPU_RESET
t(MPU_RESET)
Figure 37. State 3 to State 2 Transition (HOT_RESET Activated, See Interrupt Management Section for INT
Behavior)
SYSTEM RESET AND CONTROL SIGNALS
The RESPWRON signal is used as a global reset for the application. It is an open drain output. The
RESPWRON signal is generated according to the Power Good comparator linked to VLDO1 and remains low for
tn(RESPWRON) sec after VLDO1 has stabilized. When RESPWRON is low, PWRFAIL, MPU_RESET and INT are
also held low.
If the output voltage of LDO1 is less than 90% of its nominal value, as RESPWRON is generated, and if the
output voltage of LDO1 is programmed to a higher value, which causes the output voltage to fall out of the 90%
window, then a RESPWRON signal is generated.
The PWRFAIL signal indicates when VCC < UVLO or when the TPS65010 junction temperature has exceeded a
reliable value or if BATT_COVER is taken low. This open drain output can be connected at a fast interrupt pin for
immediate attention by the application processor. All supplies are disabled t(uvlo), t(overtemp) or t(batt_cover) sec after
PWRFAIL has gone low, giving time for the application processor to shutdown cleanly.
BATT_COVER is used to detect whether the battery cover is in place or not. If the battery cover is removed, the
TPS65010 generates a warning to the processor that the battery is likely to be removed and that it may be
prudent to shut down the system. If not required, this feature may be disabled by connecting the BATT_COVER
pin to the VCC pin. BATT_COVER is de-bounced internally. Typical de-bounce time is 56 ms. BATT_COVER
has an internal 2-MΩ pull down.
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The HOT_RESET input is used to generate an MPU_RESET signal for the application processor.
TheHOT_RESET pin could be connected to a user-activated button in the application. It can also be used to exit
low power mode, in this case the TPS65010 waits until the VCORE voltage has stabilized before generating the
MPU_RESET pulse. The MPU_RESET pulse is active low for t(mpu_nreset) sec. HOT_RESET has an internal 1-MΩ
pull up to VCC.
The PB_ONOFF input can be used to exit LOW POWER MODE. It is typically driven by a user-activated
push-button in the application. Both HOT_RESET and PB_ONOFF are de-bounced internally by the TPS65010.
Typical de-bounce time is 56 ms. PB_ONOFF has an internal 1-MΩ pull down.
PB_ONOFF, BATT_COVER and UVLO events also cause a normal, maskable interrupt to be generated and are
noted in the REGSTATUS register.
VIBRATOR DRIVER
The VIB open drain output is provided to drive a vibrator motor, controlled via the serial interface register
VDCDC2. It has a maximum dropout of 0.5 V at 100-mA load. Typically an external resistor is required to limit
the motor current, and a freewheel diode to limit the VIB overshoot voltage at turnoff.
LED2 OUTPUT
The LED2 output can be programmed in the same way as the PG output to blink or to be permanently on or off.
The LED2_ON and LED2_PER registers are used to control the blink rate. For both PG and LED2, the minimum
blink on time is 10 ms and this can be increased in 127 10 ms-steps to 1280 ms. For both PG and LED2, the
minimum blink period is 100 ms and this can be increased in 127 100-ms steps to 12800 ms.
INTERRUPT MANAGEMENT
The open drain INT pin is used to combine and report all possible conditions via a single pin. Battery and chip
temperature faults, precharge timeout, charge timeout, taper timeout and termination current are each capable of
setting INT low, i.e. active. INT can also be activated if any of the regulators are below the regulation threshold.
Interrupts can also be generated by any of the GPIO pins programmed to be inputs. These inputs can be
programmed to generate an interrupt either at the rising or falling edge of the input signal. It is possible to mask
an interrupt from any of these conditions individually by setting the appropriate bits in the MASK1, MASK2 or
MASK3 registers. By default, all interrupts are masked. Interrupts are stored in the CHGSTATUS, REGSTATUS
and DEFGPIO registers in the serial interface. CHGSTATUS and REGSTATUS interrupts are acknowledged by
reading these registers. If a 1 is present in any location then the TPS65010 automatically sets the corresponding
bit in the ACKINT1 or ACKINT2 registers and releases the INT pin. The ACKINT register contents are
self-clearing when the condition, which caused the interrupt, is removed. The applications processor should not
normally need to access the ACKINT1 or ACKINT2 registers.
Interrupt events are always captured; thus when an interrupt source is unmasked, INT may immediately go active
due to a previous interrupt condition. This can be prevented by first reading the relevant STATUS register before
unmasking the interrupt source.
If an interrupt condition occurs then the INT pin is set low. The CHGSTATUS, REGSTATUS and DEFGPIO
registers should be read. Bit positions containing a 1 (or possibly a 0 in DEFGPIO) are noted by the CPU and the
corresponding situation resolved. The reading of the CHGSTATUS and REGSTATUS registers automatically
acknowledges any interrupt condition in those registers and blocks the path to the INT pin from the relevant
bit(s). No interrupt should be missed during the read process since this process starts by latching the contents of
the register before shifting them out at SDAT. Once the contents have been latched (takes a couple of
nanoseconds), the register is free to capture new interrupt conditions. Hence the probability of missing anything
is, for practical purposes, zero.
The following describes how registers 0x01 (CHGSTATUS) and 0x02 (REGSTATUS) are handled:
• CHGSTATUS(5,0) are positive edge set. Read of set CHGSTATUS(5,0) bits sets ACKINT1(5,0) bits.
• CHGSTATUS(7-6,4-1) are level set. Read of set CHGSTATUS(7-6,4-1) bits sets ACKINT1(7-6,4-1) bits.
• CHGSTATUS(5,0) clear when input signal low and ACKINT1(5,0) bits are already set.
• CHGSTATUS(7-6,4-1) clear when input signal is low.
• ACKINT1(7-0) clear when CHGSTATUS(7-0) is clear.
• REGSTATUS(7-5) are positive edge set. Read of set REGSTATUS(7-5) bits sets ACKINT2(7-5) bits.
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•
•
•
•
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REGSTATUS(3-0) are level set. Read of set REGSTATUS(3-0) bits sets ACKINT2(3-0) bits.
REGSTATUS(7-5) clear when input signal low and ACKINT1(7-5) bit are already set.
REGSTATUS(3-0) clear when input signal is low.
ACKINT2(7-0) clear when REGSTATUS(7-0) is clear.
The following describes the function of the 0x05 (ACKINT1) and 0x06 (ACKINT2) registers. These are not
usually written to by the CPU since the TPS65010 internally sets/clears these registers:
• ACKINT1(7:0) - Bit is set when the corresponding CHGSTATUS set bit is read via I2C.
• ACKINT1(7:0) - Bit is cleared when the corresponding CHGSTATUS set bit clears.
• ACKINT2(7:0) - Bit is set when the corresponding REGSTATUS set bit is read via I2C.
• ACKINT2(7:0) - Bit is cleared when the corresponding REGSTATUS set bit clears.
• ACKINT1(7:0) - a bit set masks the corresponding CHGSTATUS bit from INT.
• ACKINT2(7:0) - a bit set masks the corresponding REGSTATUS bit from INT.
The following describes the function of the 0x03 (MASK1), 0x04 (MASK2) and 0x0F (MASK3) registers:
• MASK1(7:0) - a bit set in this register masks CHGSTATUS from INT.
• MASK2(7:0) - a bit set in this register masks REGSTATUS from INT.
• MASK3(7:4) - a bit set in this register detects a rising edge on GPIO.
• MASK3(7:4) - a bit cleared in this register detects a falling edge on GPIO.
• MASK3(3:0) - a bit set in this register clears GPIO Detect signal from INT.
GPIO interrupts are located by reading the 0x10 (DEFGPIO) register. The application CPU stores, or can read
from DEFGPIO<7:4>, which GPIO is set to input or output. This information together with the information on
which edge the interrupt was generated (the CPU either knows this or can read it from MASK3<7:4>) determines
whether the CPU is looking for a 0 or a 1 in DEFGPIO<3:0>. A GPIO interrupt is blocked from the INT pin by
setting the relevant MASK3<3:0> bit; this must be done by the CPU, there is no auto-acknowledge for the GPIO
interrupts.
SERIAL INTERFACE
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements and charger status to be monitored.
Register contents remain intact as long as VCC remains above 2 V. The TPS65010 has a 7-bit address with the
LSB set by the IFLSB pin, this allows the connection of two devices with the same address to the same bus. The
6 MSBs are 100100. Attempting to read data from register addresses not listed in this section results in FFh
being read out.
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS65010 device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS65010 device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of
data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this
case, the slave TPS65010 device must leave the data line high to enable the master to generate the stop
condition.
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DATA
CLK
Change
of Data
Allowed
Data Line
Stable
Data Valid
Figure 38. Bit Transfer on the Serial Interface
CE
DATA
CLK
S
P
START Condition
STOP Condition
Figure 39. START and STOP Conditions
...
SCLK
A6
SDAT
A5
A4
...
...
A0
R/W
ACK
0
R7
R6
... R0
R5
0
ACK
D7
D6
... D0
D5
0
Slave Address
Start
...
ACK
0
Register Address
Data
Stop
#IMPLIED. NOTE: SLAVE = TPS65010
Figure 40. Serial Interface WRITE to TPS65010 Device
...
SCLK
A6
SDAT
Start
..
...
A0
R/W
ACK
0
0
R7
Slave Address
..
...
R0
Register
Address
ACK
0
A6
..
A0
...
R/W
ACK
1
0
Slave Address
D7
..
D0
Slave
Drives
The Data
ACK
Master
Stop
Drives
ACK and Stop
#IMPLIED. NOTE: SLAVE = TPS65010
Figure 41. Serial Interface READ From TPS65010: Protocol A
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SLVS149A – JUNE 2003 – REVISED JANUARY 2004
...
SCLK
SDAT
A6
..
...
A0
R/W
ACK
0
0
..
R7
R0
Register
Address
Slave Address
Start
..
...
ACK
A6
0
Stop Start
..
A0
R/W
ACK
0
1
Slave Address
D7
..
D0
Slave
Drives
The Data
ACK
Master
Stop
Drives
ACK and Stop
#IMPLIED. NOTE: SLAVE = TPS65010
Figure 42. Serial Interface READ From TPS65010: Protocol B
DATA
t(BUF)
th(STA)
t(LOW)
tr
tf
CLK
th(STA)
STO
STA
t(HIGH)
th(DATA)
tsu(STA)
tsu(STO)
tsu(DATA)
STA
Figure 43. Serial Interface Timing Diagram
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CHGSTATUS Register (Address: 01h—Default Value: 00h)
CHGSTATUS
B7
B6
B5
B4
B3
B2
B1
B0
Name
USB charge
AC charge
Thermal
Suspend
Term Current
Taper
Timeout
Chg Timeout
Prechg
Timeout
BattTemp
error
Default
0
0
0
0
0
0
0
0
Read/write
R
R
R
R
R/W
R/W
R/W
R
The CHGSTATUS register contents indicate the status of charge.
Bit 7 - USB charge:
• 0 = inactive.
• 1 = USB source is present and in the range valid for charging. B7 remains active as long as the charge
source is present.
Bit 6 - AC charge:
• 0 = wall plug source is not present and/or not in the range valid for charging.
• 1 = wall plug source is present and in the range valid for charging. B6 remains active as long as the charge
source is present.
Bit 5 - Thermal suspend:
• 0 = charging is allowed
• 1 = charging is momentarily suspended due to excessive power dissipation on chip.
Bit 4 - Term current:
• 0 = charging, charge termination current threshold has not been crossed.
• 1 = charge termination current threshold has been crossed and charging has been stopped. It can be due to
a battery reaching full capacity, or it can be due to a battery removal condition.
Bit 3 - 1 Prechg Timeout, Chg Timeout, Taper Timeout:
• 0 = charging
• 1 = one of the timers has timed out and charging has been terminated.
Bit 0 - BattTemp error: Battery temperature error
• 0 = battery temperature is inside the allowed range and that charging is allowed.
• 1 = battery temperature is outside of the allowed range and that charging is suspended.
B1-4 may be reset via the serial interface in order to force a reset of the charger. Any attempt to write to B0 and
B5-7 is ignored. A 1 in B<7:0> sets the INT pin active unless the corresponding bit in the MASK register is set.
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REGSTATUS Register (Address: 02h—Default Value: 00h)
REGSTATUS
B7
B6
B5
B4
B3
B2
B1
B0
PGOOD
LDO2
PGOOD
LDO1
PGOOD
MAIN
PGOOD
CORE
Bit name
PB_ONOFF
BATT_COVER
UVLO
Default
0
0
0
0
0
0
0
0
Read/write
R
R
R
R
R
R
R
R
Bit 7 - PB_ONOFF:
• 0 = inactive
• 1 = user activated the PB_ONOFF switch to request that all rails are shut down.
Bit 6 - BATT_COVER:
• 0 = BATT_COVER pin is high.
• 1 = BATT_COVER pin is low.
Bit 5 - UVLO:
• 0 = voltage at the VCC pin above UVLO threshold.
• 1 = voltage at the VCC pin has dropped below the UVLO threshold.
Bit 4 - not implemented
Bit 3 - PGOOD LDO2:
• 0 = LDO2 output in regulation, or LDO2 disabled with VREGS1<7> = 0
• 1 = LDO2 output out of regulation.
Bit 2 - PGOOD LDO1:
• 0 = LDO1 output in regulation, or LDO1 disabled with VREGS1<3> =0
• 1 = LDO1 output out of regulation.
Bit 1 - PGOOD MAIN:
• 0 = Main converter output in regulation.
• 1 = Main converter output out of regulation.
Bit 0 - PGOOD CORE:
• 0 = Core converter output in regulation.
• 1 = Core converter output out of regulation, or VDCDC2<7> = 1 in low power mode.
A rising edge in the REGSTATUS register contents causes INT to be driven low if it is not masked in the MASK2.
MASK1 Register (Address: 03h—Default Value: FFh)
MASK1
Bit name
B7
Mask USB
B6
B5
Mask AC
Mask Thermal
Suspend
B4
Mask Term
B3
Mask Taper
B2
Mask Chg
B1
B0
Mask Prechg
Mask
BattTemp
Default
1
1
1
1
1
1
1
1
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The MASK1 register is used to mask all or any of the conditions in the corresponding CHGSTATUS<7:0>
positions being indicated at the INT pin. Default is to mask all.
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MASK2 Register (Address: 04h—Default Value: FFh)
MASK2
B7
B6
Bit name
Mask
PB_ONOFF
Mask
BATT_COVER
Mask UVLO
Default
1
1
R/W
R/W
R/W
Read/write
B5
B4
B3
B2
B1
B0
Mask PGOOD
LDO2
Mask PGOOD
LDO1
Mask PGOOD
MAIN
Mask PGOOD CORE
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
The MASK2 register is used to mask all or any of the conditions in the corresponding REGSTATUS<7:0>
positions being indicated at the INT pin. Default is to mask all.
ACKINT1 Register (Address: 05h—Default Value: 00h)
ACKINT1
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
Ack USB
Ack AC
Ack Thermal
Shutdown
Ack Term
Ack Taper
Ack Chg
Ack Prechg
Ack
BattTemp
Default
0
0
0
0
0
0
0
0
Read/write
R
R
R
R
R
R
R
R
The ACKINT1 register is internally used to acknowledge any of the interrupts in the corresponding
CHGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT
pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes
high, else it will remain low. A 1 at any position in ACKINT1 is automatically cleared when the corresponding
interrupt condition in CHGSTATUS is removed. The application processor should not normally need to access
the ACKINT1 register.
ACKINT2 Register (Address: 06h—Default Value: 00h)
ACKINT2
B7
B6
B5
Bit name & function
Ack
PB_ONOFF
Ack BATT_
COVER
Ack UVLO
B4
B3
B2
B1
B0
Ack PGOOD Ack PGOOD Ack PGOOD Ack PGOOD
LDO2
LDO1
MAIN
CORE
Default
0
0
0
0
0
0
0
0
Read/write
R
R
R
R
R
R
R
R
The ACKINT2 register is internally used to acknowledge any of the interrupts in the corresponding
REGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT
pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes
high, else it will remain low. A 1 at any position in ACKINT2 is automatically cleared when the corresponding
interrupt condition in REGSTATUS is removed. The application processor should not normally need to access
the ACKINT2 register.
CHGCONFIG Register Address: 07h—Default Value: 1Bh
CHGCONFIG
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
POR
Charger reset
Fast charge
timer + taper
timer enabled
MSB charge
current
LSB charge
current
USB / 100
mA 500 mA
USB charge
allowed
Charge
enable
Default
0
0
0
1
1
0
1
1
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The CHGCONFIG register is used to configure the charger.
Bit 7 - POR:
• 0 = Tn(RESPWRON) duration typically 1000 ms (+/-25%)
• 1 = Tn(RESPWRON) duration typically 69 ms (+/-25%)
Bit 6 - Charger reset:
• Clears all the timers in the charger and forces a restart of the charge algorithm.
• 0 / 1 = This bit must be set and then reset via the serial interface.
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Bit 5 - Fast charge timer + taper timer enabled:
• 0 = fast charge timer disabled (default)
• 1 = enables the fast charge timer.
Bit 4, Bit 3 - MSB/LSB Charge current:
• Used to set the constant current in the current regulation phase.
B4:B3
CHARGE CURRENT RATE
11
Maximum current set by the external resistor at the ISET pin
10
75% of maximun
01
50% of maximun
00
25% of maximun
Bit 2 - USB 100 mA / 500 mA:
• 0 = sets the USB charging current to max 100 mA.
• 1 = sets the USB charging current to max 500mA. B2 is ignored if B1=0.
Bit 1 - USB charge allowed:
• 0 = prevents any charging from the USB input.
• 1 = charging from the USB input is allowed.
Bit 0 - Charge enable:
• 0 = charging is not allowed.
• 1 = charger is free to charge from either of the two input sources. If both sources are present and valid, the
TPS65010 charges from the ac source.
LED1_ON Register (Address: 08h—Default Value: 00h)
LED1_ON
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
PG1
LED1 ON6
LED1 ON5
LED1 ON4
LED1 ON3
LED1 ON2
LED1 ON1
LED1 ON 0
Default
0
0
0
0
0
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The LED1_ON and LED1_PER registers can be used to take control of the PG open drain output normally
controlled by the charger.
Bit 7 - PG1: Control of the PG pin is determined by PG1 and PG2 according to the table under LED1_PER
register
Bit 6 - BIT 0 - LED1_ON<6:0> are used to program the on-time of the open drain output transistor at the PG pin.
The minimum on time is typically 10 ms and one LSB corresponds to a 10-ms step change in the on time.
LED1_PER Register (Address: 09h—Default Value: 00h)
LED1_PER
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
PG2
LED1 PER6
LED1 PER5
LED1 PER4
LED1 PER3
LED1 PER2
LED1 PER1
LED1 PER 0
Default
0
0
0
0
0
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7 - PG2: Control of the PG pin is determined by PG1 and PG2 according to the following table. Default shown
in bold.
42
PG1
PG2
BEHAVIOR OF PG OPEN DRAIN OUTPUT
0
0
Under charger control
0
1
Blink
1
0
Off
1
1
Always On
TPS65010
www.ti.com
SLVS149A – JUNE 2003 – REVISED JANUARY 2004
Bit 6-Bit 0 - LED1_PER<6:0> are used to program the time period of the open drain output transistor at the PG
pin. The minimum period is typically 100 ms and one LSB corresponds to a 100-ms step change in the period.
LED2_ON Register (Address: 0Ah—Default Value: 00h)
LED2_ON
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
LED21
LED2 ON6
LED2 ON5
LED2 ON4
LED2 ON3
LED2 ON2
LED2 ON1
LED2 ON0
Default
0
0
0
0
0
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The LED2_ON and LED2_PER registers are used to control the LED2 open drain output.
Bit 7 LED22: Control is determined by LED21 and LED22 according to the table under LED2_PER register.
Bit 6-Bit 0 - LED2_ON<6:0> are used to program the on-time of the open drain output transistor at the LED2 pin.
The minimum on time is typically 10 ms and one LSB corresponds to a 10-ms step change in the on time.
LED2_PER (Register Address: 0Bh—Default Value: 00h)
LED2_PER
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
LED22
LED2 PER6
LED2 PER5
LED2 PER4
LED2 PER3
LED2 PER2
LED2 PER1
LED2 PER 0
Default
0
0
0
0
0
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7 LED22: Control is determined by LED21 and LED22 according to the table. Default shown in bold.
Bit 6-Bit 0 - LED2_ON<6:0> are used to program the on-time of the open drain output transistor at the LED2 pin.
The minimum on time is typically 100 ms and one LSB corresponds to a 100-ms step change in the on time.
LED21
LED22
0
0
BEHAVIOR OF LED2 OPEN DRAIN OUTPUT
Off
0
1
Blink
1
0
Off
1
1
Always On
VDCDC1 Register (Address: 0Ch—Default Value: 72h/73h)
VDCDC1
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
FPWM
UVLO1
UVLO0
ENABLE
SUPPLY
ENABLE
LP
MAIN DISCHARGE
MAIN1
MAIN0
Default
0
1
1
1
0
0
1
DEFMAIN
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The VDCDC1 register is used to program the VMAIN switching converter.
Bit 7 - FPWM: forced PWM mode for dc-dc converters.
• 0 = MAIN and the CORE dc-dc converter are allowed to switch into PFM mode.
• 1 = MAIN and the CORE dc-dc converter operate with forced fixed frequency PWM mode and are not
allowed to switch into PFM mode at light load.
Bit 6-Bit 5 - UVLO<1:0>: The under-voltage threshold voltage is set by UVLO1 and UVLO0 according to the
below table, with the default value in bold.
UVLO1
UVLO0
VUVLO
0
0
2.5 V
0
1
2.75 V
1
0
3.0 V
1
1
3.25 V
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TPS65010
www.ti.com
SLVS149A – JUNE 2003 – REVISED JANUARY 2004
Bit 4 - ENABLE SUPPLY:
• 0 = not allowed
• 1 = must be left set.
Bit 3 - ENABLE LP:
• 0 = disables the low power function of the LOW_PWR pin.
• 1 = enables the low power function of the LOW_PWR pin.
Bit 2 - MAIN DISCHARGE:
• 0 = disable the active discharge of the VMAIN converter output.
• 1 = enable the active discharge of the VMAIN converter output, when the converter is disabled.
Bit 1-Bit 0 - MAIN<1:0>: The VMAIN converter output voltages are set according to the following table, with the
default values in bold set by the DEFMAIN pin. The default voltage can subsequently be over-written via the
serial interface after start-up.
MAIN1
MAIN0
VMAIN
0
0
2.5 V
0
1
2.75 V
1
0
3.0 V
1
1
3.3 V
VDCDC2 Register (Address: 0Dh—Default Value: 60h/70h)
VDCDC2
B7
Bit name
LP_COREOFF
B6
CORE2
B5
B4
CORE1
CORE0
B3
B2
CORELP1
CORELP0
B1
B0
VIB
CORE
DISCHARGE
Default
0
1
1
DEFCORE
1
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The VDCDC2 register is used to program the VCORE switching converter output voltage. It is programmable in 8
steps between 0.85 V and 1.6 V. The default value is governed by the DEFCORE pin; DEFCORE=0 sets an
output voltage of 1.5 V. DEFCORE=1 sets an output voltage of 1.6 V.
Bit 7 - LP_COREOFF:
• 0 = VCORE converter is enabled in low power mode.
• 1 = VCORE converter is disabled in low power mode.
Bit 6-Bit 4 - CORE<2:0>: The following table shows all possible values of VCORE. The default value can
subsequently be overwritten via the serial interface after start-up.
CORE2
CORE1
CORE0
VCORE
0
0
0
0.85 V
0
0
1
1.0 V
0
1
0
1.1 V
0
1
1
1.2 V
1
0
0
1.3 V
1
0
1
1.4 V
1
1
0
1.5 V
1
1
1
1.6 V
Bit 3-Bit 2 - CORELP<1:0>: CORELP1 and CORELP0 can be used to set the VCORE voltage in low power
mode. In low power mode, CORE2 is effectively '0', and CORE1, CORE0 take on the values programmed at
CORELP1 and CORELP0, default '10' giving VCORE = 1.1V as default in low power mode. When low power
mode is exited, VCORE reverts to the value set by CORE2, CORE1 & CORE0.
Bit 1 - VIB:
• 0 = disables the VIB output transistor.
44
TPS65010
www.ti.com
•
SLVS149A – JUNE 2003 – REVISED JANUARY 2004
1 = enables the VIB output transistor to drive the vibrator motor.
Bit 0 - CORE DISCHARGE:
• 0 = disables the active discharge of the VCORE converter output.
• 1 = enables the active discharge of the VCORE converter, output, when the converter is disabled.
VREGS1Register (Address: 0Eh—Default Value: 88h)
VREGS1
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
LDO2 enable
LDO2 OFF /
nSLP
LDO21
LDO20
LDO1 enable
LDO1 OFF /
nSLP
LDO11
LDO10
Default
1
0
0
0
1
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The VREGS1 register is used to program and enable LDO1 and LDO2 and to set their behavior when low power
mode is active. The LDO output voltages can be set either on the fly, while the relevant LDO is disabled, or
simultaneously when the relevant enable bit is set. Note that both LDOs are per default ON.
Bit 7-Bit 6 - The function of the LDO2 enable and LDO2 OFF / nSLP bits is shown in the following table. See the
power-on sequencing section for details of low-power mode.
LDO2 ENABLE
LDO2 OFF / nSLP
LDO STATUS IN NORMAL MODE
0
X
OFF
LDO STATUS IN LOW-POWER MODE
OFF
1
0
ON, full power
ON, reduced power / performance
1
1
ON, full power
OFF
Bit 5-Bit 4 - LDO2<1:0>: LDO2 has a default output voltage of 1.8 V. If so desired, this can be changed at the
same time as it is enabled via the serial interface.
LDO21
LDO20
VLDO2
0
0
1.8 V
0
1
2.5 V
1
0
2.75 V
1
1
3.0 V
Bit 3-Bit 2 - The function of the LDO1 enable and LDO1 OFF / nSLP bits is shown in the following table. See the
power-on sequencing section for details of low-power mode. Note that programming LDO1 to a higher voltage
may force a system power on reset if the increase is in the 10% or greater range.
LDO1 ENABLE
LDO1 OFF / nSLP
LDO STATUS IN NORMAL MODE
LDO STATUS IN LOW-POWER MODE
0
X
OFF
OFF
1
0
ON, full power
ON, reduced power / performance
1
1
ON, full power
OFF
Bit 1-Bit 0 - LDO1<1:0>: The LDO1 output voltage is per default set externally. If so desired, this can be changed
via the serial interface.
LDO11
LDO10
VLDO1
0
0
ADJ
0
1
2.5 V
1
0
2.75 V
1
1
3.0 V
45
TPS65010
www.ti.com
SLVS149A – JUNE 2003 – REVISED JANUARY 2004
MASK3 Register (Address: 0Fh—Default Value: 00h)
MASK3
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
Edge trigger
GPIO4
Edge trigger
GPIO3
Edge trigger
GPIO2
Edge trigger
GPIO1
Mask GPIO4
Mask GPIO3
Mask GPIO2
Mask GPIO1
Default
0
0
0
0
0
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The MASK3 register must be considered when any of the GPIO pins are programmed as inputs.
Bit 7-Bit 4 - Edge trigger GPIO<4:1>: determine whether the respective GPIO generates an interrupt at a rising or
a falling edge.
• 0 = falling edge triggered.
• 1 = rising edge triggered.
Bit 3-Bit 0 - Mask GPIO<4:1>: can be used to mask the corresponding interrupt. Default is unmasked
(MASK3<0:3> =0).
DEFGPIO Register Address: (10h—Default Value: 00h)
DEFGPIO
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
IO4
IO3
IO2
IO1
Value GPIO4
Value GPIO3
Value GPIO2
Value GPIO1
Default
0
0
0
0
0
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The DEFGPIO register is used to define the GPIO pins to be either input or output.
Bit 7-Bit 4 - IO<4:1>:
• 0 = sets the corresponding GPIO to be an input.
• 1 = sets the corresponding GPIO to be an output.
Bit 3-Bit 0 - Value GPIO<4:1>: If a GPIO is programmed to be an output, then the signal output is determined by
the corresponding bit. The output circuit for each GPIO is an open drain NMOS requiring an external pullup
resistor.
• 1 = activates the relevant NMOS, hence forcing a logic low signal at the GPIO pin.
• 0 = turns the open drain transistor OFF, hence the voltage at the GPIO pin is determined by the voltage to
which the pullup resistor is connected.
If a particular GPIO is programmed to be an input, then the contents of the relevant bit in B3-0 is defined by the
logic level at the GPIO pin. A logic low forces a 0 and a logic high forces a 1. If a GPIO is programmed to be an
input, then any attempt to write to the relevant bit in B3-0 is ignored.
46
TPS65010
www.ti.com
SLVS149A – JUNE 2003 – REVISED JANUARY 2004
DESIGN PROCEDURE
Inductor Selection for the Main and the Core Converter
The main and the core converters in the TPS65010 typically use a 6.2-µH and a 10-µH output inductor
respectively. Larger or smaller inductor values can be used to optimize the performance of the device for specific
operation conditions. The selected inductor has to be rated for its dc resistance and saturation current. The dc
resistance of the inductance influences directly the efficiency of the converter. Therefore, an inductor with lowest
dc resistance is selected for highest efficiency.
Equation 3 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 3. This is needed
because during heavy load transient, the inductor current rises above the value calculated under Equation 3.
V
1– O
V
I
I V L
O
Lƒ
(3)
I
I
I
L
L(max)
O(max)
2
(4)
with:
• f = Switching Frequency (1.25 MHz typical)
• L = Inductor Value
• ∆IL= Peak-to-peak inductor ripple current
• ILmax = Maximum inductor current
The highest inductor current occurs at maximum VI.
Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents
versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
TPS65010 (2 A for the main converter and 0.8 A for the core converter). Keep in mind that the core material from
inductor to inductor differs and has an impact on the efficiency especially at high switching frequencies.
Refer to Table 3 and the typical applications for possible inductors
Table 3. Tested Inductors
DEVICE
INDUCTOR VALUE
DIMENSIONS
COMPONENT SUPPLIER
10 µH
6,0 mm × 6,0 mm × 2,0 mm
Sumida CDRH5D18-100
10 µH
5,0 mm × 5,0 mm × 3.0 mm
Sumida CDRH4D28-100
4.7 µH
5,5 mm × 6,6 mm*1.0 mm
Coilcraft LPO1704-472M
4.7 µH
5,0 mm × 5,0 mm × 3.0 mm
Sumida CDRH4D28C-4.7
4.7 µH
5,2 mm × 5.2 mm × 2.5 mm
Coiltronics SD25-4R7
5.3 µH
5,7 mm × 5.7 mm × 3.0 mm
Sumida CDRH5D28-5R3
6.2 µH
5,7 mm × 5.7 mm × 3.0 mm
Sumida CDRH5D28-6R2
6.0 µH
7.0 mm × 7.0 mm × 3.0 mm
Sumida CDRH6D28-6R0
Core converter
Main converter
Output Capacitor Selection
The advanced fast response voltage mode control scheme of the inductive converters implemented in the
TPS65010 allow the use of small ceramic capacitors with a typical value of 22 µF for the main converter and 10
µF for the core converter without having large output voltage under and overshoots during heavy load transients.
Ceramic capacitors having low ESR values have the lowest output voltage ripple and are recommended. If
required tantalum capacitors with an ESR < 100 ΩR may be used as well.
Refer to Table 4 for recommended components.
47
TPS65010
www.ti.com
SLVS149A – JUNE 2003 – REVISED JANUARY 2004
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meet the application
requirements. Just for completeness the RMS ripple current is calculated as:
V
1– O
V
I
I
V 1
RMSC(out)
O
Lƒ
2 3
(5)
At nominal load current, the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
V
1– O
V
I
1
V V ESR
O
O
8C ƒ
Lƒ
O
(6)
Where the highest output voltage ripple occurs at the highest input voltage VI.
At light load currents, the converters operate in power save mode and the output voltage ripple is independent of
the output capacitor value. The output voltage ripple is set by the internal comparator thresholds. The typical
output voltage ripple is 1% of the nominal output voltage. If the output voltage for the core converter is
programmed to its lowest voltage of 0.85 V, the output capacitor must be increased to 22 µF for low output
voltage ripple. This is because the current in the inductor decreases slowly during the off-time and further
increases the output voltage even when the PMOS is off. This effect increases with low output voltages.
Input Capacitor Selection
Because of the nature of the buck converter, having a pulsating input current a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. The main converter needs a 22-µF ceramic input capacitor and the core converter a 10-µF
ceramic capacitor. The input capacitor for the main and the core converter can be combined and one 22-µF
capacitor can be used instead, because the two converters operate with a phase shift of 270 degrees. The input
capacitor can be increased without any limit for better input voltage filtering. The VCC pin should be separated
from the input for the main and the core converter. A filter resistor of up to 100R and a 1-µF capacitor is used for
decoupling the VCC pin from switching noise.
Table 4. Possible Capacitors
CAPACITOR VALUE
CASE SIZE
COMPONENT SUPPLIER
COMMENTS
22 µF
1206
TDK C3216X5R0J226M
Ceramic
22 µF
1206
Taiyo Yuden JMK316BJ226ML
Ceramic
22 µF
1210
Taiyo Yuden JMK325BJ226MM
Ceramic
LDO1
Output Voltage Adjustment
The output voltage of LDO1 is set with a resistor divider at the feedback pin. The sum of the two resistors must
not exceed 1 MR to minimize voltage changes due to leakage current into the feedback pin. The output voltage
for LDO1 after start up is the voltage set by the external resistor divider. It can be reprogrammed with the I2C
interface to the three other values defined in the register VREGS1.
48
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