TI TPS65023RSB

TPS65023
www.ti.com
SLVS670A – JUNE 2006 – REVISED JUNE 2006
POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS
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1.5 A, 97% Efficient Step-Down Converter for
Processor Core (VDCDC1)
1.2 A, Up to 95% Efficient Step-Down
Converter for System Voltage (VDCDC2)
1.0 A, 90% Efficient Step-Down Converter for
Memory Voltage (VDCDC3)
30 mA LDO/Switch for Real Time Clock
(VRTC)
2 x 200 mA General-Purpose LDO
Dynamic Voltage Management for Processor
Core
Preselectable LDO Voltage Using Two Digital
Input Pins
Externally Adjustable Reset Delay Time
Battery Backup Functionality
Separate Enable Pins for Inductive
Converters
I2C™ Compatible Serial Interface
85-µA Quiescent Current
Low Ripple PFM Mode
Thermal Shutdown Protection
40 Pin, 6 mm x 6 mm QFN Package
APPLICATIONS
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DESCRIPTION
The TPS65023 is an integrated Power Management
IC for applications powered by one Li-Ion or
Li-Polymer cell, and which require multiple power
rails. The TPS65023 provides three highly efficient,
step-down converters targeted at providing the core
voltage, peripheral, I/O and memory rails in a
processor based system. The core converter allows
for on-the-fly voltage changes via serial interface,
allowing the system to implement dynamic power
savings. All three step-down converters enter a
low-power mode at light load for maximum efficiency
across the widest possible range of load currents.
The TPS65023 also integrates two general-purpose
200 mA LDO voltage regulators, which are enabled
with an external input pin. Each LDO operates with
an input voltage range between 1.5 V and 6.5 V,
allowing them to be supplied from one of the
step-down converters or directly from the battery.
The default output voltage of the LDOs can be
digitally set to 4 different voltage combinations using
the DEFLDO1 and DEFLDO2 pins. The serial
interface can be used for dynamic voltage scaling,
masking interrupts, or for dis/enabling and setting the
LDO output voltages. The interface is compatible
with the Fast/Standard mode I2C specification,
allowing transfers at up to 400 kHz. The TPS65023
is available in a 40-pin (RHA) QFN package, and
operates over a free-air temperature of -40°C to
85°C.
Digital Media Players
Internet Audio Player
Digital Still Camera
Digital Radio Player
Supply DaVinci™ DSP Family Solutions
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DaVinci, PowerPAD are trademarks of Texas Instruments.
I2C is a trademark of Philips Electronics.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2006, Texas Instruments Incorporated
PRODUCT PREVIEW
FEATURES
TPS65023
www.ti.com
SLVS670A – JUNE 2006 – REVISED JUNE 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
(2)
TA
PACKAGE (1)
PART NUMBER (2)
–40°C to 85°C
40 pin QFN (RSB)
TPS65023RSB
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
The RSB package is available in tape and reel. Add the R suffix (TPS65023RSBR) to order quantities of 2500 parts per reel. Add the T
suffix (TPS65023RSBT) to order quantities of 250 parts per reel.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
VI
Input voltage range on all pins except AGND and PGND pins with respect to AGND
UNIT
–0.3 to 7
V
Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3
2000
mA
Peak current at all other pins
1000
mA
PRODUCT PREVIEW
Continuous total power dissipation
See Dissipation Rating Table
TA
Operating free-air temperature
–40 to 85
°C
TJ
Maximum junction temperature
125
°C
–65 to 150
°C
Tstg Storage temperature
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
DISSIPATION RATINGS
(1)
(2)
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
RHA (1) (2)
2.85 W
28 mW/°C
1.57 W
1.14 W
The thermal resistance junction to ambient of the RHA package is 35°C/W measured on a high K board.
The thermal resistance junction to case (exposed pad) of the RHA package is 5°C/W
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
2.5
6
Output voltage range for VDCDC1 step-down converter (1)
0.6
VINDCDC1
Output voltage range for VDCDC2 (mem) step-down converter (1)
0.6
VINDCDC2
Output voltage range for VDCDC3 (core) step-down converter (1)
0.6
VINDCDC3
VI
Input voltage range for LDOs (VINLDO1, VINLDO2)
1.5
6.5
VO
Output voltage range for LDOs (VLDO1, VLDO2)
1
VINLDO1-2
IO(DCDC2)
Output current at L1
VCC
VO
1500
Inductor at L1 (2)
CI(DCDC1)
Input capacitor at VINDCDC1
CO(DCDC1)
Output capacitor at VDCDC1
IO(DCDC2)
Output current at L2
Inductor at L2
(1)
(2)
2
NOM
Input voltage range step-down converters
(VINDCDC1, VINDCDC2, VINDCDC3)
2.2
(2)
10
2.2
When using an external resistor divider at DEFDCDC3, DEFDCDC2, DEFDCDC1
See Applications Information section for more information.
Submit Documentation Feedback
V
V
V
mA
µF
µF
22
1200
(2)
V
µH
3.3
10
(2)
UNIT
3.3
mA
µH
TPS65023
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SLVS670A – JUNE 2006 – REVISED JUNE 2006
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
CI(DCDC2)
Input capacitor at VINDCDC2
CO(DCDC2)
Output capacitor at VDCDC2
IO(DCDC3)
Output current at L3
(2)
MAX
10
µF
22
1000
2.2
CI(DCDC3)
Input capacitor at VINDCDC3 (2)
10
CO(DCDC3)
Output capacitor at VDCDC3
(2)
10
(2)
UNIT
µF
10
(2)
(2)
Inductor at L3
NOM
mA
µH
3.3
µF
µF
22
1
µF
1
µF
CI(VCC)
Input capacitor at VCC
Ci(VINLDO)
Input capacitor at VINLDO
CO(VLDO1-2)
Output capacitor at VLDO1, VLDO2
IO(VLDO1-2)
Output current at VLDO1, VLDO2
CO(VRTC)
Output capacitor at VRTC
TA
Operating ambient temperature
-40
85
°C
TJ
Operating junction temperature
-40
125
°C
10
Ω
(2)
(2)
200
(3)
mA
µF
4.7
Resistor from VINDCDC3, VINDCDC2, VINDCDC1 to VCC used for
filtering (4)
1
See Applications Information section for more information.
Up to 3 mA can flow into VCC when all 3 converters are running in PWM. This resistor causes the UVLO threshold to be shifted
accordingly.
PRODUCT PREVIEW
(3)
(4)
µF
2.2
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CONTROL SIGNALS : SCLK, SDAT (input), DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2
VIH
High level input voltage
Resistor pullup at SCLK and SDAT = 4.7
kΩ, pulled to VRTC
1.3
VCC
V
VIL
Low level input voltage
Resistor pullup at SCLK and SDAT = 4.7
kΩ, pulled to VRTC
0
0.4
V
IH
Input bias current
0.1
µA
VCC
V
0.01
CONTROL SIGNALS : HOT_RESET
VIH
High-level input voltage
1.3
VIL
Low-level input voltage
0
IIB
Input bias current
tglitch
Deglitch time at HOT_RESET
25
0.4
V
0.01
0.1
µA
30
35
ms
6
V
CONTROL SIGNALS : LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (output)
VOH
High-level output voltage
VOL
Low-level output voltage
IIL = 5 mA
Duration of low pulse at RESPWRON
External capacitor 1 nF
Resetpwron threshold
VRTC falling
–3%
2.4
3%
V
Resetpwron threshold
VRTC rising
–3%
2.52
3%
V
Submit Documentation Feedback
0
0.3
100
V
ms
3
TPS65023
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SLVS670A – JUNE 2006 – REVISED JUNE 2006
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3
I(q)
II
PRODUCT PREVIEW
I(q)
Operating quiescent
current, PFM
Current into VCC;
PWM
Quiescent current
All 3 DCDC converters enabled,
zero load, and no switching, LDOs
enabled
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
85
100
All 3 DCDC converters enabled,
zero load, and no switching, LDOs
off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
78
90
DCDC1 and DCDC2 converters
enabled, zero load, and no
switching, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
57
70
DCDC1 converter enabled, zero
load, and no switching, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
43
55
All 3 DCDC converters enabled
and running in PWM, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
2
3
DCDC1 and DCDC2 converters
enabled and running in PWM,
LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
1.5
2.5
DCDC1 converter enabled and
running in PWM, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
0.85
2
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
23
33
µA
VCC = 2.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
3.5
5
µA
43
µA
All converters disabled, LDOs off
VCC = 3.6 V, VBACKUP = 0 V;
V(VSYSIN) = 0 V
4
Submit Documentation Feedback
µA
mA
TPS65023
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SLVS670A – JUNE 2006 – REVISED JUNE 2006
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
20
33
µA
3
µA
SUPPLY PINS: VBACKUP, VSYSIN, VRTC
I(q)
Operating quiescent current
VBACKUP = 3 V, VSYSIN = 0 V;
VCC = 2.6 V, current into VBACKUP
I(SD)
Operating quiescent current
VBACKUP < V_VBACKUP, current into
VBACKUP
2
VRTC LDO output voltage
VSYSIN = VBACKUP = 0 V, IO = 0 mA
3
Output current for VRTC
VSYSIN < 2.57 V and VBACKUP < 2.57 V
30
mA
VRTC short-circuit current limit
VRTC = GND; VSYSIN = VBACKUP = 0 V
100
mA
Maximum output current at VRTC for
RESPWRON = 1
VRTC > 2.6 V, VCC = 3 V;
VSYSIN = VBACKUP = 0 V
Output voltage accuracy for VRTC
VSYSIN = VBACKUP = 0 V; IO = 0 mA
-1%
1%
Line regulation for VRTC
VCC = VRTC + 0.5 V to 6.5 V, IO = 5 mA
-1%
1%
Load regulation VRTC
IO = 1 mA to 30 mA;
VSYSIN = VBACKUP = 0 V
-3%
1%
Regulation time for VRTC
Load change from 10% to 90%
Input leakage current at VSYSIN
VSYSIN < V_VSYSIN
VO
Ilkg
30
mA
µs
10
rDS(on) of VSYSIN switch
2
µA
12.5
Ω
12.5
Ω
Input voltage range at VBACKUP (1)
2.73
3.75
V
Input voltage range at VSYSIN (1)
2.73
3.75
V
rDS(on) of VBACKUP switch
VSYSIN threshold
VSYSIN falling
–3%
2.55
3%
V
VSYSIN threshold
VSYSIN rising
–3%
2.65
3%
V
VBACKUP threshold
VBACKUP falling
–3%
2.55
3%
V
VBACKUP threshold
VBACKUP falling
–3%
2.65
3%
V
PRODUCT PREVIEW
IO
V
SUPPLY PIN: VINLDO
I(q)
I(SD)
(1)
Operating quiescent current
Current per LDO into VINLDO
16
30
µA
Shutdown current
Total current for both LDOs into VINLDO,
VLDO = 0 V
0.1
1
µA
Based on the requirements for the Intel PXA270 processor.
Submit Documentation Feedback
5
TPS65023
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SLVS670A – JUNE 2006 – REVISED JUNE 2006
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDCDC1 STEP-DOWN CONVERTER
VI
Input voltage range, VINDCDC1
IO
Maximum output current
I(SD)
Shutdown supply current in VINDCDC1
DCDC1_EN = GND
0.1
1
µA
rDS(on)
P-channel MOSFET on-resistance
VINDCDC1 = V(GS) = 3.6 V
125
261
mΩ
Ilkg
P-channel leakage current
VINDCDC1 = 6 V
2
µA
rDS(on)
N-channel MOSFET on-resistance
VINDCDC1 = V(GS) = 3.6 V
130
260
mΩ
Ilkg
N-channel leakage current
V(DS) = 6 V
7
10
µA
Forward current limit (P-channel and
N-channel)
2.5 V < VI(MAIN) < 6 V
TBD
TBD
TBD
A
1.95
2.25
2.55
MHz
fS
2.5
Oscillator frequency
Fixed output voltage
FPWMDCDC1=0
TBD
TBD
VINDCDC1 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.5 A
TBD
TBD
Adjustable output voltage with resistor
divider at DEFDCDC1; FPWMDCDC1=0
VINDCDC1 = VDCDC1 + 0.3 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 1.2 A
–2%
2%
Adjustable output voltage with resistor
divider at DEFDCDC1; FPWMDCDC1=1
VINDCDC1 = VDCDC1 + 0.3 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 1.2 A
–1%
1%
Line Regulation
VINDCDC1 = VDCDC1 + 0.3 V (min. 2.5 V)
to 6 V; IO = 10 mA
Load Regulation
Soft start ramp time
All VDCDC1
PRODUCT PREVIEW
0
%/V
IO = 10 mA to 1200 mA
0.25
%/A
VDCDC1 ramping from 5% to 95% of target
value
750
µs
1
MΩ
DCDC1 discharge = 1
300
Internal resistance from L1 to GND
VDCDC1 discharge resistance
V
mA
VINDCDC1 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.5 A
Fixed output voltage
FPWMDCDC1=1
6
6
1500
Submit Documentation Feedback
Ω
TPS65023
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SLVS670A – JUNE 2006 – REVISED JUNE 2006
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDCDC2 STEP-DOWN CONVERTER
VI
Input voltage range, VINDCDC2
IO
Maximum output current
2.5
6
I(SD)
Shutdown supply current in VINDCDC2
DCDC2_EN = GND
0.1
1
µA
rDS(on)
P-channel MOSFET on-resistance
VINDCDC2 = V(GS) = 3.6 V
140
300
mΩ
Ilkg
P-channel leakage current
VINDCDC2 = 6 V
2
µA
rDS(on)
N-channel MOSFET on-resistance
VINDCDC2 = V(GS) = 3.6 V
150
297
mΩ
Ilkg
N-channel leakage current
V(DS) = 6 V
7
10
µA
ILIMF
Forward current limit (P-channel and
N-channel)
2.5 V < VINDCDC2 < 6 V
TBD
TBD
TBD
A
fS
Oscillator frequency
1.95
2.25
2.55
MHz
VDCDC2 = 1.8 V
VINDCDC2 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.2 A
TBD
TBD
VDCDC2 = 3.3 V
VINDCDC2 = 3.6 V to 6 V;
0 mA ≤ IO ≤ 1.2 A
TBD
TBD
VDCDC2 = 1.8 V
VINDCDC2 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.2 A
TBD
TBD
VDCDC2 = 3.3 V
VINDCDC2 = 3.6 V to 6 V;
0 mA ≤ IO ≤ 1.2 A
TBD
TBD
Adjustable output voltage with resistor
divider at DEFDCDC2 FPWMDCDC2=0
VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 1 A
–2%
2%
Adjustable output voltage with resistor
divider at DEFDCDC2; FPWMDCDC2=1
VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 1 A
–1%
1%
Line Regulation
VINDCDC2 = VDCDC2 + 0.3 V (min. 2.5 V)
to 6 V; IO = 10 mA
Load Regulation
Soft start ramp time
Fixed output voltage
FPWMDCDC2=0
Fixed output voltage
FPWMDCDC2=1
0
%/V
IO = 10 mA to 1000 mA
0.25
%/A
VDCDC2 ramping from 5% to 95% of target
value
750
µs
1
MΩ
DCDC2 discharge =1
300
Internal resistance from L2 to GND
VDCDC2 discharge resistance
V
mA
Submit Documentation Feedback
PRODUCT PREVIEW
1200
Ω
7
TPS65023
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SLVS670A – JUNE 2006 – REVISED JUNE 2006
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDCDC3 STEP-DOWN CONVERTER
VI
Input voltage range, VINDCDC3
IO
Maximum output current
I(SD)
Shutdown supply current in VINDCDC3
DCDC3_EN = GND
0.1
1
µA
rDS(on)
P-channel MOSFET on-resistance
VINDCDC3 = V(GS) = 3.6 V
310
698
mΩ
Ilkg
P-channel leakage current
VINDCDC3 = 6 V
0.1
2
µA
rDS(on)
N-channel MOSFET on-resistance
VINDCDC3 = V(GS) = 3.6 V
220
503
mΩ
Ilkg
N-channel leakage current
V(DS) = 6 V
7
10
µA
Forward current limit (P-channel and
N-channel)
2.5 V < VINDCDC3 < 6 V
TBD
TBD
TBD
A
1.95
2.25
2.55
MHz
fS
2.5
Oscillator frequency
VDCDC3 = 1.8V
TBD
TBD
VDCDC3 = 3.3V
VINDCDC3 = 3.6 V to 6 V;
0 mA ≤ IO ≤ 1 A
TBD
TBD
VDCDC3 = 1.8V
VINDCDC3 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1 A
TBD
TBD
VDCDC3 = 3.3V
VINDCDC3 = 3.6 V to 6 V;
0 mA ≤ IO ≤ 1 A
TBD
TBD
Adjustable output voltage with resistor
divider at DEFDCDC3 FPWMDCDC3=0
VINDCDC3 = VDCDC3 + 0.5 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 800 mA
–2%
2%
Adjustable output voltage with resistor
divider at DEFDCDC3; FPWMDCDC3=1
VINDCDC3 = VDCDC3 + 0.5 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 800 mA
–1%
1%
Line Regulation
VINDCDC3 = VDCDC3 + 0.3 V (min. 2.5 V)
to 6 V; IO = 10 mA
Load Regulation
Soft start ramp time
PRODUCT PREVIEW
Fixed output voltage
FPWMDCDC3=1
0
%/V
IO = 10 mA to 1000 mA
0.25
%/A
VDCDC3 ramping from 5% to 95% of target
value
750
µs
1
MΩ
DCDC3 discharge =1
300
Internal resistance from L3 to GND
VDCDC3 discharge resistance
V
mA
VINDCDC3 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1 A
Fixed output voltage
FPWMDCDC3=0
8
6
1000
Submit Documentation Feedback
Ω
TPS65023
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SLVS670A – JUNE 2006 – REVISED JUNE 2006
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VLDO1 and VLDO2 LOW DROPOUT REGULATORS
Input voltage range for LDO1, 2
VO(LD01)
LDO1 output voltage range
VO(LDO2)
LDO2 output voltage range
IO
Maximum output current for LDO1,
LDO2
I(SC)
LDO1 and LDO2 short circuit
current limit
Minimum voltage drop at LDO1,
LDO2
VI = 1.8 V, VO = 1.3 V
1.5
6.5
V
1
3.3
V
1
3.3
V
200
VI = 1.5 V, VO = 1.3 V
mA
120
V(LDO1) = GND, V(LDO2) = GND
400
IO = 50 mA, VINLDO = 1.8 V
120
IO = 50 mA, VINLDO = 1.5 V
65
IO = 200 mA, VINLDO = 1.8 V
150
mA
mV
300
Output voltage accuracy for LDO1,
LDO2
IO = 10 mA
–2%
1%
Line regulation for LDO1, LDO2
VINLDO1, 2 = VLDO1,2 + 0.5 V
(min. 2.5 V) to 6.5 V, IO = 10 mA
–1%
1%
Load regulation for LDO1, LDO2
IO = 0 mA to 50 mA
–1%
1%
Regulation time for LDO1, LDO2
Load change from 10% to 90%
PRODUCT PREVIEW
VI
µs
10
ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3
VIH
High-level input voltage
1.3
VCC
V
VIL
Low-level input voltage
0
0.1
V
0.05
µA
Input bias current
0.001
THERMAL SHUTDOWN
T(SD)
Thermal shutdown
Increasing junction temperature
160
°C
Thermal shutdown hysteresis
Decreasing junction temperature
20
°C
INTERNAL UNDERVOLTAGE LOCK OUT
UVLO
Internal UVLO
V(UVLO_HYST)
Internal UVLO comparator
hysteresis
VCC falling
–2%
2.35
2%
120
V
mV
VOLTAGE DETECTOR COMPARATORS
Comparator threshold
(PWRFAIL_SNS, LOWBAT_SNS)
Falling threshold
Hysteresis
Propagation delay
–1%
1
1%
V
40
50
60
mV
10
µs
25-mV overdrive
POWER GOOD
V(PGOODF)
VDCDC1, VDCDC2, VDCDC3, VLDO1,
VLDO2, decreasing
–12%
–10%
–8%
V(PGOODR)
VDCDC1, VDCDC2, VDCDC3, VLDO1,
VLDO2, increasing
–7%
–5%
–3%
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PWRFAIL
VDCDC2
DEFDCDC2
PGND2
VINDCDC2
L2
PWRFAIL_SNS
VCC
AGND1
LOWBAT_SNS
PIN ASSIGNMENT
(TOP VIEW)
40 39 38 37 36 35 34 33 32 31
DEFDCDC3
1
30
SCLK
VDCDC3
2
29
SDAT
3
28
INT
L3
4
27
RESPWRON
VINDCDC3
5
26
TRESPWRON
VINDCDC1
6
25
DCDC1_EN
L1
7
24
DCDC2_EN
PGND1
8
23
DCDC3_EN
VDCDC1
9
22
LDO_EN
10
21
LOWBAT
PGND3
VLDO1
VINLDO
VLDO2
AGND2
VRTC
VBACKUP
VSYSIN
DEFLDO2
DEFLDO1
11 12 13 14 15 16 17 18 19 20
HOT_RESET
PRODUCT PREVIEW
DEFDCDC1
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
SWITCHING REGULATOR SECTION
AGND1
40
Analog ground. All analog ground pins are connected internally on the chip.
AGND2
17
Analog ground. All analog ground pins are connected internally on the chip.
PowerPAD™
–
Connect the power pad to analog ground.
VINDCDC1
6
L1
7
VDCDC1
9
PGND1
8
VINDCDC2
36
L2
35
VDCDC2
33
PGND2
34
VINDCDC3
5
L3
4
VDCDC3
2
PGND3
3
VCC
37
10
I
Input voltage for VDCDC1 step-down converter. VINDCDC1 must be connected to the same voltage
supply as VINDCDC2, VINDCDC3, and VCC.
Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.
I
VDCDC1 feedback voltage sense input. Connect directly to VDCDC1
Power ground for VDCDC1 converter.
I
Input voltage for VDCDC2 step-down converter. VINDCDC2 must be connected to the same voltage
supply as VINDCDC1, VINDCDC3, and VCC.
Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.
I
VDCDC2 feedback voltage sense input. Connect directly to VDCDC2
Power ground for VDCDC2 converter
I
Input voltage for VDCDC3 step-down converter. VINDCDC3 must be connected to the same voltage
supply as VINDCDC1, VINDCDC2, and VCC.
Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.
I
VDCDC3 feedback voltage sense input. Connect directly to VDCDC3
Power ground for VDCDC3 converter.
I
Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 dc-dc converters.
VCC must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2.
VCC also supplies serial interface block.
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
DEFDCDC1
10
I
Input signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V DEFDCDC1 can also be
connected to a resistor divider between VDCDC1 and GND, if the output voltage of the DCDC1
converter is set in a range from 0.6 V to VINDCDC1 V.
DEFDCDC2
32
I
Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 3.3 V DEFDCDC2 can also be
connected to a resistor divider between VDCDC2 and GND, if the output voltage of the DCDC2
converter is set in a range from 0.6 V to VINDCDC2 V.
DEFDCDC3
1
I
Input signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V DEFDCDC3 can also be
connected to a resistor divider between VDCDC3 and GND, if the output voltage of the DCDC3
converter is set in a range from 0.6 V to VINDCDC3 V.
DCDC1_EN
25
I
VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC2_EN
24
I
VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC3_EN
23
I
VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.
VINLDO
19
I
Input voltage for LDO1 and LDO2
VLDO1
20
O
Output voltage of LDO1
VLDO2
18
O
Output voltage of LDO2
LDO_EN
22
I
Enable input for LDO1 and LDO2. A Logic high enables the LDOs, a logic low disables the LDOs.
VBACKUP
15
I
Connect the backup battery to this input pin.
VRTC
16
O
Output voltage of the LDO/switch for the real time clock.
VSYSIN
14
I
Input of system voltage for VRTC switch.
DEFLD01
12
I
Digital input. DEFLD01 sets the default output voltage of LDO1 and LDO2.
DEFLD02
13
I
Digital input. DEFLD02 sets the default output voltage of LDO1 and LDO2.
PRODUCT PREVIEW
LDO REGULATOR SECTION
CONTROL AND I2C SECTION
HOT_RESET
11
I
Push button input that reboots or wakes up the processor via RESPWRON output pin.
TRESPWRON
26
I
Connect the timing capacitor to TRESPWRON to set the reset delay time: 1 nF → 100 ms.
RESPWRON
27
O
Open drain system reset output.
PWRFAIL
31
O
Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.
LOW_BAT
21
O
Open drain output of LOW_BAT comparator.
INT
28
O
Open drain output
SCLK
30
I
Serial interface clock line
SDAT
29
I/O
PWRFAIL_SNS
38
I
Input for the comparator driving the PWRFAIL output.
LOWBAT_SNS
39
I
Input for the comparator driving the LOW_BAT output.
Serial interface data/address
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FUNCTIONAL BLOCK DIAGRAM
VCC
VSYSIN
VBACKUP
VRTC
TPS65023
BBAT
SWITCH
Thermal
Shutdown
VINDCDC1
L1
DCDC1
Buck Converter
1500 mA
SCLK
SDAT
VDCDC1
DEFDCDC1
PGND1
Serial Interface
VINDCDC2
DCDC1_EN
L2
DCDC2_EN
DCDC2
Buck Converter
1200 mA
DCDC3_EN
LDO_EN
CONTROL
VDCDC2
DEFDCDC2
PGND2
HOT_RESET
PRODUCT PREVIEW
Dynamic
Voltage
Management
RESPWRON
INT
VINDCDC3
L3
LOWBAT_SNS
PWRFAIL_SNS
LOW_BATT
PWRFAIL
DCDC3
Buck Converter
1000 mA
UVLO
VREF
OSC
VDCDC3
DEFDCDC3
PGND3
TRESPWRON
LDO1
200 mA
DEFLDO1
DEFLDO2
VLDO1
VINLDO
LDO2
200 mA
VLDO2
AGND1
AGND2
12
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TYPICAL CHARACTERISTICS
Graphs were taken using the EVM with the following inductor/output capacitor combinations:
CONVERTER
INDUCTOR
OUTPUT CAPACITOR
OUTPUT CAPACITOR VALUE
VDCDC1
VLCF4020-2R2
C2012X5R0J106M
2 × 10 µF
VDCDC2
VLCF4020-2R2
C2012X5R0J106M
2 × 10 µF
VDCDC3
VLF4012AT-2R2M1R5
C2012X5R0J106M
2 × 10 µF
Table 1. Table of Graphs
FIGURE
Efficiency
vs Output current
1, 2, 3, 4, 5, 6, 7
Line transient response
8, 9, 10
Load transient response
11, 12, 13
VDCDC2 PFM operation
14
VDCDC2 low ripple PFM operation
15
VDCDC2 PWM operation
16
Startup VDCDC1, VDCDC2 and VDCDC3
17
Startup LDO1 and LDO2
18
Line transient response
19, 20, 21
Load transient response
22, 23, 24
PRODUCT PREVIEW
η
Data presented in Figures 1 - 16 are representative of the TPS65021. The curves are subject to change.
DCDC1: EFFICIENCY
vs
OUTPUT CURRENT
DCDC1: EFFICIENCY
vs
OUTPUT CURRENT
VI = 3.8 V
VI = 4.2 V
VI = 4.2 V
VI = 3.8 V
Efficiency - %
Efficiency - %
VI = 5 V
VI = 5 V
TA = 25oC
VO = 3.3 V
PFM / PWM Mode
0.01
0.1
1
10
100
1k
o
TA = 25 C
VO = 3.3 V
PWM Mode
10 k
0.01
IO - Output Current - mA
0.1
1
10
100
1k
10 k
IO - Output Current - mA
Figure 1.
Figure 2.
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DCDC2: EFFICIENCY
vs
OUTPUT CURRENT
DCDC2: EFFICIENCY
vs
OUTPUT CURRENT
VI = 2.5 V
VI = 3.8 V
Efficiency - %
Efficiency - %
VI = 3.8 V
VI = 4.2 V
VI = 4.2 V
VI = 2.5 V
VI = 5 V
VI = 5 V
TA = 25oC
VO = 1.8 V
PWM Mode
o
TA = 25 C
VO = 1.8 V
PWM / PFM Mode
PRODUCT PREVIEW
0.01
0.1
10
1
100
1k
10 k
0.01
0.1
10
1
100
IO - Output Current - mA
IO - Output Current - mA
Figure 3.
Figure 4.
DCDC3: EFFICIENCY
vs
OUTPUT CURRENT
DCDC3: EFFICIENCY
vs
OUTPUT CURRENT
VI = 3 V
1k
10 k
o
TA = 25 C
VO = 1.55 V
PWM Mode
VI = 2.5 V
VI = 3.8 V
Efficiency - %
Efficiency - %
VI = 3.8 V
VI = 4.2 V
VI = 3 V
VI = 2.5 V
VI = 5 V
VI = 4.2 V
TA = 25oC
VO = 1.55 V
PWM / PFM Mode
0.01
0.1
1
10
100
VI = 5 V
1k
0.01
IO - Output Current - mA
1
10
IO - Output Current - mA
Figure 5.
14
0.1
Figure 6.
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DCDC3: EFFICIENCY
vs
OUTPUT CURRENT
VDCDC1 LINE TRANSIENT RESPONSE
Ch1 = VI
Ch2 = VO
C1 High
4.74 V
VI = 3.8 V
VI = 2.5 V
C1 Low
3.08 V
VI = 4.2 V
C2 PK-PK
85 mV
VI = 5 V
C2 Mean
3.2957 V
IO = 100 mA
VI = 3.6 V to 4.7 V
VO = 3 V
PWM Mode
o
TA = 25 C
VO = 1.3 V
Low Ripple PFM Mode
0.01
0.1
10
1
IO - Output Current - mA
Figure 7.
Figure 8.
VDCDC2 LINE TRANSIENT RESPONSE
VDCDC3 LINE TRANSIENT RESPONSE
Ch1 = VI
Ch2 = VO
C1 High
4.04 V
Ch1 = VI
Ch2 = VO
C1 High
4.05 V
C1 Low
2.95 V
C1 Low
2.94 V
C2 PK-PK
46.0 mV
C2 PK-PK
49.9 mV
C2 Mean
1.79419 V
C2 Mean
1.59798 V
IO = 100 mA
VI = 3 V to 4 V
VO = 1.6 V
PWM Mode
IO = 100 mA
VI = 3 V to 4 V
VO = 1.8 V
PWM Mode
Figure 9.
Figure 10.
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PRODUCT PREVIEW
Efficiency - %
VI = 3 V
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VDCDC1 LOAD TRANSIENT RESPONSE
VDCDC2 LOAD TRANSIENT RESPONSE
Ch2 = VO
Ch4 = IO
Ch2 = VO
Ch4 = IO
C4 High
1.09 A
C4 High
830 mA
C4 Low
120 mA
C4 Low
90 mA
C2 PK-PK
188 mV
C2 PK-PK
80 mV
C2 Mean
3.3051 V
C2 Mean
1.7946 V
IO = 100 mA to 800 mA
VI = 3.8 V
IO = 120 mA to 1080 mA
VI = 3.8 V
VO = 1.8 V
PWM Mode
VO = 3.3 V
PWM Mode
PRODUCT PREVIEW
Figure 11.
Figure 12.
VDCDC3 LOAD TRANSIENT RESPONSE
VDCDC2 OUTPUT VOLTAGE RIPPLE
Ch2 = VO
Ch4 = IO
C4 High
730 mA
VI = 3.8 V
VO = 1.8 V
IO = 1 mA
TA = 25oC
PFM Mode
C4 Low
80 mA
C2 PK-PK
17.0 mV
C2 PK-PK
80 mV
C2 Mean
1.80522 V
C2 Mean
1.5931 V
IO = 80 mA to 720 mA
VI = 3.8 V
VO = 1.6 V
TA = 25oC
PWM Mode
Figure 13.
16
Figure 14.
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VDCDC2 OUTPUT VOLTAGE RIPPLE
VO = 1.8 V
VI = 3.8 V
IO = 1 mA
o
TA = 25 C
Low Ripple PFM Mode
VDCDC2 OUTPUT VOLTAGE RIPPLE
VI = 3.8 V
VO = 1.8 V
IO = 1 mA
TA = 25oC
PWM Mode
C2 PK-PK
7.7 mV
Figure 15.
Figure 16.
STARTUP VDCDC1, VDCDC2, AND VDCDC3
STARTUP LDO1 AND LDO2
PRODUCT PREVIEW
C2 Mean
1.79955 mV
ENABLE
ENABLE
VDCDC1
LDO1
VDCDC2
LDO2
VDCDC3
Figure 17.
Figure 18.
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LDO1 LINE TRANSIENT RESPONSE
Ch1 = VI
Ch2 = VO
IO = 25 mA
VO = 1.1 V
o
TA = 25 C
LDO2 LINE TRANSIENT RESPONSE
C1 High
3.83 V
Ch1 = VI
Ch2 = VO
IO = 25 mA
VO = 3.3 V
TA = 25oC
C1 Low
3.29 V
C1 Low
3.99 V
C2 PK-PK
6.2 mV
C2 PK-PK
6.1 mV
C2 Mean
1.09702 V
PRODUCT PREVIEW
Ch1 = VI
Ch2 = VO
C2 Mean
3.29828 V
Figure 19.
Figure 20.
VRTC LINE TRANSIENT RESPONSE
LDO1 LOAD TRANSIENT RESPONSE
IO = 10 mA
VO = 3 V
o
TA = 25 C
C1 High
3.82 V
C4 High
48.9 mA
C1 Low
3.28 V
C4 Low
2.1 mA
C2 PK-PK
22.8 mV
C2 PK-PK
42.5 mV
C2 Mean
2.98454 V
C2 Mean
1.09664 V
Ch2 = VO
Ch4 = IO
Figure 21.
18
C1 High
4.51 V
VI = 3.3 V
VO = 1.1 V
o
TA = 25 C
Figure 22.
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LDO2 LOAD TRANSIENT RESPONSE
VRTC LOAD TRANSIENT RESPONSE
C4 High
47.8 mA
C4 High
21.4 mA
C4 Low
-2.9 mA
C4 Low
-1.4 mA
C2 PK-PK
40.4 mV
C2 PK-PK
76 mV
C2 Mean
3.29821 V
Ch2 = VO
Ch4 = IO
Figure 23.
VI = 3.8 V
VO = 3 V
o
TA = 25 C
Figure 24.
PRODUCT PREVIEW
Ch2 = VO
Ch4 = IO
VI = 4 V
VO = 3.3 V
TA = 25oC
C2 Mean
2.9762 V
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DETAILED DESCRIPTION
VRTC OUTPUT AND OPERATION WITH OR WITHOUT BACKUP BATTERY
The VRTC pin is an always-on output, intended to supply up to 30 mA to a permanently required rail. The output
voltage selected from a priority scheme based on the VSYSIN and VBACKUP pins. Texas Instruments
recommends that all DaVinci systems connect the VSYSIN and VBACKUP pins to ground and leave the VRTC
output floating.
When the voltage at the VSYSIN pin exceeds 2.65 V, VRTC is connected to the VSYSIN input via a PMOS
switch and all other paths to VRTC are disabled. VSYSIN can be connected to any voltage source with the
approriate input voltage, including either DCDC2 or DCDC3 if set to 3.3V output. When VSYSIN is connected to
ground or drops below 2.65V, the PMOS switch between VRTC and VSYSIN opens and VRTC is then
connected to either VBACKUP or the output of a dedicated 3V/30mA LDO. If VSYSIN is not going to provided to
the TPS65023, the VSYSIN input should be connected to GND.
PRODUCT PREVIEW
In applications using a backup battery, the backup voltage can connected to the TPS65023 VBACKUP pin,
directly if a single Li-Ion cell is used, or via a boost converter (e.g. TPS61070) if a single NiMH battery is used. If
the connection between VRTC and VSYSIN is opened, VRTC will be connected to the VBACKUP input via a
PMOS switch. The TPS65023 asserts the RESPWRON signal if VRTC drops below 2.4 V. The PMOS switch
connecting VBACKUP to VRTC drops 375 mV at 30 mA, setting the minimum voltage applied at VBACKUP to
2.775 V for normal operation. If the both switches between VRTC and VSYSIN or VBACKUP are open, the
dedicated 3V/30mA LDO drives VRTC. In systems where no backup battery is used, the VBACKUP pin should
be connected to GND.
In systems where VSYSIN and VBACKUP inputs grounded, a dedicated low power LDO is enabled. This LDO is
supplied from VCC and capable of delivering 30 mA to a 3 V output. This LDO is disabled if the voltage at the
VSYSIN input exceeds 2.65 V. VRTC is then supplied from the external source connected to this pin as
previously described.
Inside TPS65023 there is a switch (Vmax switch) which selects the higher voltage between VCC and
VBACKUP. This is used as the supply voltage for some basic functions. The functions powered from the output
of the Vmax switch are:
• INT output
• RESPWRON output
• HOT_RESET input
• LOW_BATT output
• PWRFAIL output
• Enable pins for dc-dc converters, LDO1 and LDO2
• Undervoltage lockout comparator (UVLO)
• Reference system with low frequency timing oscillators
• LOW_BATT and PWRFAIL comparators
The main 1.5-MHz oscillator, and the I2C™ interface are only powered from VCC.
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DETAILED DESCRIPTION (continued)
VSYSIN
Vref
V_VSYSIN
priority
#1
VCC
VBACKUP
Vref
V_VBACKUP
priority
#2
V_VSYSIN
V_VBACKUP
EN
VRTC
LDO
priority
#3
VRTC
A.
V_VSYSIN, V_VBACKUP thresholds: falling = 2.55 V, rising = 2.65 V ±3%
B.
RESPWRON thresholds: falling = 2.4 V, rising = 2.52 V ±3%
RESPWRON
Figure 25.
STEP-DOWN CONVERTERS, VDCDC1, VDCDC2, and VDCDC3
The TPS65023 incorporates three synchronous step-down converters operating typically at 1.5 MHz fixed
frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the
converters automatically enter the power save mode (PSM), and operate with pulse frequency modulation
(PFM). The VDCDC1 converter is capable of delivering 1.5 A output current, the VDCDC2 converter is capable
of delivering 1.2 A and the VDCDC3 converter is capable of delivering up to 1 A.
The converter output voltages can be programmed via the DEFDCDC1, DEFDCDC2 and DEFDCDC3 pins. The
pins can either be connected to GND, VCC, or to a resistor divider between the output voltage and GND. The
VDCDC1 converter defaults to 1.2 V or 1.8 V depending on the DEFDCDC1 configuration pin. If DEFDCDC1 is
tied to ground, the default is 1.2 V. If it is tied to VCC, the default is 1.8 V. When the DEFDCDC1 pin is
connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC1 V. See the
application information section for more details. The core voltage can be reprogrammed via the serial interface
in the range of 0.8 V to 1.6 V with a programmable slew rate. The converter is forced into PWM operation whilst
any programmed voltage change is underway, whether the voltage is being increased or decreased. The
DEFCORE and DEFSLEW registers are used to program the output voltage and slew rate during voltage
transitions.
The VDCDC2 converter defaults to 1.8 V or 2.5 V depending on the DEFDCDC2 configuration pin. If
DEFDCDC2 is tied to ground, the default is 1.8 V. If it is tied to VCC, the default is 2.5 V. When the DEFDCDC2
pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC2 V.
The VDCDC3 converter defaults to 1.8 V or 3.3 V depending on the DEFDCDC3 configuration pin. If
DEFDCDC3 is tied to ground the default is 1.8 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC3
pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC3 V.
The step-down converter outputs (when enabled) are monitored by power good (PG) comparators, the outputs
of which are available via the serial interface. The outputs of the dc-dc converters can be optionally discharged
via on-chip 300-Ω resistors when the dc-dc converters are disabled.
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PRODUCT PREVIEW
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DETAILED DESCRIPTION (continued)
During PWM operation, the converters use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on. The inductor current ramps up until the comparator trips and the control logic turns off the switch. The
current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded. After the
adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on, and the
inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel
rectifier and turning on the P-channel switch.
The three dc-dc converters operate synchronized to each other with the VDCDC1 converter as the master. A
180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3
switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for
a typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7 V to 1.2 V, the
VDCDC2 converter from 3.7 V to 1.8 V, and the VDCDC3 converter from 3.7 V to 3.3 V. The phase of the three
converters can be changed using the CON_CTRL register.
POWER SAVE MODE OPERATION
PRODUCT PREVIEW
As the load current decreases, the converters enter the power save mode operation. During PSM, the
converters operate in a burst mode (PFM mode) with a frequency between 750 kHz and 1.5 MHz, nominal for
one burst cycle. However, the frequency between different burst cycles depends on the actual load current and
is typically far less than the switching frequency with a minimum quiescent current to maintain high efficiency.
In order to optimize the converter efficiency at light load, the average current is monitored and if in PWM mode
the inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM
is calculated as follows:
VINDCDC1
IPFMDCDC1 enter =
24 W
IPFMDCDC2 enter =
VINDCDC2
26 W
IPFMDCDC3 enter =
VINDCDC3
39 W
(1)
During the PSM the output voltage is monitored with a comparator, and by maximum skip burst width. As the
output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the converter
effectively delivers a constant current defined as follows.
VINDCDC1
IPFMDCDC1 leave =
18 W
IPFMDCDC2 leave =
VINDCDC2
20 W
IPFMDCDC3 leave =
VINDCDC3
29 W
(2)
If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the
other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output
voltage has again dropped below the threshold. The power save mode is exited, and the converter returns to
PWM mode if either of the following conditions are met:
1. the output voltage drops 2% below the nominal VO due to increasing load current
2. the PFM burst time exceeds 16 × 1/fs (10.67 µs typical).
22
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DETAILED DESCRIPTION (continued)
These control methods reduce the quiescent current to typically 14 µA per converter, and the switching activity
to a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal
output voltage at light load current results in a low output voltage ripple. The ripple depends on the comparator
delay and the size of the output capacitor. Increasing capacitor values makes the output ripple tend to zero. The
PSM is disabled through the I2C interface to force the individual converters to stay in fixed frequency PWM
mode.
LOW RIPPLE MODE
Setting Bit 3 in register CON-CTRL to 1 enables the low ripple mode for all of the dc-dc converters if operated in
PFM mode. For an output current less than approximately 10 mA, the output voltage ripple in PFM mode is
reduced, depending on the actual load current. The lower the actual output current on the converter, the lower
the output ripple voltage. For an output current above 10 mA, there is only minor difference in output voltage
ripple between PFM mode and low ripple PFM mode. As this feature also increases switching frequency, it is
used to keep the switching frequency above the audible range in PFM mode down to a low output current.
Each of the three converters has an internal soft start circuit that limits the inrush current during start-up. The
soft start is realized by using a very low current to initially charge the internal compensation capacitor. The soft
start time is typically 750 µs if the output voltage ramps from 5% to 95% of the final target value. If the output is
already precharged to some voltage when the converter is enabled, then this time is reduced proportionally.
There is a short delay of typically 170 µs between the converter being enabled and switching activity actually
starting. This is to allow the converter to bias itself properly, to recognize if the output is precharged, and if so to
prevent discharging of the output while the internal soft start ramp catches up with the output voltage.
100% DUTY CYCLE LOW DROPOUT OPERATION
The TPS65023 converters offer a low input to output voltage difference while still maintaining operation with the
use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly
useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage required to maintain dc regulation depends on the load
current and output voltage. It is calculated as:
Vin
min
+ Vout
min
) Iout max
ǒrDS(on) max ) RLǓ
(3)
with:
Ioutmax = maximum load current (Note: ripple current in the inductor is zero under these conditions)
rDS(on)max = maximum P-channel switch rDS(on)
RL = DC resistance of the inductor
Voutmin = nominal output voltage minus 2% tolerance limit
ACTIVE DISCHARGE WHEN DISABLED
When the VDCDC1, VDCDC2, and VDCDC3 converters are disabled, due to an UVLO, DCDC_EN or
OVERTEMP condition, it is possible to actively pull down the outputs. This feature is disabled per default and is
individually enabled via the CON_CTRL2 register in the serial interface. When this feature is enabled, the
VDCDC1, VDCDC2, and VDCDC3 outputs are discharged by a 300 Ω (typical) load which is active as long as
the converters are disabled.
POWER GOOD MONITORING
All three step-down converters and both the LDO1 and LDO2 linear regulators have power good comparators.
Each comparator indicates when the relevant output voltage has dropped 10% below its target value with 5%
hysteresis. The outputs of these comparators are available in the PGOODZ register via the serial interface. An
interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when
the converters are disabled and the relevant PGOODZ register bits indicate that power is good.
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PRODUCT PREVIEW
SOFT START
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DETAILED DESCRIPTION (continued)
LOW DROPOUT VOLTAGE REGULATORS
The low dropout voltage regulators are designed to operate well with low value ceramic input and output
capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of
300 mV at rated output current. Each LDO supports a current limit feature. Both LDOs are enabled by the
LDO_EN pin, both LDOs can be disabled or programmed via the serial interface using the REG_CTRL and
LDO_CTRL registers. The LDOs also have reverse conduction prevention. This allows the possibility to connect
external regulators in parallel in systems with a backup battery. The TPS65023 step-down and LDO voltage
regulators automatically power down when the VCC voltage drops below the UVLO threshold or when the
junction temperature rises above 160°C.
POWER GOOD MONITORING
Both the LDO1 and LDO2 linear regulators have power good comparators. Each comparator indicates when the
relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these
comparators are available in the PGOODZ register via the serial interface. An interrupt is generated when any
voltage rail drops below the 10% threshold. The comparators are disabled when the LDOs are disabled and the
relevant PGOODZ register bits indicate that power is good.
UNDERVOLTAGE LOCKOUT
PRODUCT PREVIEW
The undervoltage lockout circuit for the five regulators on the TPS65023 prevents the device from malfunctioning
at low-input voltages and from excessive discharge of the battery. It disables the converters and LDOs. The
UVLO circuit monitors the VCC pin, the threshold is set internally to 2.35 V with 5% (120 mV) hysteresis. Note
that when any of the dc-dc converters are running, there is an input current at the VCC pin, which is up to 3 mA
when all three converters are running in PWM mode. This current needs to be taken into consideration if an
external RC filter is used at the VCC pin to remove switching noise from the TPS65023 internal analog circuitry
supply.
POWER-UP SEQUENCING
The TPS65023 power-up sequencing is designed to be entirely flexible and customer driven. This is achieved by
providing separate enable pins for each switch-mode converter, and a common enable signal for the LDOs. The
relevant control pins are described in Table 2.
Table 2. Control Pins and Status Outputs for DC-DC Converters
PIN NAME
I/O
FUNCTION
DEFDCDC3
I
Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to
1.8 V, DEFDCDC3 = VCC defaults VDCDC3 to 3.3 V.
DEFDCDC2
I
Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to
1.8 V, DEFDCDC2 = VCC defaults VDCDC2 to 3.3 V.
DEFDCDC1
I
Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 1.2
V, DEFDCDC1 = VCC defaults VDCDC1 to 1.6 V.
DCDC3_EN
I
Set DCDC3_EN = 0 to disable and DCDC3_EN = 1 to enable the VDCDC3 converter
DCDC2_EN
I
Set DCDC2_EN = 0 to disable and DCDC2_EN = 1 to enable the VDCDC2 converter
DCDC1_EN
I
Set DCDC1_EN = 0 to disable and DCDC1_EN = 1 to enable the VDCDC1 converter
HOT_RESET
I
The HOT_RESET pin generates a reset (RESPWRON) for the processor.HOT_RESET does not alter any
TPS65023 settings except the output voltage of VDCDC1. Activating HOT_RESET sets the voltage of
VDCDC1 to its default value defined with the DEFDCDC1 pin. HOT_RESET is internally de-bounced by
the TPS65023.
RESPWRON
O
RESPWRON is held low when power is initially applied to the TPS65023. The VRTC voltage is monitored:
RESWPRON is low when VRTC < 2.4 V and remains low for a time defined by the external capacitor at
the TRESPWRON pin. RESPWRON can also be forced low by activation of the HOT_RESET pin.
TRESPWRON
I
Connect a capacitor here to define the RESET time at the RESPWRON pin (1 nF typically gives 100 ms).
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SYSTEM RESET + CONTROL SIGNALS
The RESPWRON signal can be used as a global reset for the application. It is an open drain output. The
RESPWRON signal is generated according to the power good comparator of VRTC, and remains low for
tnrespwron seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). tnrespwron is set by
an external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms. RESPWRON is also triggered by
the HOT_RESET input. This input is internally debounced, with a filter time of typically 30 ms.
The PWRFAIL and LOW_BAT signals are generated by two voltage detectors using the PWRFAIL_SNS and
LOWBAT_SNS input signals. Each input signal is compared to a 1 V threshold (falling edge) with 5% (50 mV)
hysteresis.
The DCDC1 converter is reset to its default output voltage defined by the DEFDCDC1 input, when HOT_RESET
is asserted. Other I2C registers are not affected. Generally, the DCDC1 converter is set to its default voltage with
one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage, undervoltage lockout
(UVLO) condition, or RESPWRON active.
DEFLDO1 and DEFLDO2
Table 3.
DEFLDO2
DEFLDO1
VLDO1
VLDO2
0
0
1.3 V
3.3 V
0
1
2.8 V
3.3 V
1
0
1.3 V
1.8 V
1
1
1.8 V
3.3 V
Interrupt Management and the INT Pin
The INT pin combines the outputs of the PGOOD comparators from each dc-dc converter and LDOs. The INT
pin is used as a POWER_OK pin indicating when all enabled supplies are in regulation. If the PGOODZ register
is read via the serial interface, any active bits are then blocked from the INT output pin.
Interrupts can be masked using the MASK register; default operation is not to mask any DCDC or LDO
interrupts since this provides the POWER_OK function.
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PRODUCT PREVIEW
These two pins are used to set the default output voltage of the two 200 mA LDOs. The digital value applied to
the pins is latched during power up and determines the initial output voltage according to Table 3. The voltage of
both LDOs can be changed during operation with the I2C interface as described in the interface description.
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TIMING DIAGRAMS
Figure 26. HOT_RESET Timing
VCC
2.35V
1.9V
1.2V
2.47V
1.9V
0.8V
PRODUCT PREVIEW
UVLO*
VRTC
2.52V
3.0V
2.4V
RESPWRON
tNRESPWRON
DCDCx_EN
Ramp within
800 μs
VO DCDCx
slope depending
on load
LDO_EN
VO LDOx
*... internal signal
VSYSIN=VBACKUP=GND;
VINLDO=VCC
Figure 27. Power-Up and Power-Down Timing
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VCC
tNRESPWRON
RESPWRON
DCDC3_EN
1.8V or 3.3V
VO DCDC3
ramp within 800μs
ramp within 800μs
VO DCDC2
PRODUCT PREVIEW
DCDC2_EN
1.8V or 2.5V
ramp within 800μs
DEFCORE
register
default value
set higher output voltage for DCDC1
GO bit
CON_CTRL2[7]
cleared automatically
DCDC1_EN
VO DCDC1
1.2V or 1.6V
ramp within 800μs
programmed
slew rate
slope depending
on load
ramp within
800us
Figure 28. DVS Timing
SERIAL INTERFACE
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to
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400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed
to new values depending on the instantaneous application requirements and charger status to be monitored.
Register contents remain intact as long as VCC remains above 2 V. The TPS65023 has a 7-bit address:
1001000, other addresses are available upon contact with the factory. Attempting to read data from the register
addresses not listed in this section results in FFh being read out.
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a
start condition and terminated with a stop condition. When addressed, the TPS65023 device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS65023 device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end
of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In
this case, the slave TPS65023 device must leave the data line high to enable the master to generate the stop
condition
DATA
PRODUCT PREVIEW
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 29. Bit Transfer on the Serial Interface
CE
DATA
CLK
S
P
START Condition
STOP Condition
Figure 30. START and STOP Conditions
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SCLK
SDAT
A6
A5
A0
A4
ACK
R/W
R5
R0
0
0
Start
R6
R7
ACK
D5
D6
D7
D0 ACK
0
0
Register Address
Slave Address
Stop
Data
Note: SLAVE = TPS65020
Figure 31. Serial i/f WRITE to TPS65023 Device
SDAT
A6
A0
R/W
ACK
0
0
R7
A6
ACK
A0
R/W
ACK
1
0
0
Register
Address
Slave Address
Start
R0
D0
D7
ACK
Slave
Drives
the Data
Slave Address
Stop
Master
Drives
ACK and Stop
Repeated
Start
Note: SLAVE = TPS65020
Figure 32. Serial i/f READ from TPS65023: Protocol A
SCLK
SDA
A6
A0
R/W
0
Start
Slave Address
ACK
R7
R0
0
0
Register
Address
A6
ACK
A0
R/W
1
Stop Start
ACK
D7
D0
ACK
0
Slave Address
Slave
Drives
the Data
Stop
Master
Drives
ACK and Stop
Note: SLAVE = TPS65020
Figure 33. Serial i/f READ from TPS65023: Protocol B
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PRODUCT PREVIEW
SCLK
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DATA
t(BUF)
th(STA)
t(LOW)
tf
tr
CLK
th(STA)
t(HIGH)
tsu(STA)
th(DATA)
STO
tsu(STO)
tsu(DATA)
STA
STA
Figure 34. Serial i/f Timing Diagram
PRODUCT PREVIEW
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STO
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MIN
MAX
UNIT
400
kHz
fMAX
Clock frequency
twH(HIGH)
Clock high time
600
twL(LOW)
Clock low time
1300
tR
DATA and CLK rise time
tF
DATA and CLK fall time
th(STA)
Hold time (repeated) START condition (after this period the first clock pulse is generated)
600
ns
th(DATA)
Setup time for repeated START condition
600
ns
th(DATA)
Data input hold time
0
ns
tsu(DATA)
Data input setup time
100
ns
tsu(STO)
STOP condition setup time
600
ns
t(BUF)
Bus free time
1300
ns
ns
ns
300
ns
300
ns
VERSION. Register Address: 00h (read only)
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
0
0
1
0
0
0
1
1
Read/Write
R
R
R
R
R
R
R
R
PRODUCT PREVIEW
VERSION
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PGOODZ. Register Address: 01h (read only)
PGOODZ
B7
Bit name and
function
PWRFAILZ
Set by signal
PWRFAIL
Default value
loaded by:
PWRFAILZ
Read/Write
Bit 7
Bit 6
Bit 5
PRODUCT PREVIEW
Bit 4
Bit 3
Bit 2
Bit 1
32
B6
B5
B4
B3
B2
B1
LOWBATTZ
PGOODZ
VDCDC1
PGOODZ
VDCDC2
PGOODZ
VDCDC3
PGOODZ
LDO2
PGOODZ
LDO1
LOWBATT
PGOODZ
VDCDC1
PGOODZ
VDCDC2
PGOODZ
VDCDC3
PGOODZ
LDO2
PGOODZ
LDO1
LOWBATTZ
PGOOD
VDCDC1
PGOOD
VDCDC2
PGOOD
VDCDC3
PGOOD
LDO2
PGOOD
LDO1
R
R
R
R
R
R
R
B0
R
PWRFAILZ:
0=
indicates that the PWRFAIL_SNS input voltage is above the 1-V threshold.
1=
indicates that the PWRFAIL_SNS input voltage is below the 1-V threshold.
LOWBATTZ:
0=
indicates that the LOWBATT_SNS input voltage is above the 1-V threshold.
1=
indicates that the LOWBATT_SNS input voltage is below the 1-V threshold.
PGOODZ VDCDC1:
0=
indicates that the VDCDC1 converter output voltage is within its nominal range. This bit is zero if
the VDCDC1 converter is disabled.
1=
indicates that the VDCDC1 converter output voltage is below its target regulation voltage
PGOODZ VDCDC2:
0=
indicates that the VDCDC2 converter output voltage is within its nominal range. This bit is zero if
the VDCDC2 converter is disabled.
1=
indicates that the VDCDC2 converter output voltage is below its target regulation voltage
PGOODZ VDCDC3: .
0=
indicates that the VDCDC3 converter output voltage is within its nominal range. This bit is zero if
the VDCDC3 converter is disabled and during a DVM controlled output voltage transition
1=
indicates that the VDCDC3 converter output voltage is below its target regulation voltage
PGOODZ LDO2:
0=
indicates that the LDO2 output voltage is within its nominal range. This bit is zero if LDO2 is
disabled.
1=
indicates that LDO2 output voltage is below its target regulation voltage
PGOODZ LDO1
0=
indicates that the LDO1 output voltage is within its nominal range. This bit is zero if LDO1 is
disabled.
1=
indicates that the LDO1 output voltage is below its target regulation voltage
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MASK. Register Address: 02h (read/write)
MASK
Bit name and
function
Default
Default value
loaded by:
Read/Write
Default Value: C0h
B7
B6
B5
B4
B3
B2
B1
MASK
PWRFAILZ
MASK
LOWBATTZ
MASK
VDCDC1
MASK
VDCDC2
MASK
VDCDC3
MASK
LDO2
MASK
LDO1
1
1
0
0
0
0
0
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
B0
0
The MASK register can be used to mask particular fault conditions from appearing at the INT pin. MASK<n> = 1
masks PGOODZ<n>.
REG_CTRL. Register Address: 03h (read/write)
Default Value: FFh
The REG_CTRL register is used to disable or enable the power supplies via the serial interface. The contents of
the register are logically AND’ed with the enable pins to determine the state of the supplies. A UVLO condition
resets the REG_CTRL to 0xFF, so the state of the supplies defaults to the state of the enable pin. The
REG_CTRL bits are automatically reset to default when the corresponding enable pin is low.
B7
B6
Bit name and
function
Default
1
Set by signal
Default value
loaded by:
Read/Write
Bit 5
1
B5
B4
B3
B2
B1
VDCDC1
ENABLE
VDCDC2
ENABLE
VDCDC3
ENABLE
LDO2
ENABLE
LDO1
ENABLE
1
1
1
DCDC1_ENZ DCDC2_ENZ DCDC3_ENZ
1
1
LDO_ENZ
LDO_ENZ
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
B0
1
VDCDC1 ENABLE
DCDC1 Enable. This bit is logically AND’ed with the state of the DCDC1_EN pin to turn on the DCDC1
converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The
bit is reset to 1 when the pin DCDC1_EN is pulled to GND, allowing DCDC1 to turn on when
DCDC1_EN returns high.
Bit 4
VDCDC2 ENABLE
DCDC2 Enable. This bit is logically AND’ed with the state of the DCDC2_EN pin to turn on the DCDC2
converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The
bit is reset to 1 when the pin DCDC2_EN is pulled to GND, allowing DCDC2 to turn on when
DCDC2_EN returns high.
Bit 3
VDCDC3 ENABLE
DCDC3 Enable. This bit is logically AND’ed with the state of the DCDC3_EN pin to turn on the DCDC3
converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The
bit is reset to 1 when the pin DCDC3_EN is pulled to GND, allowing DCDC3 to turn on when
DCDC3_EN returns high.
Bit 2
LDO2 ENABLE
LDO2 Enable. This bit is logically AND’ed with the state of the LDO2_EN pin to turn on LDO2. Reset to
1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when
the pin LDO_EN is pulled to GND, allowing LDO2 to turn on when LDO_EN returns high.
Bit 1
LDO1 ENABLE
LDO1 Enable. This bit is logically AND’ed with the state of the LDO1_EN pin to turn on LDO1. Reset to
1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when
the pin LDO_EN is pulled to GND, allowing LDO1 to turn on when LDO_EN returns high.
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REG_CTRL
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CON_CTRL. Register Address: 04h (read/write)
Default Value: B1h
CON_CTRL
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
DCDC2
PHASE1
DCDC2
PHASE0
DCDC3
PHASE1
DCDC3
PHASE0
LOW
RIPPLE
FPWM
DCDC2
FPWM
DCDC1
FPWM
DCDC3
1
0
1
1
0
0
0
0
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
Default value
loaded by:
Read/Write
The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when low
output voltage ripple is vital. It is also used to control the phase shift between the three converters in order to
minimize the input rms current, hence reduce the required input blocking capacitance. The DCDC1 converter is
taken as the reference and consequently has a fixed zero phase shift.
DCDC2 CONVERTER
DELAYED BY
CON_CTRL<5:4>
00
zero
00
zero
01
1/4 cycle
01
1/4 cycle
10
1/2 cycle
10
1/2 cycle
11
3/4 cycle
11
3/4 cycle
CON_CTRL<7:6>
PRODUCT PREVIEW
Bit 3
Bit 2
Bit 1
Bit 0
34
DCDC3 CONVERTER
DELAYED BY
LOW RIPPLE:
0=
PFM mode operation optimized for high efficiency for all converters
1=
PFM mode operation optimized for low output voltage ripple for all converters
FPWM DCDC2:
0=
DCDC2 converter operates in PWM / PFM mode
1=
DCDC2 converter is forced into fixed frequency PWM mode
FPWM DCDC1:
0=
DCDC1 converter operates in PWM / PFM mode
1=
DCDC1 converter is forced into fixed frequency PWM mode
FPWM DCDC3:
0=
DCDC3 converter operates in PWM / PFM mode
1=
DCDC3 converter is forced into fixed frequency PWM mode
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CON_CTRL2. Register Address: 05h (read/write)
CON_CTRL2
B7
B6
Bit name and
function
GO
Core adj
allowed
0
1
UVLO +
DONE
RESET(1)
R/W
R/W
Default
Default value
loaded by:
Read/Write
B5
0
Default Value: 40h
B4
B3
0
B2
B1
B0
DCDC2
discharge
DCDC1
discharge
DCDC3
discharge
0
0
0
UVLO
UVLO
UVLO
R/W
R/W
R/W
0
The CON_CTRL2 register can be used to take control the inductive converters.
RESET(1): CON_CTRL2[6] is reset to its default value by one of these events:
undervoltage lockout (UVLO)
HOT_RESET pulled low
RESPWRON active
VRTC below threshold
Bit 7
Bit 6
Bit 2– 0
GO:
0=
no change in the output voltage for the DCDC1 converter
1=
the output voltage of the DCDC1 converter is changed to the value defined in DEFCORE with
the slew rate defined in DEFSLEW. This bit is automatically cleared when the DVM transition is
complete. The transition is considered complete in this case when the desired output voltage
code has been reached, not when the VDCDC3 output voltage is actually in regulation at the
desired voltage.
CORE ADJ Allowed:
0=
the output voltage is set with the I2C register
1=
DEFDCDC1 is either connected to GND or VCC or an external voltage divider. When
connected to GND or VCC, VDCDC1 defaults to 1.2 V or 1.6 V respectively at start-up
0=
the output capacitor of the associated converter is not actively discharged when the converter
is disabled
1=
the output capacitor of the associated converter is actively discharged when the converter is
disabled. This decreases the fall time of the output voltage at light load
Submit Documentation Feedback
35
PRODUCT PREVIEW
•
•
•
•
TPS65023
www.ti.com
SLVS670A – JUNE 2006 – REVISED JUNE 2006
DEFCORE. Register Address: 06h (read/write
DEFCORE
B7
B6
Default Value: 14h/1Eh
B5
Bit name and
function
Default
0
0
B4
B3
B2
B1
B0
CORE4
CORE3
CORE2
CORE1
CORE0
1
DEFDCDC1
DEFDCDC1
DEFDCDC1
DEFDCDC1
RESET(1)
RESET(1)
RESET(1)
RESET(1)
RESET(1)
R/W
R/W
R/W
R/W
R/W
0
Default value
loaded by:
Read/Write
RESET(1): DEFCORE is reset to its default value by one of these events:
• undervoltage lockout (UVLO)
• HOT_RESET pulled low
• RESPWRON active
• VRTC below threshold
CORE4 CORE3
PRODUCT PREVIEW
CORE2
CORE1
CORE0
VDCDC1
CORE4
CORE3
CORE2
CORE1
CORE0
0
0
0
0
0
0.8 V
1
0
0
0
0
1.2 V
0
0
0
0
1
0.825 V
1
0
0
0
1
1.225 V
0
0
0
1
0
0.85 V
1
0
0
1
0
1.25 V
0
0
0
1
1
0.875 V
1
0
0
1
1
1.275 V
0
0
1
0
0
0.9 V
1
0
1
0
0
1.3 V
0
0
1
0
1
0.925 V
1
0
1
0
1
1.325 V
0
0
1
1
0
0.95 V
1
0
1
1
0
1.35 V
0
0
1
1
1
0.975 V
1
0
1
1
1
1.375 V
0
1
0
0
0
1V
1
1
0
0
0
1.4 V
0
1
0
0
1
1.025 V
1
1
0
0
1
1.425 V
0
1
0
1
0
1.05 V
1
1
0
1
0
1.45 V
0
1
0
1
1
1.075 V
1
1
0
1
1
1.475 V
0
1
1
0
0
1.1 V
1
1
1
0
0
1.5 V
0
1
1
0
1
1.125 V
1
1
1
0
1
1.525 V
0
1
1
1
0
1.15 V
1
1
1
1
0
1.55 V
0
1
1
1
1
1.175 V
1
1
1
1
1
1.6 V
DEFSLEW. Register Address: 07h (read/write)
DEFSLEW
B7
B6
Default Value: 06h
B5
B4
B3
Bit name and
function
B2
B1
B0
SLEW2
SLEW1
SLEW0
1
1
0
UVLO
UVLO
UVLO
R/W
R/W
R/W
Default
Default value
loaded by:
Read/Write
36
VDCDC1
SLEW2
SLEW1
SLEW0
VDCDC1 SLEW RATE
0
0
0
0.15 mV/µs
0
0
1
0.3 mV/µs
0
1
0
0.6 mV/µs
0
1
1
1.2 mV/µs
1
0
0
2.4 mV/µs
1
0
1
4.8 mV/µs
1
1
0
9.6 mV/µs
1
1
1
Immediate
Submit Documentation Feedback
TPS65023
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SLVS670A – JUNE 2006 – REVISED JUNE 2006
LDO_CTRL. Register Address: 08h (read/write)
LDO_CTRL
Bit name and
function
B7
B5
B4
LDO2_2
LDO2_1
LDO2_0
DEFLDOx
DEFLDOx
UVLO
R/W
RSVD
Default
Default Value: set with DEFLDO1 and DEFLDO2
B6
Default value
loaded by:
Read/Write
B3
B2
B1
B0
LDO1_2
LDO1_1
LDO1_0
DEFLDOx
DEFLDOx
DEFLDOx
DEFLDOx
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
RSVD
The LDO_CTRL registers can be used to set the output voltage of LDO1 and LDO2. LDO_CTRL[7] and
LDO_CTRL[3] are reserved and should always be written to 0.
The default voltage is set with DEFLDO1 and DEFLDO2 pins as described in Table 3.
LDO2_1
LDO2_0
LDO2 OUTPUT
VOLTAGE
LDO1_2
LDO1_1
LDO1_0
LDO1 OUTPUT
VOLTAGE
0
0
0
1.05 V
0
0
0
1V
0
0
1
1.2 V
0
0
1
1.1 V
0
1
0
1.3 V
0
1
0
1.3 V
0
1
1
1.8 V
0
1
1
1.8 V
1
0
0
2.5 V
1
0
0
2.2 V
1
0
1
2.8 V
1
0
1
2.6 V
1
1
0
3.0 V
1
1
0
2.8 V
1
1
1
3.3 V
1
1
1
3.15 V
DESIGN PROCEDURE
Inductor Selection for the DC-DC Converters
Each of the converters in the TPS65023 typically use a 3.3 µH output inductor. Larger or smaller inductor values
are used to optimize the performance of the device for specific operation conditions. The selected inductor has
to be rated for its dc resistance and saturation current. The dc resistance of the inductance influences directly
the efficiency of the converter. Therefore, an inductor with lowest dc resistance should be selected for highest
efficiency.
For a fast transient response, a 2.2-µH inductor in combination with a 22-µF output capacitor is recommended.
Equation 4 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 4. This is
needed because during heavy load transient the inductor current rises above the value calculated under
Equation 4.
1 * Vout
Vin
DI + Vout
L
L ƒ
(4)
I
Lmax
+ I outmax )
DI
L
2
(5)
with:
f = Switching Frequency (1.5 MHz typical)
L = Inductor Value
∆IL = Peak-to-Peak inductor ripple current
ILMAX = Maximum Inductor current
The highest inductor current occurs at maximum Vin.
Open core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents
versus a comparable shielded inductor.
Submit Documentation Feedback
37
PRODUCT PREVIEW
LDO2_2
TPS65023
www.ti.com
SLVS670A – JUNE 2006 – REVISED JUNE 2006
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
TPS65023 (2 A for the VDCDC1 and VDCDC2 converters, and 1.5 A for the VDCDC3 converter). The core
material from inductor to inductor differs and has an impact on the efficiency especially at high switching
frequencies.
See Table 4 and the typical applications for possible inductors.
Table 4. Tested Inductors
DEVICE
DCDC3 converter
DCDC2 converter
DCDC1 converter
INDUCTOR
VALUE
TYPE
COMPONENT SUPPLIER
3.3 µH
CDRH2D14NP-3R3
Sumida
3.3 µH
LPS3010-332
Coilcraft
3.3 µH
VLF4012AT-3R3M1R3
TDK
PRODUCT PREVIEW
2.2 µH
VLF4012AT-2R2M1R5
TDK
3.3 µH
CDRH2D18/HPNP-3R3
Sumida
3.3 µH
VLF4012AT-3R3M1R3
TDK
2.2 µH
VLCF4020-2R2
TDK
3.3 µH
CDRH3D14/HPNP-3R2
Sumida
3.3 µH
CDRH4D28C-3R2
Sumida
3.3 µH
MSS5131-332
Coilcraft
2.2 µH
VLCF4020-2R2
TDK
Output Capacitor Selection
The advanced Fast Response voltage mode control scheme of the inductive converters implemented in the
TPS65023 allow the use of small ceramic capacitors with a typical value of 10 µF for each converter without
having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low
ESR values have the lowest output voltage ripple and are recommended. See Table 5 for recommended
components.
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application
requirements. Just for completeness, the RMS ripple current is calculated as:
V
1 - out
Vin
1
x
IRMSCout = Vout x
L x ¦
2 x Ö3
(6)
At nominal load current, the inductive converters operate in PWM mode. The overall output voltage ripple is the
sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
V
1 - out
Vin
1
DVout = Vout x
x
+ ESR
L x ¦
8 x Cout x ¦
(
)
(7)
Where the highest output voltage ripple occurs at the highest input voltage Vin.
At light load currents, the converters operate in PSM and the output voltage ripple is dependent on the output
capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The
typical output voltage ripple is less than 1% of the nominal output voltage.
38
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TPS65023
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SLVS670A – JUNE 2006 – REVISED JUNE 2006
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. Each dc-dc converter requires a 10-µF ceramic input capacitor on its input pin VINDCDCx. The
input capacitor is increased without any limit for better input voltage filtering. The VCC pin is separated from the
input for the dc-dc converters. A filter resistor of up to 10R and a 1-µF capacitor is used for decoupling the VCC
pin from switching noise. Note that the filter resistor may affect the UVLO threshold since up to 3 mA can flow
via this resistor into the VCC pin when all converters are running in PWM mode.
Table 5. Possible Capacitors
CAPACITOR VALUE
CASE SIZE
COMPONENT SUPPLIER
COMMENTS
22 µF
22 µF
1206
TDK C3216X5R0J226M
Ceramic
1206
Taiyo Yuden JMK316BJ226ML
Ceramic
22 µF
0805
TDK C2012X5R0J226MT
Ceramic
22µF
0805
Taiyo Yuden JMK212BJ226MG
Ceramic
10 µF
0805
Taiyo Yuden JMK212BJ106M
Ceramic
10 µF
0805
TDK C2012X5R0J106M
Ceramic
The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down
converter. See Table 6 for the default voltages if the pins are pulled to GND or to VCC. If a different voltage is
needed, an external resistor divider can be added to the DEFDCDCx pin as shown in Figure 35.
The output voltage of VDCDC3 is set with the I2C interface. If the voltage is changed from the default, using the
DEFCORE register, the output voltage only depends on the register value. Any resistor divider at DEFDCDC3
does not change the voltage set with the register.
Table 6.
PIN
LEVEL
DEFAULT OUTPUT VOLTAGE
DEFDCDC1
DEFDCDC2
DEFDCDC3
VCC
1.6 V
GND
1.2 V
VCC
2.5 V
GND
1.8 V
VCC
3.3 V
GND
1.8 V
Using an external resistor divider at DEFDCDCx:
10 R
V(bat)
VCC
1 mF
VDCDC3
L3
VINDCDC3
CI
CO
DCDC3_EN
VO
L
R1
DEFDCDC3
R2
AGND
PGND
Figure 35. External Resistor Divider
Submit Documentation Feedback
39
PRODUCT PREVIEW
Output Voltage Selection
TPS65023
www.ti.com
SLVS670A – JUNE 2006 – REVISED JUNE 2006
When a resistor divider is connected to DEFDCDCx, the output voltage can be set from 0.6 V up to the input
voltage V(bat). The total resistance (R1+R2) of the voltage divider should be kept in the 1-MR range in order to
maintain a high efficiency at light load.
V(DEFDCDCx) = 0.6 V
R1 + R2
R2
VOUT = VDEFDCDCx x
R1 = R2 x
(
VOUT
VDEFDCDCx
)
- R2
(8)
VRTC Output
The VRTC output is typically connected to the Vcc_Batt pin of a Intel® PXA270 processor. During power-up of
the processor, the TPS65023 internally switches from the LDO or the backup battery to the system voltage
connected at the VSYSIN pin (see Figure 25). It is recommended that a 4.7-µF (minimum) capacitor be added to
the VRTC pin.
LDO1 and LDO2
PRODUCT PREVIEW
The LDOs in the TPS65023 are general-purpose LDOs which are stable using ceramics capacitors. The
minimum output capacitor required is 2.2 µF. The LDOs output voltage can be changed to different voltages
between 1 V and 3.3 V using the I2C interface. Therefore, they can also be used as general-purpose LDOs in
applications powering processors different from PXA270. The supply voltage for the LDOs needs to be
connected to the VINLDO pin, giving the flexibility to connect the lowest voltage available in the system and
provides the highest efficiency.
TRESPWRON
This is the input to a capacitor that defines the reset delay time after the voltage at VRTC rises above 2.52 V.
The timing is generated by charging and discharging the capacitor with a current of 2 µA between a threshold of
0.25 V and 1 V for 128 cycles. A 1-nF capacitor gives a delay time of 100 ms.
t(reset) = 2 x 128 x
(
(1 V - 0.25 V) x C(reset)
2 mA
)
(9)
Where:
t(reset) is the reset delay time
C(reset) is the capacitor connected to the TRESPWRON pin
VCC-Filter
An RC filter connected at the VCC input is used to keep noise from the internal supply for the bandgap and
other analog circuitry. A typical value of 10 R and 1 µF is used to filter the switching spikes, generated by the
dc-dc converters. A larger resistor than 10 R should not be used because the current into VCC of up to 3 mA
causes a voltage drop at the resistor causing the undervoltage lockout circuitry connected at VCC internally to
switch off too early.
40
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TPS65023
www.ti.com
SLVS670A – JUNE 2006 – REVISED JUNE 2006
APPLICATION INFORMATION
TYPICAL CONFIGURATION FOR THE Texas Instruments® TMS320DM644x DaVinci
PROCESSORS
V IN
DSP_EN
DaVinci
TMS320DM644x
10Ω
V
IN
CC
1μF
TPS65023
VINDCDC1
10μF
4.7kΩ
SCLK
SDA T
SDA T
VINDCDC2
INT
VINDCDC3
VDCDC1
10μF
10μF
4.7kΩ
SCLK
CVDDDSP
100kΩ
USB_VDD1P2LDO
CVDD
L1
2.2μH
VIN_LDO
APLLREFV
22μF
VDDA_1P1V
100kΩ
LOW_BA TT
PWRF AIL_SNS
VDCDC3
VDCDC2
DVD18
L2
DVDDR2
2.2μH
22μF
VDDA_1P8V
USB_VDD1P8
LOWBA T_SNS
M24VDD
HOT_RESET
LDO1
DDR_VDDDL
1nF
MXVDD
DEFLDO1
IN
1.8V
Domain
PLL VDD18
2.2μF
TRESPWRON
V
1.2V
Domain
PRODUCT PREVIEW
V
LDO2
2.2μF
DEFLDO2
LDO_EN
VDCDC3
VSYSIN
VBACKUP
1μF
USB_VDDA3P3
VDCDC3
DVDD33
L3
2.2μH
VR TC
22μF
PWRF AIL
4.7μF
100kΩ
EN
V IN
100kΩ
DCDC2_EN
3.3V
Domain
100kΩ
RESPWRON
DCDC1_EN
AGND1
DCDC3_EN
AGND2
DEFDCDC3
PGND1
DEFDCDC2
PGND2
DEFDCDC1
PGND3
Submit Documentation Feedback
41
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS65023RSBR
PREVIEW
QFN
RSB
40
3000
TBD
Call TI
Call TI
TPS65023RSBT
PREVIEW
QFN
RSB
40
250
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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to Customer on an annual basis.
Addendum-Page 1
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