MACH 1 & 2 FAMILIES 1 FINAL COM’L: -7/10/12/15 IND: -10/12/14/18 MACH 1 & 2 Families MACH211SP-7/10/12/15 High-Performance EE CMOS In-System Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ JTAG-Compatible, 5-V in-system programming ◆ 44 Pins in PLCC and TQFP ◆ 64 Macrocells ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 7.5 ns tPD Commercial, 10 ns tPD Industrial 133 MHz fCNT 32 I/Os; 2 dedicated inputs/clocks 64 Flip-flops; 2 clock choices 4 “PALCE26V16” blocks with buried macrocells Speed Locking™ for guaranteed fixed timing Bus-Friendly™ Inputs and I/Os Peripheral Component Interconnect (PCI) compliant (-7/-10/-12) Programmable power-down mode IN-SYSTEM PROGRAMMING In-system programming allows the MACH211SP to be programmed while soldered onto a system board. Programming the MACH211SP in-system yields numerous benefits at all stages of development: prototyping, manufacturing, and in the field. Since insertion into a programmer isn’t needed, multiple handling steps and the resulting bent leads are eliminated. The design can be modified in-system for design changes and debugging while prototyping, programming boards in production, and field upgrades. The MACH211SP offers advantages with in-system programming. MACH® devices have extensive routing resources for pin-out retention; design changes resulting in pin-out changes for many non-Vantis CPLDs cancel the advantages of in-system programming. The MACH211SP can be deployed in any JTAG (IEEE 1149.1) compliant chain. GENERAL DESCRIPTION The MACH211SP is a member of Vantis’ high-performance EE CMOS MACH 1 & 2 families. This device has approximately six times the logic macrocell capability of the popular PALCE22V10 without loss of speed. The MACH211SP consists of four PAL® blocks interconnected by a programmable switch matrix. The four PAL blocks are essentially “PALCE26V16” structures complete with product-term arrays and programmable macrocells, which can be programmed as high speed or low power, and buried macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, Publication# 20405 Amendment/0 Rev: C Issue Date: August 1997 1 V A N T I S providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH211SP has two kinds of macrocell: output and buried. The MACH211SP output macrocell provides registered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. The MACH211SP has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers or latches for use in synchronizing signals and reducing setup time requirements. The MACH211SP is an enhanced version of the MACH211, adding the JTAG-compatible in-system programming feature. Vantis offers software design support for MACH devices through its own development system and device fitters integrated into third-party CAE tools. Platform support extends across PCs, Sun and HP workstations under advanced operating systems such as Windows 3.1, Windows 95 and NT, SunOS and Solaris, and HPUX. MACHXL® software is a complete development system for the PC, supporting Vantis' MACH devices. It supports design entry with Boolean and behavioral syntax, state machine syntax and truth tables. Functional simulation and static timing analysis are also included in this easy-to-use system. This development system includes high-performance device fitters for all MACH devices. The same fitter technology included in MACHXL software is seamlessly incorporated into third-party tools from leading CAE vendors such as Synario, Viewlogic, Mentor Graphics, Cadence and MINC. Interface kits and MACHXL configurations are also available to support design entry and verification with other leading vendors such as Synopsys, Exemplar, OrCAD, Synplicity and Model Technology. These MACHXL configurations and interfaces accept EDIF 2.0.0 netlists, generate JEDEC files for MACH devices, and create industry-standard SDF, VITAL-compliant VHDL and Verilog output files for design simulation. Vantis offers in-system programming support for MACH devices through its MACHPRO® software enabling MACH device programmability through JTAG compliant ports and easy-to-use PC interface. Additionally, MACHPRO generated vectors work seamlessly with HP3070, GenRad and Teradyne testers to program MACH devices or test them for connectivity. All MACH devices are supported by industry standard programmers available from a number of vendors. These programmer vendors include Advin Systems, BP Microsystems, Data I/O Corporation, Hi-Lo Systems, SMS GmbH, Stag House, and System General. 2 MACH211SP-7/10/12/15 V A N T I S MACH 1 & 2 Families BLOCK DIAGRAM Block B Block A I/O0–I/O7 I/O8–I/O15 8 I/O Cells 8 I/O Cells 8 8 8 Macrocells Macrocells 8 8 8 2 Macrocells Macrocells 2 2 OE 52 x 68 AND Logic Array and Logic Allocator OE 52 x 68 AND Logic Array and Logic Allocator 26 26 Switch Matrix 26 26 52 x 68 AND Logic Array and Logic Allocator OE 2 Macrocells 8 8 Macrocells 8 I/O Cells 52 x 68 AND Logic Array and Logic Allocator OE 2 Macrocells 8 8 Macrocells 8 2 2 I/O Cells 8 8 I/O24–I/O31 I/O16–I/O23 Block D CLK0/I0 CLK1/I1 Block C MACH211SP-7/10/12/15 20405C-1 3 V A N T I S CONNECTION DIAGRAM Top View 44-Pin PLCC 3 2 I/O28 I/O29 I/O30 I/O31 VCC GND 5 4 I/O0 6 I/O1 I/O2 I/O3 Block D I/O4 Block A 1 44 43 42 41 40 I/O5 7 39 I/O27 I/O6 8 38 I/O26 I/O7 9 37 I/O25 TDI 10 36 I/O24 CLK0/I0 11 35 TDO GND 12 34 GND TCK 13 33 CLK1/I1 I/O8 14 32 TMS I/O9 15 31 I/O23 I/O10 16 30 I/O22 17 29 I/O21 I/O11 Block B I/O20 I/O19 I/O18 I/O17 GND I/O16 VCC I/O15 I/O14 I/O13 I/O12 18 19 20 21 22 23 24 25 26 27 28 Block C 20405C-2 PIN DESIGNATIONS CLK/I = Clock or Input TDI = Test Data In GND = Ground TCK = Test Clock I = Input TMS = Test Mode Select I/O = Input/Output TDO = Test Data Out VCC = Supply Voltage 4 MACH211SP-7/10/12/15 V A N T I S MACH 1 & 2 Families CONNECTION DIAGRAM Top View 44-Pin TQFP Block D 44 43 42 41 40 39 38 37 36 35 34 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 Block A 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 I/O27 I/O26 I/O25 I/O24 TDO GND CLK1/I1 TMS I/O23 I/O22 I/O21 I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 12 13 14 15 16 17 18 19 20 21 22 I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 I/O9 I/O10 I/O11 Block B Block C 20405C-3 PIN DESIGNATIONS CLK/I = Clock or Input TDI = Test Data In GND = Ground TCK = Test Clock I = Input TMS = Test Mode Select I/O = Input/Output TDO = Test Data Out VCC = Supply Voltage MACH211SP-7/10/12/15 5 V A N T I S ORDERING INFORMATION Commercial Products Vantis programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 211 SP -7 J C FAMILY TYPE MACH = Macro Array CMOS High-Speed OPERATING CONDITIONS C = Commercial (0°C to +70°C) DEVICE NUMBER 211 = 64 Macrocells, 44 Pins, Power-Down mode, Bus-Friendly Inputs and I/Os PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) V = 44-Pin Thin Quad Flat Pack (PQT044) PRODUCT DESIGNATION SP = In-system Programmable SPEED -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD Valid Combinations Valid Combinations MACH211SP-7 MACH211SP-10 JC, VC The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confir m availability of specific valid combinations and to check on newly released combinations. MACH211SP-12 MACH211SP-15 6 MACH211SP-7/10/12/15 (Com’l) V A N T I S Industrial Products Vantis programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 211 SP -10 J I FAMILY TYPE MACH = Macro Array CMOS High-Speed OPERATING CONDITIONS I = Industrial (–40°C to +85°C) DEVICE NUMBER 11 = 64 Macrocells, 44 Pins, Power-Down mode, Bus-Friendly Inputs and I/Os PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) PRODUCT DESIGNATION P = In-system Programmable SPEED -10 = 10 -12 = 12 -14 = 14 -18 = 18 ns ns ns ns tPD tPD tPD tPD Valid Combinations Valid Combinations MACH211SP-10 MACH211SP-12 JI The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confir m availability of specific valid combinations and to check on newly released combinations. MACH211SP-14 MACH211SP-18 MACH211SP-10/12/14/18 (Ind) 7 MACH 1 & 2 Families ORDERING INFORMATION V A N T I S FUNCTIONAL DESCRIPTION The MACH211SP consists of four PAL blocks connected by a switch matrix. There are 32 I/O pins feeding the switch matrix. These signals are distributed to the four PAL blocks for efficient design implementation. There are two clock pins that can also be used as dedicated inputs. The PAL Blocks Each PAL block in the MACH211SP (Figure 1) contains a 64-product-term logic array, a logic allocator, 8 output macrocells, 8 buried macrocells, and 8 I/O cells. The switch matrix feeds each PAL block with 26 inputs. This makes the PAL block look effectively like an independent “PALCE26V16” with 8 buried macrocells. In addition to the logic product terms, two output enable product terms, an asynchronous reset product term, and an asynchronous preset product term are provided. One of the two output enable product terms can be chosen within each I/O cell in the PAL block. All flip-flops within the PAL block are initialized together. The Switch Matrix The MACH211SP switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each PAL block provides 16 internal feedback signals and 8 I/O feedback signals. The switch matrix distributes these signals back to the PAL blocks in an efficient manner that also provides for high performance. The design software automatically configures the switch matrix when fitting a design into the device. The Product-term Array The MACH211SP product-term array consists of 64 product terms for logic use, and 4 special-purpose product terms. Two of the special-purpose product terms provide programmable output enable; one provides asynchronous reset, and one provides asynchronous preset. The Logic Allocator The logic allocator in the MACH211SP takes the 64 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven by up to 16 product terms. The design software automatically configures the logic allocator when fitting the design into the device. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers. Table 1. Macrocell Output Buried M0 M1 M2 M3 M5 C0, C1, C2 M8 C0, C1, C2, C3 Buried M9 M11 M13 MACH211SP-7/10/12/15 C10, C11, C12, C13 C11, C12, C13, C14 M14 C6, C7, C8, C9 C8, C9, C10, C11 C9, C10, C11, C12 M12 C4, C5, C6, C7 Available Clusters C7, C8, C9, C10 M10 C2, C3, C4, C5 C5, C6, C7, C8 M7 8 Output C3, C4, C5, C6 M6 Macrocell Available Clusters C1, C2, C3, C4 M4 Logic Allocation C12, C13, C14, C15 C13, C14, C15 M15 C14, C15 V A N T I S The MACH211SP has two types of macrocell: output and buried. The output macrocells can be configured as either registered, latched, or combinatorial, with programmable polarity. The macrocell provides internal feedback whether configured with or without the flip-flop. The registers can be configured as D-type or T-type, allowing for product-term optimization. The flip-flops can individually select one of two clock/gate pins, which are also available as data inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The latch holds its data when the gate input is HIGH, and is transparent when the gate input is LOW. The flip-flops can also be asynchronously initialized with the common asynchronous reset and preset product terms. The buried macrocells are the same as the output macrocells if they are used for generating logic. In that case, the only thing that distinguishes them from the output macrocells is the fact that there is no I/O cell connection, and the signal is only used internally. The buried macrocell can also be configured as an input register or latch. The I/O Cell The I/O cell in the MACH211SP consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to all I/O cells in a PAL block. These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus. SpeedLocking for Guaranteed Fixed Timing The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in both raw speed, but even more importantly, guaranteed fixed speed. Using the design of the central switch matrix, the MACH211SP product offers the SpeedLocking feature, which allows a stable fixed pin-to-pin delay, independent of logic paths, routing resources and design refits for up to 16 product terms per output. Other non-Vantis CPLDs incur serious timing delays as product terms expand beyond their typical 4 or 5 product-term limits. Speed and SpeedLocking combine for continuous, high performance required in today's demanding designs. In-System Programming Programming is the process where MACH devices are loaded with a pattern defined in a JEDEC file obtained from MACHXL software or third-party software. Programming is accomplished through four JTAG pins: Test Mode Select (TMS), Test Clock (TCK), Test Data In (TDI), and Test Data Out (TDO). The MACH211SP can be deployed in any JTAG (IEEE 1149.1) compliant chain. While the MACH211SP is fully JTAG compatible, it supports the BYPASS instruction, not the EXTEST and SAMPLE/PRELOAD instructions. The MACH211SP can be programmed across the commercial temperature range. Programming the MACH device after it has been placed on a circuit board is easily accomplished. Programming is initiated by placing the device into programming mode, using the MACHPRO programming software provided by Vantis. The device is bulk erased and the JEDEC file is then loaded. After the data is transferred into the device, the PROGRAM instruction is loaded. MACH211SP-7/10/12/15 9 MACH 1 & 2 Families The Macrocell V A N T I S Bus-Friendly Inputs and I/Os The MACH211SP inputs and I/Os include two inverters in series which loop back to the input. This double inversion reinforces the state of the input and pulls the voltage away from the input threshold voltage. Unlike a pull-up, this configuration cannot cause contention on a bus. For an illustration of this configuration, please turn to the Input/Output Equivalent Schematics section. PCI Compliant The MACH211SP-7/10/12 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The MACH211SP-7/10/12’s predictable timing ensures compliance with the PCI AC specifications independent of the design. Power-Down Mode The MACH211SP features a programmable low-power mode in which individual signal paths can be programmed as low power. These low-power speed paths will be slightly slower than the non-low-power paths. This feature allows speed critical paths to run at maximum frequency while the rest of the paths operate in the low-power mode, resulting in power savings of up to 75%. If all signals in a PAL block are low-power, then total power is reduced further. On-Board Programming Options Since the MACHPRO software performs these steps automatically, the following programming options are published for reference. The configuration file, which is also known as the chain file, defines the MACH device JTAG chain. The file contains the information concerning which JEDEC file is to be placed into which device, the state which the outputs should be placed, and whether the security fuses should be programmed. The configuration file is discussed in detail in the MACHPRO software manual. The MACH211SP devices tristate the outputs during programming. They have one security bit which inhibits program and verify. This allows the user to protect proprietary patterns and designs. Program verification of a MACH device involves reading back the programmed pattern and comparing it with the original JEDEC file. The Vantis method of program verification performed on the MACH devices permits the verification of one device at a time. Accidental Programming or Erasure Protection It is virtually impossible to program or erase a MACH device inadvertently. The following conditions must be met before programming actually takes place: ◆ The device must be in the password-protected program mode ◆ The programming or bulk erase instruction must be in the instruction register If the above conditions are not met, the programming circuitry cannot be activated. 10 MACH211SP-7/10/12/15 V A N T I S 4 8 12 16 20 24 28 32 36 40 43 47 51 Output Enable Output Enable Asynchronous Reset Asynchronous Preset Output Macro Cell M0 I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O Buried Macro Cell M1 Output Macro Cell M2 Buried Macro Cell M3 0 C0 I/O Cell Output Macro Cell M4 C1 C2 Buried Macro Cell M5 C3 C5 C6 Switch Matrix C7 C8 Logic Allocator C4 C9 Output Macro Cell M6 Buried Macro Cell M7 Output Macro Cell M8 C10 C11 Buried Macro Cell M9 C12 C13 Output Macro Cell M10 C14 C15 63 Buried Macro Cell M11 Output Macro Cell M12 Buried Macro Cell M13 Output Macro Cell M15 Buried Macro Cell CLK M14 2 0 4 8 12 16 20 24 28 32 36 40 43 47 51 16 8 20405C-4 Figure 1. MACH211SP PAL Block MACH211SP-7/10/12/15 11 MACH 1 & 2 Families 0 V A N T I S ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0°C to +70°C Device Junction Temperature . . . . . . . . . . . . . +150°C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V Supply Voltage with Respect to Ground . . . . . . . . . . . . . . –0.5 V to +7.0 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Input Voltage . . . . . . . . . . . .–0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to 70°C) . . . . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. DC CHARACTERISTICS over COMMERCIAL operating ranges Parameter Symbol Parameter Description Test Conditions Min 2.4 Typ Max Unit 3.3 V 0.5 V VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL VOL Output LOW Voltage IOL = 16 mA, VCC = Min, VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Current VIN = 0 V, VCC = Max (Note 2) –10 µA 2.0 V IOZH Off-State Output Leakage Current VOUT = 5.25 V, VCC = Max HIGH VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current VOUT = 0 V, VCC = Max LOW VIN = VIH or VIL (Note 2) –10 µA –160 mA ISC ICC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 Supply Current (Static) VCC = 5 V, TA = 25°C, f = 0 MHz (Note 4) 40 mA Supply Current (Active) VCC = 5 V, TA = 25°C, f = 1 MHz (Note 4) 45 mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled and reset. 12 MACH211SP-7/10/12/15 (Com’l) V A N T I S Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Unit Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25°C 6 pF Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) -7 Parameter Symbol Parameter Description tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) tS Setup Time from Input, I/O, or Feedback D-type to Clock (Note 3) T-type tH Register Data Hold Time tCO Clock to Output (Note 3) tWL Max Min 7.5 -12 Max Min 10 -15 Max Min 12 Max Unit 15 ns 5.5 6.5 7 10 ns 6.5 7.5 8 11 ns 0 0 0 0 ns 4.5 6 8 10 ns LOW 3 5 6 6 ns HIGH 3 5 6 6 ns D-type 100 80 66.7 50 MHz T-type 91 74 62.5 47.6 MHz D-type 133 100 83.3 66.6 MHz T-type 125 91 76.9 62.5 MHz 166.7 100 83.3 83.3 MHz 5.5 6.5 7 10 ns 0 0 0 0 ns Clock Width tWH External Feedback fMAX Min -10 Maximum Frequency (Note 1) 1/(tS + tCO) Internal Feedback (fCNT) No Feedback 1/(tWL + tWH) tSL Setup Time from Input, I/O, or Feedback to Gate tHL Latch Data Hold Time tGO Gate to Output tGWL Gate Width LOW tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch tSIR Input Register Setup Time 2 2 2 2 ns tHIR Input Register Hold Time 2 2 2 2.5 ns tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup tWICL 7 3 5 9.5 10 6 12 11 11 6 14 13 ns 17 15 ns 18 ns ns D-type 9 10 12 15 ns T-type 10 11 13 16 ns LOW 3 5 6 6 ns HIGH 3 5 6 6 ns 166.7 100 83.3 83.3 MHz Input Register Clock Width tWICH fMAXIR 7 Maximum Input Register Frequency tSIL Input Latch Setup Time 2 2 2 2 ns tHIL Input Latch Hold Time 2 2 2 2.5 ns tIGO Input Latch Gate to Combinatorial Output 12 MACH211SP-7/10/12/15 (Com’l) 14 17 20 ns 13 MACH 1 & 2 Families CAPACITANCE (Note 1) V A N T I S SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) -7 -10 -12 -15 Parameter Symbol Parameter Description tIGOL Input Latch Gate to Output Through Transparent Output Latch tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 7.5 8.5 9 12 ns tIGS Input Latch Gate to Output Latch Setup 10 11 13 16 ns tWIGL Input Latch Gate Width LOW 3 5 6 6 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 12.5 14 16 19 ns Asynchronous Reset to Registered or Latched Output 9.5 15 16 20 ns tAR Min Max Min 14 Max Min 16 Max Min 19 Max Unit 22 ns tARW Asynchronous Reset Width (Note 1) 5 10 12 15 ns tARR Asynchronous Reset Recovery Time (Note 1) 5 10 8 10 ns tAP Asynchronous Preset to Registered or Latched Output 9.5 15 16 20 ns tAPW Asynchronous Preset Width (Note 1) 5 10 12 15 ns tAPR Asynchronous Preset Recovery Time (Note 1) 5 10 8 10 ns tEA Input, I/O, or Feedback to Output Enable (Note 1) 9.5 12 15 15 ns tER Input, I/O, or Feedback to Output Disable (Note 1) 9.5 12 15 15 ns tLP tPD Increase for Powered-down Macrocell (Note 3) 10 10 10 10 ns tLPS tS Increase for Powered-down Macrocell (Note 3) 10 10 10 10 ns tLPCO tCO Increase for Powered-down Macrocell (Note 3) 0 0 0 0 ns tLPEA tEA Increase for Powered-down Macrocell (Note 3) 10 10 10 10 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter. 14 MACH211SP-7/10/12/15 (Com’l) V A N T I S OPERATING RANGES Storage Temperature . . . . . . . . . . . . . –65°C to +150°C Industrial (I) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . –40°C to +85°C Device Junction Temperature . . . . . . . . . . . . . +150°C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V Supply Voltage with Respect to Ground . . . . . . . . . . . . . . –0.5 V to +7.0 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Input Voltage . . . . . . . . . . . .–0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = –40°C to +85°C) . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. DC CHARACTERISTICS over INDUSTRIAL operating ranges Parameter Symbol Parameter Description Test Conditions Min 2.4 Typ Max Unit 3.3 V 0.5 V VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL VOL Output LOW Voltage IOL = 16 mA, VCC = Min, VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –10 µA 2.0 V IOZH Off-State Output Leakage Current VOUT = 5.25 V, VCC = Max HIGH VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current VOUT = 0 V, VCC = Max LOW VIN = VIH or VIL (Note 2) –10 µA –160 mA ISC ICC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 Supply Current (Static) VCC = 5 V, TA = 25°C, f = 0 MHz (Note 4) 40 mA Supply Current (Active) VCC = 5 V, TA = 25°C, f = 1 MHz (Note 4) 45 mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled and reset. MACH211SP-10/12/14/18 (Ind) 15 MACH 1 & 2 Families ABSOLUTE MAXIMUM RATINGS V A N T I S CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Unit Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25°C 6 pF Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) -10 Parameter Symbol Parameter Description tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) tS Setup Time from Input, I/O, or Feedback to Clock tH Register Data Hold Time tCO Clock to Output (Note 3) tWL Min 10 -14 Max Min 12 -18 Max Min 14 Max Unit 18 ns D-type 6.5 8 8.5 12 ns T-type 7.5 9 10 13.5 ns 0 0 0 0 ns 7.5 10 12 ns LOW 5 6 7.5 7.5 ns HIGH 5 6 7.5 7.5 ns D-type 80 64 53 40 MHz T-type 74 59 50 38 MHz D-type 100 80 61.5 53 MHz T-type 91 72.5 57 44 MHz 100 80 66.5 66.5 MHz 6.5 8 8.5 12 ns 0 0 0 0 ns Clock Width External Feedback Maximum Frequency (Note 1) 1/(tS + tCO) Internal Feedback (fCNT) No Feedback 1/(tWL + tWH) tSL Setup Time from Input, I/O, or Feedback to Gate tHL Latch Data Hold Time tGO Gate to Output tGWL Gate Width LOW tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch tSIR Input Register Setup Time 2 2.5 2.5 2.5 ns tHIR Input Register Hold Time 2 3 3 3.5 ns tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register D-type Setup T-type tWICL 8 5 8.5 6 12 12 7.5 14.5 13 13.5 7.5 17 16 ns 20.5 18 ns 22 ns ns 10 12 14.5 18 ns 11 13 16 19.5 ns LOW 5 6 7.5 7.5 ns HIGH 5 6 7.5 7.5 ns 100 80 66.5 66.5 MHz 2 2.5 2.5 2.5 ns Input Register Clock Width tWICH 16 Max 6 tWH fMAX Min -12 fMAXIR Maximum Input Register Frequency tSIL Input Latch Setup Time 1/(tWICL + tWICH) MACH211SP-10/12/14/18 (Ind) V A N T I S Parameter Symbol -10 Parameter Description Min -12 Max 2 Min -14 Max 3 Min -18 Max 3 Min Max 3.5 Unit tHIL Input Latch Hold Time ns tIGO Input Latch Gate to Combinatorial Output 14 17 20.5 24 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 16 19.5 23 26.5 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 8.5 10.5 11 14.5 ns tIGS Input Latch Gate to Output Latch Setup 11 13.5 16 19.5 ns tWIGL Input Latch Gate Width LOW 5 6 7.5 7.5 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 14 17 19.5 23 ns Asynchronous Reset to Registered or Latched Output 15 19.5 19.5 24 ns tAR tARW Asynchronous Reset Width (Note 1) 10 12 14.5 18 ns tARR Asynchronous Reset Recovery Time (Note 1) 10 10 10 12 ns tAP Asynchronous Preset to Registered or Latched Output 15 18 19.5 24 ns tAPW Asynchronous Preset Width (Note 1) 10 12 14.5 18 ns tAPR Asynchronous Preset Recovery Time (Note 1) 10 10 10 12 ns tEA Input, I/O, or Feedback to Output Enable (Note 1) 15 15 14.5 18 ns tER Input, I/O, or Feedback to Output Disable (Note 1) 15 15 14.5 18 ns tLP tPD Increase for Powered-down Macrocell (Note 3) 10 10 10 10 ns tLPS tS Increase for Powered-down Macrocell (Note 3) 10 10 10 10 ns tLPCO tCO Increase for Powered-down Macrocell (Note 3) 0 0 0 0 ns tLPEA tEA Increase for Powered-down Macrocell (Note 3) 10 10 10 10 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit for test conditions. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter. MACH211SP-10/12/14/18 (Ind) 17 MACH 1 & 2 Families SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) V A N T I S TYPICAL CURRENT vs. VOLTAGE (I-V) CHARACTERISTICS VCC = 5.0 V, TA = 25°C IOL (mA) 80 60 40 20 VOL (V) -1.0 -0.8 -0.6 -0.4 -0.2 -20 .2 .4 .6 .8 1.0 -40 -60 -80 Output, LOW 20405C-5 IOH (mA) 25 1 2 3 4 5 VOH (V) -3 -2 -1 -25 -50 -75 -100 -125 -150 Output, HIGH 20405C-6 II (mA) 20 VI (V) -2 -1 -20 1 2 3 4 5 -40 -60 -80 -100 Input 18 MACH211SP-7/10/12/15 20405C-7 V A N T I S MACH 1 & 2 Families TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25°C High Speed 150 125 Low Power ICC (mA) 100 75 50 25 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Frequency (MHz) 20405C-8 The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. MACH211SP-7/10/12/15 19 V A N T I S TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Typ Parameter Symbol Parameter Description θjc Thermal impedance, junction to case θja Thermal impedance, junction to ambient θjma TQFP PLCC 11 Thermal impedance, junction to ambient with air flow 4 Unit °C/W 41 30 °C/W 200 lfpm air 35 19 °C/W 400 lfpm air 34 16 °C/W 600 lfpm air 33 14 °C/W 800 lfpm air 32 13 °C/W Plastic θjc Considerations The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. The thermal measurements are taken with components on a six-layer printed circuit board. SWITCHING WAVEFORMS Input, I/O, or Feedback VT tPD Combinatorial Output VT 20405C-9 Combinatorial Output Input, I/O, or Feedback Input, I/O, or Feedback VT tS tH tSL tCO Registered Output tHL Gate VT Clock VT VT tPDL VT tGO Latched Out VT 20405C-10 Registered Output Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. 20 20405C-11 Latched Output MACH211SP-7/10/12/15 V A N T I S MACH 1 & 2 Families SWITCHING WAVEFORMS tWH Gate Clock VT tGWL tWL 20405C-12 20405C-13 Clock Width Gate Width Registered Input Registered Input VT tSIR Input Register Clock tHIR Input Register Clock VT tICO Combinatorial Output VT VT VT Output Register Clock tICS 20405C-14 VT 20405C-15 Registered Input Input Register to Output Register Setup Latched In VT tSIL tHIL VT Gate tIGO Combinatorial Output VT 20405C-16 Latched Input Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. MACH211SP-7/10/12/15 21 V A N T I S SWITCHING WAVEFORMS tPDLL Latched In VT Latched Out VT tIGOL Input Latch Gate tSLL tIGS VT Output Latch Gate 20405C-17 Latched Input and Output tWICH Clock VT tWICL Input Latch Gate VT tWIGL 20405C-18 Input Register Clock Width Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. 22 20405C-19 Input Latch Gate Width MACH211SP-7/10/12/15 V A N T I S tARW MACH 1 & 2 Families SWITCHING WAVEFORMS tAPW Input, I/O, or Feedback Input, I/O, or Feedback VT VT tAP tAR Registered Output or Latched Output Registered Output or Latched Output VT tARR Clock or Input Latch Gate VT VT tAPR Clock or Input Latch Gate VT 20405C-20 20405C-21 Asynchronous Reset Asynchronous Preset Input, I/O, or Feedback VT tER Outputs tEA VOH – 0.5 V VOL + 0.5 V VT 20405C-22 Output Disable/Enable Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. MACH211SP-7/10/12/15 23 V A N T I S KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING TEST CIRCUIT* 5V S1 R1 Output Test Point R2 CL 20405C-23 Commercial Specification tPD, tCO tEA tER S1 CL R1 R2 Closed Z → H: Open 35 pF Z → L: Closed H → Z: Open L → Z: Closed 1.5 V 300 Ω 390 Ω 5 pF * Switching several outputs simultaneously should be avoided for accurate measurement. 24 Measured Output Value MACH211SP-7/10/12/15 H → Z: VOH – 0.5 V L → Z: VOL + 0.5 V V A N T I S The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated “fMAX external.” The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is designated “fMAX internal”. A simple internal counter is a good example of this type of design; therefore, this parameter is sometimes called “fCNT.” The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (tS + tH). However, a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third fMAX, designated “fMAX no feedback.” For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no feedback, it is calculated the same way as fMAX no feedback. The minimum period will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is specified as 1/(tWICL + tWICH). Note that if both input and output registers are used in the same path, the overall frequency will be limited by tICS. All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is measured directly. CLK CLK (SECOND CHIP) LOGIC tS REGISTER LOGIC tCO tS fMAX Internal (fCNT) fMAX External 1/(ts + tCO) CLK LOGIC REGISTER CLK REGISTER REGISTER tS fMAX No Feedback; 1/(ts + tH) or 1/(tWH + tWL) LOGIC tHIR tSIR fMAXIR; 1/(tSIR + tHIR) or 1/(tWICL + tWICH) 20405C-24 MACH211SP-7/10/12/15 25 MACH 1 & 2 Families fMAX PARAMETERS V A N T I S ENDURANCE CHARACTERISTICS The MACH families are manufactured using Vantis’ advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Endurance Characteristics Parameter Symbol tDR N Parameter Description Units 10 Years Max Storage Temperature 20 Years Max Operating Temperature 100 Cycles Normal Programming Conditions Min Pattern Data Retention Time Max Reprogramming Cycles Test Conditions INPUT/OUTPUT EQUIVALENT SCHEMATICS VCC 100 kΩ VCC 1 kΩ ESD Protection Input VCC VCC 100 kΩ 1 kΩ Preload Circuitry Feedback Input I/O 20405C-25 26 MACH211SP-7/10/12/15 V A N T I S The MACH devices have been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Symbol Parameter Descriptions tPR Power-Up Reset Time tS Input or Feedback Setup Time tWL Max Unit 10 µs See Switching Characteristics Clock Width LOW VCC Power 4V tPR Registered Output tS Clock tWL 20405C-26 Power-Up Reset Waveform MACH211SP-7/10/12/15 27 MACH 1 & 2 Families POWER-UP RESET V A N T I S DEVELOPMENT SYSTEMS (subject to change) For more information on the products listed below, please consult the local Vantis sales office. MANUFACTURER SOFTWARE DEVELOPMENT SYSTEMS Vantis Corporation P.O. Box 3755 920 DeGuigne Drive Sunnyvale, CA 94088 (408) 732-0555 or 1(888) 826-8472 (VANTIS2) http://www.vantis.com MACHXL Software Vantis-ABEL Software Vantis-Synario Software Aldec, Inc. 3 Sunset Way, Suite F Henderson, NV 89014 (702) 456-1222 or (800) 487-8743 ACTIVE-CAD Cadence Design Systems 555 River Oaks Pkwy San Jose, CA 95134 (408) 943-1234 or (800) 746-6223 PIC Designer Concept/Composer Synergy Leapfrog/Verilog-XL Exemplar Logic, Inc. 815 Atlantic Avenue, Suite 105 Alameda, CA 94501 (510) 337-3700 Leonardo™ Galileo™ Logic Modeling 19500 NW Gibbs Dr. P.O. Box 310 Beaverton, OR 97075 (800) 346-6335 Mentor Graphics Corp. 8005 S.W. Boeckman Rd. Wilsonville, OR 97070-7777 (800) 547-3000 or (503) 685-7000 SmartModel® Library Design Architect, PLDSynthesis™ II Autologic II Synthesizer, QuickSim Simulator, QuickHDL Simulator MicroSim Corp. 20 Fairbanks Irvine, CA 92718 (714) 770-3022 MicroSim Design Lab PLogic, PLSyn MINC Inc. 6755 Earl Drive, Suite 200 Colorado Springs, CO 80918 (800) 755-FPGA or (719) 590-1155 PLDesigner-XL™ Software Model Technology 8905 S.W. Nimbus Avenue, Suite 150 Beaverton, OR 97008 (503) 641-1340 V-System/VHDL OrCAD, Inc. 9300 S.W. Nimbus Avenue Beaverton, OR 97008 (503) 671-9500 or (800) 671-9505 OrCAD Express Synario® Design Automation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 332-8246 or (206) 881-6444 28 ABEL™ Synario™ Software MACH211SP-7/10/12/15 V A N T I S Synopsys 700 E. Middlefield Rd. Mountain View, CA 94040 (415) 962-5000 or (800) 388-9125 SOFTWARE DEVELOPMENT SYSTEMS FPGA or Design Compiler (Requires MINC PLDesigner-XL™) VSS Simulator Synplicity, Inc. 624 East Evelyn Ave. Sunnyvale, CA 94086 (408) 617-6000 Teradyne EDA 321 Harrison Ave. Boston, MA 02118 (800) 777-2432 or (617) 422-2793 Synplify MultiSIM Interactive Simulator LASAR VeriBest, Inc. 6101 Lookout Road, Suite A Boulder, CO 80301 (800) 837-4237 Viewlogic Systems, Inc. 293 Boston Post Road West Marlboro, MA 01752 (800) 873-8439 or (508) 480-0881 MANUFACTURER Acugen Software, Inc. 427-3 Amherst St., Suite 391 Nashua, NH 03063 (603) 881-8821 MACH 1 & 2 Families MANUFACTURER VeriBest PLD Viewdraw, ViewPLD, Viewsynthesis Speedwave Simulator, ViewSim Simulator, VCS Simulator TEST GENERATION SYSTEM ATGEN™ Test Generation Software iNt GmbH Busenstrasse 6 D-8033 Martinsried, Munich, Germany (87) 857-6667 PLDCheck 90 Vantis is not responsible for any information relating to the products of third parties. The inclusion of such information is not a representation nor an endorsement by Vantis of these products. MACH211SP-7/10/12/15 29 V A N T I S APPROVED PROGRAMMERS (subject to change) For more information on the products listed below, please consult the local Vantis sales office. MANUFACTURER PROGRAMMER CONFIGURATION Advin Systems, Inc. 1050-L East Duane Ave. Sunnyvale, CA 940 86 (408) 243-7000 or (800) 627-2456 BBS (408) 737-9200 Fax (408) 736-2503 BP Microsystems 1000 N. Post Oak Rd., Suite 225 Houston, TX 77055-7237 (800) 225-2102 or (713) 688-4600 BBS (713) 688-9283 Fax (713) 688-0920 Data I/O Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 426-1045 or (206) 881-6444 BBS (206) 882-3211 Fax (206) 882-1043 Pilot-U40 BP1200 UniSite™ Hi-Lo Systems 4F, No. 2, Sec. 5, Ming Shoh E. Road Taipei, Taiwan (886) 2-764-0215 Fax (886) 2-756-6403 or Tribal Microsystems / Hi-Lo Systems 44388 South Grimmer Blvd. Fremont, CA 94538 (510) 623-8859 BBS (510) 623-0430 Fax (510) 623-9925 SMS GmbH Im Grund 15 88239 Wangen Germany (49) 7522-97280 Fax (49) 7522-972850 or SMS USA 544 Weddell Dr. Suite 12 Sunnyvale, CA 94089 (408) 542-0388 BP1400 Model 2900 ALL-07 Sprint Expert Stag House Silver Court Watchmead, Welwyn Garden City Herfordshire UK AL7 1LT 44-1-707-332148 Fax 44-1-707-371503 30 Pilot-U84 BP2100 BP2200 Model 3900 AutoSite FLEX-700 Sprint Optima Stag Quazar MACH211SP-7/10/12/15 MVP Multisite V A N T I S MACH 1 & 2 Families MANUFACTURER PROGRAMMER CONFIGURATION System General 1603A South Main Street Milpitas, CA 95035 (408) 263-6667 BBS (408) 262-6438 Fax (408) 262-9220 or 3F, No. 1, Alley 8, Lane 45 Bao Shing Road, Shin Diau Taipei, Taiwan (886) 2-917-3005 Fax (886) 2-911-1283 Turpro-1 Turpro-1/FX Turpro-1/TX APPROVED ADAPTER MANUFACTURERS MANUFACTURER California Integration Coordinators, Inc. 656 Main Street Placerville, CA 95667 (916) 626-6168 Fax (916) 626-7740 PROGRAMMER CONFIGURATION MACH/PAL Programming Adapters Emulation Technology, Inc. 2344 Walsh Ave., Bldg. F Santa Clara, CA 95051 (408) 982-0660 Fax (408) 982-0664 Adapt-A-Socket® Programming Adapters APPROVED ON-BOARD ISP PROGRAMMING TOOLS MANUFACTURER PROGRAMMER CONFIGURATION Corelis, Inc. 12607 Hidden Creek Way, Suite H Cerritos, California 70703 (310) 926-6727 JTAGPROG™ Vantis Corporation P.O. Box 3755 920 DeGuigne Drive Sunnyvale, CA 94088 (408) 732-0555 or 1(888) 826-8472 (VANTIS2) http://www.vantis.com MACHPRO® MACH211SP-7/10/12/15 31 V A N T I S PHYSICAL DIMENSIONS PL 044 44-Pin Plastic Leaded Chip Carrier (measured in inches) .685 .695 .650 .656 .062 .083 .042 .056 Pin 1 I.D. .685 .695 .650 .656 .500 .590 REF .630 .013 .021 .026 .032 .050 REF .009 .015 .090 .120 .165 .180 TOP VIEW 32 SEATING PLANE SIDE VIEW MACH211SP-7/10/12/15 16-038-SQ PL 044 DA78 6-28-94 ae V A N T I S MACH 1 & 2 Families PHYSICAL DIMENSIONS PQT044 44-Pin Thin Quad Flat Pack (measured in millimeters) 44 1 11.80 12.20 9.80 10.20 9.80 10.20 11.80 12.20 11° – 13° 0.95 1.05 1.20 MAX 1.00 REF. 0.30 0.45 0.80 BSC 11° – 13° 16-038-PQT-2 PQT 44 7-11-95 ae Trademarks Copyright © 1997 Advanced Micro Devices, Inc. All rights reserved. AMD, Vantis, the Vantis logo and combinations thereof, SpeedLocking and Bus-Friendly are trademarks, MACH, MACHXL, MACHPRO and PAL are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. MACH211SP-7/10/12/15 33