USE GAL DEVICES FOR NEW DESIGNS FINAL COM’L: H-15/25 Lattice Semiconductor PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS ■ Lattice/Vantis Programmable Array Logic (PAL) architecture ■ Asynchronous clocking via product term or bank register clocking from external pins ■ Electrically-erasable CMOS technology providing half power (90 mA ICC) at high speed ■ Register preload for testability — -15 = 15-ns tPD ■ Power-up reset for initialization ■ Space-saving 24-pin SKINNYDIP and 28-pin PLCC packages — -25 = 25-ns tPD ■ Sixteen macrocells with configurable I/O architecture ■ Fully tested for 100% programming yield and high reliability ■ Registered or combinatorial operation ■ Registers programmable as D, T, J-K, or S-R ■ Extensive third-party software and programmer support through FusionPLD partners GENERAL DESCRIPTION The PALCE610 is a general purpose PAL device and is functionally and fuse map equivalent to the EP610. It can accommodate logic functions with up to 20 inputs and 16 outputs. There are 16 I/O macrocells that can be individually configured to the user’s specifications. The macrocells can be configured as either registered or combinatorial. The registers can be configured as D, T, J-K, or S-R flip-flops. The PALCE610 uses the familiar sum-of-products logic with programmable-AND and fixed-OR structure. Eight product terms are brought to each macrocell to provide logic implementations. The PALCE610 is manufactured using advanced CMOS EE technology providing low power consumption. Moreover, it is a high-speed device having a worstcase tPD of 15 ns. Space-saving 24-pin SKINNYDIP and 28-pin PLCC packages are offered. This device can be quickly erased and reprogrammed providing for easy prototyping. Once a device is programmed the security bit can be used to provide protection from copying a proprietary design. BLOCK DIAGRAM I I/O16 I/O15 2 8 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 2 8 2 8 2 8 2 8 Programmable AND Array 40 x 160 2 8 2 8 2 8 2 8 2 8 2 8 2 8 2 8 2 8 2 8 2 8 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 CLK1 4 CLK2 2-374 Publication# 12950 Rev. G Issue Date: February 1996 12950G-1 Amendment /0 CONNECTION DIAGRAMS Top View SKINNYDIP I/O9 3 22 I/O1 I/O10 4 21 I/O2 I/O11 5 20 I/O3 I/O12 6 19 I/O13 7 I/O14 4 3 2 1 28 27 26 I/O1 I I 23 VCC VCC 2 VCC 24 I CLK1 1 I CLK1 I/O9 PLCC/LCC I/O10 5 25 I/O2 I/O4 I/O11 6 24 I/O3 18 I/O5 I/O12 7 23 I/O4 8 17 I/O6 I/O13 8 22 I/O5 I/O15 9 16 I/O7 I/O14 9 21 I/O6 I/O16 10 15 I/O8 I/O15 10 20 I/O7 I 11 14 I NC 11 19 NC GND 12 13 CLK2 Note: Pin 1 is marked for orientation I/O8 I CLK2 GND I GND 12950G-2 I/O16 12 13 14 15 16 17 18 12950G-3 PIN DESIGNATIONS CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect VCC = Supply Voltage PALCE610 Family 2-375 ORDERING INFORMATION Commercial Products Programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: PAL CE 610 H -15 P C FAMILY TYPE PAL = Programmable Array Logic OPERATING CONDITIONS C = Commercial (0°C to +75°C) TECHNOLOGY CE = CMOS Electrically Erasable PACKAGE TYPE P = 24-Pin 300 mil Plastic SKINNYDIP (PD3024) J = 28-Pin Plastic Leaded Chip Carrier (PL 028) DEVICE NUMBER 610 = 600 Gates POWER H = Half Power (90 mA ICC) SPEED -15 = 15 ns tPD -25 = 25 ns tPD Valid Combinations PALCE610H-15 PC, JC PALCE610H-25 2-376 Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations, and to check on newly released combinations. PALCE610H-15/25 (Com’l) FUNCTIONAL DESCRIPTION The PALCE610 is a general purpose programmable logic device. It has 16 independently-configurable macrocells. Each macrocell can be configured as either combinatorial or registered. The registers can be D, T, J-K, or S-R type flip-flops. The device has 4 dedicated input pins and 2 clock pins. Each clock pin controls 8 of the 16 macrocells. The programming matrix implements a programmable AND logic array which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide user-programmable input polarity. Unused input pins should be tied to VCC or ground. asynchronous configuration, the clock input is controlled by the product term. The output is always enabled. In The D and T configurations, feedback can be either from Q or the output pin. This allows D and T configurations to be either outputs or I/O. In the J-K and S-R configurations, feedback is only from Q; therefore, J-K and S-R configurations are strictly outputs. D Flip-Flop All 8 product terms are available to the OR gate. The D input polarity is controlled by an exclusive-OR gate. For the D flip-flop, the output level is the D-input level at the rising edge of the clock. The array uses our electrically erasable technology. An unprogrammed bit is disconnected and a programmed bit is connected. Product terms with all bits unprogrammed assume the logical-HIGH state and product terms with both the TRUE and Complement bits programmed assume the logical-LOW state. The programmable functions in the PALCE610 are automatically configured from the user’s design specifications, which can be in a number of formats. The design specification is processed by development software to verify the design and create a programming file. This file, once downloaded to the programmer, configures the design according to the user’s desired function. Each macrocell can select as its clock either the corresponding clock pin or the CLK/OE product term. If the clock pin is selected, the output enable is controlled by the CLK/OE product term. If the CLK/OE product term is selected, the output is always enabled. Qn Qn+1 0 0 0 0 1 0 1 0 1 1 1 1 T Flip-Flop All 8 product terms are available to the OR gate. The T input polarity is controlled by an exclusive-OR gate. For the T register, the output level toggles when the T input is HIGH and remains the same when the T input is LOW. Macrocell Configurations The PALCE610 macrocell can be configured as either combinatorial or registered. Both the combinatorial and registered configurations have output polarity control. The register can be configured as a D, T, J-K, or S-R type flip-flop. Figure 1 shows the possible configurations. D T Qn Qn+1 0 0 0 0 1 1 1 0 1 1 1 0 J-K Flip-Flop The 8 product terms are divided between the J and K inputs. N product terms go to the J input and 8-N product terms go to the K input, where N can range from 0 to 8. Both the J and K inputs to the flip-flop have polarity control via exclusive-OR gates. The J-K flip-flop operation is shown below. Combinatorial I/O J K Qn All 8 product terms are available to the OR gate. The output-enable function is performed by the CLK/OE product term. 0 0 0 0 0 0 1 1 0 1 0 0 Registered Configurations 0 1 1 0 There are 4 flip-flop types available: D, T, J-K and S-R. 1 0 0 1 The registers can be configured as synchronous or asynchronous. In the synchronous configuration, the clock is controlled by the clock input pin. The output enable is controlled by the product term function. In the 1 0 1 1 1 1 0 1 1 1 1 0 PALCE610 Family Qn+1 2-377 Combinatorial 1 0 VCC 1 0 CLK 1 0 VCC 1 0 CLK T Q D Q AR AR 1 0 1 0 D Register T Register VCC VCC 1 0 1 0 CLK 1 0 1 0 CLK N N J Q 8–N S Q 8–N K AR R AR S–R Register J–K Register 12950G-4 Figure 1. Macrocell Configurations 2-378 PALCE610 Family S-R Flip-Flop Security Bit The 8 product terms are divided between the S and R inputs. N product terms go to the S input and 8-N product terms go to the R input, where N can range from 0 to 8. Both the S and R inputs to the flip-flop have polarity control via exclusive-OR gates. The S-R flip-flop operation is shown below. After programming and verification, a PALCE610 design can be secured by programming the security bit. Once programmed, this bit defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. However, programming and verification are also defeated by the security bit. The bit can only be erased in conjunction with the array during the erase cycle. Preload is not affected by the security bit. S R Qn Qn+1 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 Technology All flip-flops have an asynchronous-reset product-term input. When the product term is true, the flip-flop will reset to a logic LOW, regardless of the clock and data inputs. The PALCE610 is manufactured using our advanced Electrically Erasable (EE) CMOS process. This technology uses an EE cell to replace the fuse link in bipolar parts, and allows Lattice to offer lower-power parts of high complexity. In addition, since the EE cells can be erased and reprogrammed, these devices can be 100% factory tested before being shipped to the customer. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input clamp diodes, output slew-rate control, and a grounded substrate for clear switching. Power-Up Reset Programming and Erasing All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCE610 depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be LOW. If combinatorial is selected, the output will be a function of the logic. The VCC rise must be monotonic and the reset delay time is 1000 ns maximum. The PALCE610 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its virgin state. Bulk erase is automatically performed by the programming hardware. No special erase operation is required. Register Preload The PALCE610 has CMOS-compatible outputs. The output voltage (VOH) is 3.85 V at –2.0 mA. 1 Not Allowed Asynchronous Reset The register on the PALCE610 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. CMOS Compatibility PALCE610 Family 2-379 PALCE610 LOGIC DIAGRAM DIP (PLCC) Pinouts 40 CLK1 24 VCC (1, 28) 1 (2) 2 (3) INPUT 80 0 I/O 9 3 (4) NODE 1 Macrocell Macrocell AR OE/CLK 89 9 90 10 AR OE/CLK I/O 10 4 (5) NODE 2 Macrocell Macrocell AR OE/CLK 99 AR OE/CLK 19 23 (27) INPUT 22 (26) I/O 1 NODE 16 21 (25) I/O 2 NODE 15 100 20 I/O 11 5 (6) NODE 3 Macrocell Macrocell AR OE/CLK AR OE/CLK 109 29 110 (7) Macrocell Macrocell I/O 13 7 NODE 5 I/O 16 10 (12) NODE 8 INPUT 40 AR OE/CLK 49 18 (22) Macrocell 139 59 140 60 AR OE/CLK Macrocell Macrocell AR OE/CLK 149 69 150 70 AR OE/CLK Macrocell Macrocell AR OE/CLK 159 AR OE/CLK 79 0 8 16 24 32 39 0 8 16 24 32 39 I/O 5 NODE 12 130 50 11 (13) GND 12 I/O 4 AR OE/CLK Macrocell I/O 15 9 NODE 7 120 129 AR OE/CLK (10) 39 Macrocell I/O 14 8 NODE 6 119 Macrocell AR OE/CLK (9) 19 (23) NODE 13 AR OE/CLK (8) I/O 3 NODE 14 30 I/O 12 6 NODE 4 20 (24) 17 (21) I/O 6 NODE 11 16 (20) I/O 7 NODE 10 15 (18) I/O 8 NODE 9 14 (17) INPUT 13 (16) CLK2 (14, 15) 40 12950G-5 2-380 PALCE610 Family ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to +75°C) . . . . . . . . . . . . . . . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified (Note 2) Parameter Symbol Parameter Description Test Conditions Min Max VOH Output HIGH Voltage VIN = VIH or VIL VCC = Min IOH = –4.0 mA IOH = –2.0 mA VOL Output LOW Voltage VIN = VIH or VIL VCC = Min IOL = 8.0 mA IOL = 4.0 mA VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –10 µA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –10 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –150 mA ICC Supply Current VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max 90 mA 2.4 3.84 V V 0.5 0.45 2.0 –30 Unit V V V Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. PALCE610H-15/25 (Com’l) 2-381 CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Input Capacitance VIN = 2.0 V Output Capacitance VOUT = 2.0 V Typ VCC = 5.0 V TA = +25°C f = 1 MHz Unit 8 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol -15 Parameter Description Min tPD Input or Feedback to Combinatorial Output -25 Max Min 15 Max Unit 25 ns tS Setup Time from Input or Feedback to Clock 12 15 ns tH Hold Time 0 0 ns tCO Clock to Output tWL tWH fMAX Clock Width Maximum Frequency (Note 3) 8 12 ns LOW 6 10 ns HIGH 6 10 ns 50 76.1 37 40 MHz MHz 83.3 50 MHz External Feedback Internal Feedback (fCNT) No Feedback 1/(tS + tCO) 1/(tS + tCF) (Note 5) 1/(tWH + tWL) tEA Input to Output Enable Using Product Term Control 15 25 ns tER Input to Output Disable Using Product Term Control 15 25 ns tAR Asynchronous Reset to Registered Output 25 ns 15 tARW Asynchronous Reset Width tARR Asynchronous Reset Recovery Time tSA Setup Time from Input or Feedback to Clock (Note 4) 5 8 ns tHA Hold Time (Note 4) 5 12 ns tCOA Clock to Output (Note 4) tWLA Clock Width tWHA fMAXA Maximum Frequency (Notes 3 and 4) 10 15 15 ns 25 15 27 ns ns LOW (Note 4) 6 10 ns HIGH (Note 4) 6 10 ns 50 61.6 83.3 28.6 29.4 50 MHz MHz MHz External Feedback 1/(tSA + tCOA) Internal Feedback (fCNT) No Feedback 1/(tWLA + tWHA) Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. These parameters are measured using the asynchronous product-term clock. 5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) – tS. 2-382 PALCE610H-15/25 (Com’l) SWITCHING WAVEFORMS Input or Feedback VT tS Input or Feedback tH VT VT Clock tPD Combinatorial Output tCO Registered Output VT VT 12950G-6 12950G-7 Combinatorial Output Registered Output VT Input tWH tER VT Clock Output tWL tEA VOH - 0.5V VT VOL + 0.5V 12950G-9 12950G-8 Clock Width Input to Output Disable/Enable Input or Feedback VT tSA Product-Term Clock tWHA Product-Term Clock tHA VT tCOA VT Registered Output tWLA VT 12950G-10 Input Asserting Asynchronous Reset 12950G-11 Registered Output Using Product-Term Clock Clock Width Using Product-Term Clock tARW VT tAR Registered Output VT tARR Clock Notes: VT Asynchronous Reset 12950G-12 1. VT = 1.5 V 2. Input pulse amplitude 0 V to 3.0 V 3. Input rise and fall times 2 ns–5 ns typical. PALCE610 Family 2-383 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING TEST CIRCUIT 5V S1 R1 Output Test Point R2 CL 12950G-13 Commercial Specification tPD, tCO tEA tER S1 CL R1 Closed Measured Output Value 1.5 V Z → H: Open Z → L: Closed 35 pF H → Z: Open 5 pF 855 Ω 340 Ω 1.5 V H → Z: VOH – 0.5 V L → Z: Closed 2-384 R2 L → Z: VOL + 0.5 V PALCE610 Family ENDURANCE Symbol tDR N Parameter Description Test Conditions Min Unit Pattern Data Retention Time Max Storage Temperature 10 Years Max Operating Temperature 20 Years Normal Programming Conditions 100 Cycles Reprogramming Cycles INPUT/OUTPUT EQUIVALENT SCHEMATICS VCC ESD Program/Verify Protection Circuitry Typical Input VCC Preload Circuitry Feedback Input Typical Output 12950G-14 PALCE610 Family 2-385 Power-Up Reset The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and wide range of ways VCC can rise to Parameter Symbol its steady state, two conditions are required to insure a valid power-up reset. These conditions are: ■ The VCC rise must be monotonic. ■ Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Description Max Unit tPR Power-up Reset Time 1000 ns tS Input or Feedback Setup Time tWL Clock Width LOW See Switching Characteristics VCC 4V Power tPR Registered Output tS Clock tWL 12950G-15 Power-Up Reset Waveform 2-386 PALCE610 Family TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Parameter Symbol Typ SKINNYDIP PLCC Parameter Description Unit θjc Thermal impedance, junction to case 21 20 °C/W θja Thermal impedance, junction to ambient 72 57 °C/W 200 lfpm air 64 47 °C/W 400 lfpm air 60 44 °C/W 600 lfpm air 55 40 °C/W 800 lfpm air 49 36 °C/W θjma Thermal impedance, junction to ambient with air flow Plastic θjc Considerations The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. PALCE610 Family 2-387