LATTICE MACH230-10

FINAL
COM’L: -10/15/20
IND: -18/24
MACH230-10/15/20
Lattice Semiconductor
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
84 Pins
64 Outputs
128 Macrocells
128 Flip-flops; 4 clock choices
10 ns tPD Commercial
18 ns tPD Industrial
8 “PAL26V16” blocks with buried macrocells
100 MHz fCNT
Pin-compatible with MACH130, MACH131,
MACH231, and MACH435
70 Inputs
GENERAL DESCRIPTION
The MACH230 is a member of the high-performance
EE CMOS MACH 2 device family. This device has approximately twelve times the logic macrocell capability
of the popular PAL22V10 without loss of speed.
The MACH230 consists of eight PAL blocks interconnected by a programmable switch matrix. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACH230 has two kinds of macrocell: output and
buried. The output macrocell provides registered,
latched, or combinatorial outputs with programmable
polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help
reduce the number of product terms. The register type
decision can be made by the designer or by the software. All output macrocells can be connected to an I/O
cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees
up the I/O pin for use as an input.
The MACH230 has dedicated buried macrocells which,
in addition to the capabilities of the output macrocell,
also provide input registers for use in synchronizing
signals and reducing setup time requirements.
BLOCK DIAGRAM
If you would like to view
Block Diagram in full size,
please click on the box.
Publication# 14132 Rev. I
Issue Date: May 1995
Amendment /0
I/O0 – I/O7 (Block A)
I/O16 – I/O23 (Block C)
I/O8 – I/O15 (Block B)
8
I/O Cells
8
I/O Cells
8
8
I/O Cells
8
8
Macrocells
Macrocells
I2, I5
8
8
8
Macrocells
I/O24 – I/O31 (Block D)
8
I/O Cells
8
8
Macrocells
Macrocells
8
8
8
Macrocells
8
Macrocells
Macrocells
2
OE
OE
OE
OE
52 x 68
AND Logic Array
and Logic Allocator
52 x 68
AND Logic Array
and Logic Allocator
52 x 68
AND Logic Array
and Logic Allocator
52 x 68
AND Logic Array
and Logic Allocator
Switch Matrix
26
26
26
Siblings
26
Siblings
26
Siblings
26
Siblings
26
26
52 x 68
AND Logic Array
and Logic Allocator
52 x 68
AND Logic Array
and Logic Allocator
52 x 68
AND Logic Array
and Logic Allocator
52 x 68
AND Logic Array
and Logic Allocator
OE
OE
OE
OE
8
Macrocells
Macrocells
Macrocells
8
8
8
8
I/O Cells
I/O Cells
8
I/O56 – I/O63 (Block H)
Macrocells
Macrocells
8
8
I/O48 – I/O55 (Block G)
Macrocells
8
I/O Cells
8
Macrocells
8
8
4
Macrocells
8
4
8
I/O Cells
8
I/O40 – I/O47 (Block F)
4
8
I/O31 – I/O39 (Block E)
CLK0/I0, CLK1/I1
CLK2/I3, CLK3/I4
14132I-1
CONNECTION DIAGRAM
Top View
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O58
I/O57
I/O56
I/O61
I/O60
I/O59
4
5
I/O63
I/O62
6
VCC
I5
I/O1
I/O0
8 7
VCC
GND
I/O3
I/O2
11 10 9
I/O5
I/O4
I/O7
I/06
GND
84 PLCC
3 2 1 84 83 82 81 80 79 78 77 76 75
12
74
73
72
71
70
69
13
14
15
16
17
68
I/O15
CLK0/I0
18
19
20
VCC
21
65
GND
CLK1/I1
22
64
23
24
25
63
26
27
28
29
30
60
59
58
57
31
55
32
54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
I/O52
I/O51
I/O50
I/O49
I/O48
CLK3/I4
GND
VCC
CLK2/I3
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
GND
I/O37
I/O38
I/O39
I/O34
I/O35
I/O36
VCC
I/O32
I/O33
VCC
GND
I2
I/O31
56
I/O24
I/O25
I/O23
GND
62
61
I/O28
I/O29
I/O30
I/O20
I/O21
I/O22
66
I/O26
I/O27
I/O16
I/O17
I/O18
I/O19
67
GND
I/O55
I/O54
I/O53
14132I-2
Note:
Pin-compatible with MACH130, MACH131, MACH231, and MACH435.
PIN DESIGNATIONS
CLK/I =
GND =
I
=
I/O =
VCC
Clock or Input
Ground
Input
Input/Output
= Supply Voltage
MACH230-10/15/20
3
ORDERING INFORMATION
Commercial Products
Programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
MACH
230 -10
J
C
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
DEVICE NUMBER
230 = 128 Macrocells, 84 Pins
SPEED
-10 = 10 ns tPD
-15 = 15 ns tPD
-20 = 20 ns tPD
PACKAGE TYPE
J = 84-Pin Plastic Leaded
Chip Carrier (PL 084)
Valid Combinations
MACH230-10
MACH230-15
MACH230-20
4
JC
Valid Combinations
The Valid Combinations table lists configurations
planned to be supported in volume for this device. Consult your local sales office to confirm availability of
specific valid combinations and to check on newly released combinations.
MACH230-10/15/20 (Com’l)
ORDERING INFORMATION
Industrial Products
Programmable logic products for industrial applications are available with several ordering options. The order number (Valid
Combination) is formed by a combination of:
MACH
230 -18
J
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
I = Industrial (–40°C to +85°C)
DEVICE NUMBER
230 = 128 Macrocells, 84 Pins
SPEED
-18 = 18 ns tPD
-24 = 24 ns tPD
PACKAGE TYPE
J = 84-Pin Plastic Leaded
Chip Carrier (PL 084)
Valid Combinations
MACH230-18
MACH230-24
I
JI
Valid Combinations
The Valid Combinations table lists configurations
planned to be supported in volume for this device.
Consult your local sales office to confirm availability of specific valid combinations and to check on newly
released combinations.
MACH230-18/24 (Ind)
5
FUNCTIONAL DESCRIPTION
The MACH230 consists of eight PAL blocks connected
by a switch matrix. There are 64 I/O pins and 2
dedicated input pins feeding the switch matrix. These
signals are distributed to the four PAL blocks for efficient
design implementation. There are 4 clock pins that can
also be used as dedicated inputs.
The PAL Blocks
Each PAL block in the MACH230 (Figure 1) contains a
64-product-term logic array, a logic allocator, 8 output
macrocells, 8 buried macrocells, and 8 I/O cells. The
switch matrix feeds each PAL block with 26 inputs. This
makes the PAL block look effectively like an independent “PAL26V16” with 8 buried macrocells.
In addition to the logic product terms, two output enable
product terms, an asynchronous reset product term,
and an asynchronous preset product term are provided.
One of the two output enable product terms can be
chosen within each I/O cell in the PAL block. All flip-flops
within the PAL block are initialized together.
configures the logic allocator when fitting the design into
the device.
Table 2 illustrates which product term clusters are
available to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.
Table 2. Logic Allocation
Macrocell
Output
Buried
The MACH230 switch matrix is fed by the inputs and
feedback signals from the PAL blocks. Each PAL block
provides 16 internal feedback signals and 8 I/O
feedback signals. The switch matrix distributes these
signals back to the PAL blocks in an efficient manner
that also provides for high performance. The design
software automatically configures the switch matrix
when fitting a design into the device.
The MACH230 places a restriction on buried macrocell
feedback only. Buried macrocell feedback from one
block can be used as an input only to that block or its
“sibling” block. Sibling blocks are illustrated in the block
diagram and in Table 1. Output macrocell feedback is
not restricted.
Table 1. Sibling Blocks
PAL Block
Sibling Block
A
B
C
D
E
F
G
H
H
G
F
E
D
C
B
A
The Product-Term Array
The MACH230 product-term array consists of 64
product terms for logic use, and 4 special-purpose
product terms. Two of the special-purpose product
terms provide programmable output enable, one
provides asynchronous reset, and one provides asynchronous preset.
The Logic Allocator
The logic allocator in the MACH230 takes the 64 logic
product terms and allocates them to the 16 macrocells
as needed. Each macrocell can be driven by up to 16
product terms. The design software automatically
6
M1
C0, C1, C2
C0, C1, C2, C3
M3
C1, C2, C3, C4
C2, C3, C4, C5
M5
C3, C4, C5, C6
C4, C5, C6, C7
M7
C5, C6, C7, C8
C6, C7, C8, C9
M9
C7, C8, C9, C10
C8, C9, C10, C11
M11
C9, C10, C11, C12
C10, C11, C12, C13
M13
C11, C12, C13, C14
C12, C13, C14, C15
M15
C13, C14, C15
C14, C15
M0
M2
M4
M6
M8
M10
The Switch Matrix
Available
Clusters
M12
M14
The Macrocell
The MACH230 has two types of macrocell: output and
buried. The output macrocells can be configured as
either registered, latched, or combinatorial, with programmable polarity. The macrocell provides internal
feedback whether configured with or without the flipflop. The registers can be configured as D-type or
T-type, allowing for product-term optimization.
The flip-flops can individually select one of four clock/
gate pins, which are also available as data inputs. The
registers are clocked on the LOW-to-HIGH transition of
the clock signal. The latch holds its data when the gate
input is HIGH, and is transparent when the gate input is
LOW. The flip-flops can also be asynchronously initialized with the common asynchronous reset and preset
product terms.
The buried macrocells are the same as the output
macrocells if they are used for generating logic. In that
case, the only thing that distinguishes them from the
output macrocells is the fact that there is no I/O cell
connection, and the signal is only used internally. The
buried macrocell can also be configured as an input
register or latch.
The I/O Cell
The I/O cell in the MACH230 consists of a three-state
output buffer. The three-state buffer can be configured
in one of three ways: always enabled, always disabled,
or controlled by a product term. If product term control is
chosen, one of two product terms may be used to
provide the control. The two product terms that are
available are common to all I/O cells in a PAL block.
These choices make it possible to use the macrocell as
an output, an input, a bidirectional pin, or a three-state
output for use in driving a bus.
MACH230-10/15/20
0
4
8
12
16
20
24
28
32
36
40
43
47
51
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
Output
Macro
Cell
M0
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
Buried
Macro
Cell
M1
Output
Macro
Cell
M2
Buried
Macro
Cell
M3
0
C0
I/O
Cell
Output
Macro
Cell
M4
C1
C2
Buried
Macro
Cell
M5
C3
C5
C6
Switch
Matrix
C7
C8
Logic Allocator
C4
C9
Output
Macro
Cell
M6
Buried
Macro
Cell
M7
Output
Macro
Cell
M8
C10
C11
Buried
Macro
Cell
M9
C12
C13
Output
Macro
Cell
M10
C14
C15
63
Buried
Macro
Cell
M11
Output
Macro
Cell
M12
Buried
Macro
Cell
M13
M15
Buried
Macro
Cell
CLK
M14
Output
Macro
Cell
4
0
4
8
12
16
20
24
28
32
36
40
43
47
51
16
8
14132I-3
Figure 1. MACH230 PAL Block
MACH230-10/15/20
7
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature
With Power Applied . . . . . . . . . . . . . –55°C to +125°C
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
DC Input Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Static Discharge Voltage . . . . . . . . . . . . . . . . 2001 V
Latchup Current
(TA = 0°C to 70°C) . . . . . . . . . . . . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA, VCC = Min
VIN = VIH or VIL
2.4
VOL
Output LOW Voltage
IOL = 16 mA, VCC = Min
VIN = VIH or VIL
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Current
VIN = 5.25 V, VCC = Max (Note 2)
10
µA
IIL
Input LOW Current
VIN = 0 V, VCC = Max (Note 2)
–10
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
10
µA
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–10
µA
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Note 3)
–130
mA
ICC
Supply Current
VIN = 0 V, Outputs Open (IOUT = 0 mA)
VCC = 5.0 V, f = 25 MHz, TA = 25°C
(Note 4)
V
0.5
2.0
V
V
–30
235
mA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. This parameter is measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and
capable of being loaded, enabled, and reset.
8
MACH230-10 (Com’l)
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Typ
Unit
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C
6
pF
Output Capacitance
VOUT = 2.0 V
f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Parameter
Symbol
-10
Parameter Description
Min
tPD
Input, I/O, or Feedback to Combinatorial Output
tS
Setup Time from Input, I/O, or Feedback to Clock
tH
Register Data Hold Time
tCO
Clock to Output
tWL
tWH
Clock
Width
Max
Unit
10
ns
D-type
6.5
ns
T-type
7.5
ns
0
ns
6.5
ns
LOW
HIGH
4
4
ns
ns
D-type
77
MHz
T-type
72
MHz
D-type
100
MHz
T-type
91
MHz
No Feedback
125
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate
8
ns
tHL
Latch Data Hold Time
0
ns
tGO
Gate to Output
tGWL
Gate Width LOW
tPDL
Input, I/O, or Feedback to Output Through Transparent
Input or Output Latch
tSIR
Input Register Setup Time
2
ns
tHIR
Input Register Hold Time
2.5
ns
tICO
Input Register Clock to Combinatorial Output
tICS
Input Register Clock to Output Register Setup
External Feedback
fMAX
Maximum
Frequency
Internal Feedback (fCNT)
7.5
4
tWICL
tWICH
Input Register
Clock Width
fMAXIR
Maximum Input Register Frequency
ns
ns
14
15.5
ns
ns
D-type
11
ns
T-type
12
ns
LOW
HIGH
4
4
ns
ns
125
MHz
tSIL
Input Latch Setup Time
2
ns
tHIL
Input Latch Hold Time
2.5
ns
tIGO
Input Latch Gate to Combinatorial Output
17
ns
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
18
ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
MACH230-10 (Com’l)
10
ns
9
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (continued)
Parameter
Symbol
-10
Parameter Description
Min
Max
Unit
tIGS
Input Latch Gate to Output Latch Setup
11
ns
tWIGL
Input Latch Gate Width LOW
4
ns
tPDLL
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
16
ns
tAR
Asynchronous Reset to Registered or Latched Output
18
ns
tARW
Asynchronous Reset Width
10
ns
tARR
Asynchronous Reset Recovery Time
10
ns
tAP
Asynchronous Preset to Registered or Latched Output
18
ns
tAPW
Asynchronous Preset Width
10
ns
tAPR
Asynchronous Preset Recovery Time
10
ns
tEA
Input, I/O, or Feedback to Output Enable
15
ns
tER
Input, I/O, or Feedback to Output Disable
15
ns
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
10
MACH230-10 (Com’l)
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature
With Power Applied . . . . . . . . . . . . . –55°C to +125°C
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
DC Input Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Static Discharge Voltage . . . . . . . . . . . . . . . . 2001 V
Latchup Current
(TA = 0°C to 70°C) . . . . . . . . . . . . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA, VCC = Min
VIN = VIH or VIL
2.4
VOL
Output LOW Voltage
IOL = 16 mA, VCC = Min
VIN = VIH or VIL
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Current
VIN = 5.25 V, VCC = Max (Note 2)
10
µA
IIL
Input LOW Current
VIN = 0 V, VCC = Max (Note 2)
–10
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
10
µA
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–10
µA
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Note 3)
–130
mA
ICC
Supply Current (Typical)
VCC = 5 V, TA = 25°C, f = 25 MHz
(Note 4)
V
0.5
2.0
V
V
–30
235
mA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being
loaded, enabled, and reset.
MACH230-15/20 (Com’l)
11
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Typ
Unit
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C
6
pF
Output Capacitance
VOUT = 2.0 V
f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
-15
Min
Max
Parameter Description
tPD
Input, I/O, or Feedback to Combinatorial Output (Note 3)
tS
Setup Time from Input, I/O, or Feedback to Clock
tH
Register Data Hold Time
tCO
Clock to Output (Note 3)
tWL
tWH
Clock
Width
Maximum
Frequency
(Note 1)
20
1/(tS + tCO)
Internal Feedback (fCNT)
Unit
ns
D-type
10
13
ns
T-type
11
14
ns
0
10
No Feedback
ns
12
ns
LOW
HIGH
6
6
8
8
ns
ns
D-type
50
40
MHz
T-type
47.6
38.5
MHz
D-type
66.6
50
MHz
T-type
62.5
47.6
MHz
83.3
62.5
MHz
1/(tWL + tWH)
tSL
Setup Time from Input, I/O, or Feedback to Gate
10
13
ns
tHL
Latch Data Hold Time
0
0
ns
tGO
Gate to Output (Note 3)
tGWL
Gate Width LOW
tPDL
Input, I/O, or Feedback to Output Through Transparent
Input or Output Latch
11
6
12
8
17
ns
ns
22
ns
tSIR
Input Register Setup Time
2
2
ns
tHIR
Input Register Hold Time
2.5
3
ns
tICO
Input Register Clock to Combinatorial Output
tICS
Input Register Clock to Output Register Setup
tWICL
tWICH
Input Register
Clock Width
fMAXIR
Maximum Input Register Frequency
18
23
ns
D-type
15
20
ns
T-type
16
21
ns
LOW
HIGH
6
6
8
8
ns
ns
83.3
62.5
MHz
1/(tWICL + tWICH)
tSIL
Input Latch Setup Time
2
2
ns
tHIL
Input Latch Hold Time
2.5
3
ns
tIGO
Input Latch Gate to Combinatorial Output
20
25
ns
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
22
27
ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
12
15
ns
Input Latch Gate to Output Latch Setup
16
21
ns
tIGS
12
15
0
External Feedback
fMAX
-20
Min
Max
MACH230-15/20 (Com’l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
(continued)
Parameter
Symbol
-15
Parameter Description
Min
-20
Max
6
Min
Max
8
Unit
tWIGL
Input Latch Gate Width LOW
ns
tPDLL
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
19
24
ns
tAR
Asynchronous Reset to Registered or Latched Output
20
25
ns
tARW
Asynchronous Reset Width (Note 1)
15
20
ns
tARR
Asynchronous Reset Recovery Time (Note 1)
10
15
ns
tAP
Asynchronous Preset to Registered or Latched Output
20
25
ns
tAPW
Asynchronous Preset Width (Note 1)
15
20
ns
tAPR
Asynchronous Preset Recovery Time (Note 1)
10
15
ns
tEA
Input, I/O, or Feedback to Output Enable (Note 3)
15
20
ns
tER
Input, I/O, or Feedback to Output Disable (Note 3)
15
20
ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
2. See Switching Test Circuit for test conditions.
3. Parameters measured with 32 outputs switching.
MACH230-15/20 (Com’l)
13
ABSOLUTE MAXIMUM RATINGS
INDUSTRIAL OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . –40°C to +85°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Supply Voltage (VCC) with
Respect to Ground . . . . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC Output or
I/O Pin Voltage . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current
(TA =–40°C to +85°C) . . . . . . . . . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA, VCC = Min
VIN = VIH or VIL
2.4
VOL
Output LOW Voltage
IOL = 16 mA, VCC = Min
VIN = VIH or VIL
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Leakage Current
VIN = 5.25 V, VCC = Max (Note 2)
10
µA
IIL
Input LOW Leakage Current
VIN = 0 V, VCC = Max (Note 2)
–10
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
10
µA
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–10
µA
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Note 3)
–130
mA
ICC
Supply Current (Typical)
VCC = 5 V, TA = 25°C, f = 25 MHz (Note 4)
V
0.5
2.0
V
V
–30
235
mA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of
being loaded, enabled, and reset.
14
MACH230-18/24 (Ind)
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Typ
Unit
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C
6
pF
Output Capacitance
VOUT = 2.0 V
f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter
Symbol
tPD
-18
Min
Max
Parameter Description
Input, I/O, or Feedback to Combinatorial Output (Note 3)
tS
Setup Time from Input, I/O, or Feedback to Clock
tH
Register Data Hold Time
tCO
Clock to Output (Note 3)
tWL
tWH
Clock
Width
Maximum
Frequency
(Note 1)
18
24
1/(tS + tCO)
Internal Feedback (fCNT)
No Feedback
16
ns
T-type
13.5
17
ns
0
0
ns
14.5
7.5
7.5
10
10
ns
ns
D-type
40
32
MHz
T-type
38
30.5
MHz
D-type
53
38
MHz
T-type
44
34.5
MHz
66.5
50
MHz
16
ns
Setup Time from Input, I/O, or Feedback to Gate
12
0
tHL
Latch Data Hold Time
tGO
Gate to Output (Note 3)
tGWL
Gate Width LOW
tPDL
Input, I/O, or Feedback to Output Through Transparent
Input or Output Latch
tSIR
Input Register Setup Time
2.5
3.5
0
13.5
7.5
Input Register Hold Time
Input Register Clock to Combinatorial Output
tICS
Input Register Clock to Output Register Setup
tWICL
tWICH
Input Register
Clock Width
fMAXIR
Maximum Input Register Frequency
ns
LOW
HIGH
tSL
tHIR
ns
12
1/(tWL + tWH)
tICO
Unit
D-type
12
External Feedback
fMAX
-24
Min
Max
ns
14.5
10
20.5
ns
26.5
2.5
ns
ns
4
22
ns
ns
28
ns
D-type
18
24
ns
T-type
19.5
25.5
ns
LOW
HIGH
7.5
7.5
10
10
ns
ns
66.5
50
MHz
1/(tWICL + tWICH)
tSIL
Input Latch Setup Time
2.5
2.5
ns
tHIL
Input Latch Hold Time
3.5
4
ns
tIGO
Input Latch Gate to Combinatorial Output
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
24
30
ns
26.5
32.5
ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
14.5
18
ns
tIGS
Input Latch Gate to Output Latch Setup
19.5
25.5
ns
tWIGL
Input Latch Gate Width LOW
7.5
10
ns
tPDLL
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
MACH230-18/24 (Ind)
23
29
ns
15
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
(continued)
Parameter
Symbol
tAR
-18
Parameter Description
Min
Asynchronous Reset to Registered or Latched Output
-24
Max
Min
24
Max
Unit
30
ns
tARW
Asynchronous Reset Width (Note 1)
18
24
ns
tARR
Asynchronous Reset Recovery Time (Note 1)
12
18
ns
tAP
Asynchronous Preset to Registered or Latched Output
24
30
ns
tAPW
Asynchronous Preset Width (Note 1)
18
24
ns
tAPR
Asynchronous Preset Recovery Time (Note 1)
12
18
ns
tEA
Input, I/O, or Feedback to Output Enable (Note 3)
18
24
ns
tER
Input, I/O, or Feedback to Output Disable (Note 3)
18
24
ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
2. See Switching Test Circuit for test conditions.
3. Parameters measured with 32 outputs switching.
16
MACH230-18/24 (Ind)
TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS
VCC = 5.0 V, TA = 25°C
IOL (mA)
80
60
40
20
VOL (V)
–1.0 –0.8 –0.6 –0.4 –0.2
–20
.2
.4
.6
.8
1.0
–40
–60
–80
14132I-4
Output, LOW
IOH (mA)
25
1
2
3
4
5
VOH (V)
–3
–2
–1
–25
–50
–75
–100
–125
–150
14132I-5
Output, HIGH
II (mA)
20
VI (V)
–2
–1
–20
1
2
3
4
5
–40
–60
–80
–100
14132I-6
Input
MACH230-10/15/20
17
TYPICAL ICC CHARACTERISTICS
VCC = 5 V, TA = 25°C
300
MACH230
275
250
225
200
175
ICC (mA)
150
125
100
75
50
25
0
0
10
20
30
40
50
60
70
Frequency (MHz)
14132I-7
The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of
being loaded, enabled, and reset.
Maximum frequency shown uses internal feedback and a D-type register.
18
MACH230-10/15/20
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
Parameter
Symbol
Parameter Description
Typ
PLCC
Units
θjc
Thermal impedance, junction to case
5
°C/W
θja
Thermal impedance, junction to ambient
20
°C/W
200 lfpm air
17
°C/W
400 lfpm air
14
°C/W
600 lfpm air
12
°C/W
800 lfpm air
10
°C/W
θjma
Thermal impedance, junction to
ambient with air flow
Plastic θjc Considerations
The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the
package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a
constant temperature. Therefore, the measurements can only be used in a similar environment.
MACH230-10/15/20
19
SWITCHING WAVEFORMS
Input, I/O, or
Feedback
VT
tPD
Combinatorial
Output
VT
14132I-8
Combinatorial Output
Input, I/O,
or Feedback
Input, I/O, or
Feedback
VT
tS
VT
tH
tSL
Gate
VT
Clock
tHL
tCO
Registered
Output
VT
tPDL
tGO
Latched
Out
VT
VT
14132I-9
14132I-10
Registered Output
Latched Output (MACH 2, 3, and 4)
tWH
Clock
Gate
VT
tGWS
tWL
14132I-12
14132I-11
Clock Width
Registered
Input
VT
tSIR
Input
Register
Clock
Gate Width (MACH 2, 3, and 4)
Registered
Input
tHIR
Input
Register
Clock
VT
tICO
Combinatorial
Output
VT
14132I-13
Output
Register
Clock
Registered Input (MACH 2 and 4)
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
20
VT
MACH230-10/15/20
VT
tICS
VT
14132I-14
Input Register to Output Register Setup
(MACH 2 and 4)
SWITCHING WAVEFORMS
Latched
In
VT
tSIL
tHIL
Gate
VT
tIGO
Combinatorial
Output
VT
14132I-15
Latched Input (MACH 2 and 4)
tPDLL
Latched
In
VT
Latched
Out
Input
Latch Gate
VT
tIGOL
tSLL
tIGS
VT
Output
Latch Gate
14132I-16
Latched Input and Output
(MACH 2, 3, and 4)
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
MACH230-10/15/20
21
SWITCHING WAVEFORMS
tWICH
Clock
Input
Latch
Gate
VT
VT
tWICL
tWIGL
14132I-18
14132I-17
Input Register Clock Width
(MACH 2 and 4)
Input Latch Gate Width
(MACH 2 and 4)
tARW
tAPW
Input, I/O, or
Feedback
Input, I/O,
or Feedback
VT
VT
tAR
Registered
Output
tAP
Registered
Output
VT
VT
tARR
Clock
tAPR
Clock
VT
VT
14132I-19
14132I-20
Asynchronous Reset
Asynchronous Preset
Input, I/O, or
Feedback
VT
tER
Outputs
tEA
VOH - 0.5V
VOL + 0.5V
VT
14132I-21
Output Disable/Enable
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
22
MACH230-10/15/20
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUIT
5V
S1
R1
Output
Test Point
R2
CL
14132I-22
Commercial
Specification
tPD, tCO
tEA
tER
S1
CL
R1
R2
Closed
Measured
Output Value
1.5 V
Z → H: Open
Z → L: Closed
35 pF
H → Z: Open
L → Z: Closed
5 pF
1.5 V
300 Ω
390 Ω
H → Z: VOH – 0.5 V
L → Z: VOL + 0.5 V
*Switching several outputs simultaneously should be avoided for accurate measurement.
MACH230-10/15/20
23
fMAX PARAMETERS
The parameter fMAX is the maximum clock rate at which
the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, fMAX is specified for
three types of synchronous designs.
The first type of design is a state machine with feedback
signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external
feedback or in conjunction with an equivalent speed device. This fMAX is designated “fMAX external.”
The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the
internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is
designated “fMAX internal”. A simple internal counter is a
good example of this type of design; therefore, this parameter is sometimes called “fCNT.”
The third type of design is a simple data path application. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
data setup time and the data hold time (tS + tH). However,
a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum
clock period determines the period for the third fMAX, designated “fMAX no feedback.”
For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no
feedback, it is calculated the same way as fMAX no feedback. The minimum period will be limited either by the
sum of the setup and hold times (tSIR + tHIR) or the sum of
the clock widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is specified
as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same path, the overall frequency will
be limited by tICS.
All frequencies except fMAX internal are calculated from
other measured AC parameters. fMAX internal is measured directly.
CLK
CLK
(SECOND
CHIP)
LOGIC
LOGIC
REGISTER
tS
t CO
tS
fMAX Internal (fCNT)
fMAX External; 1/(tS + tCO)
LOGIC
REGISTER
CLK
CLK
REGISTER
REGISTER
tS
tSIR
fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL)
LOGIC
tHIR
fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)
14132I-23
24
MACH230-10/15/20
ENDURANCE CHARACTERISTICS
The MACH families are manufactured using our
advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in
bipolar parts. As a result, the device can be erased and
reprogrammed, a feature which allows 100% testing at
the factory.
Endurance Characteristics
Parameter
Symbol
tDR
N
Parameter Description
Min
Units
Test Conditions
10
Years
Max Storage
Temperature
Min Pattern Data Retention Time
20
Years
Max Operating
Temperature
Max Reprogramming Cycles
100
Cycles
Normal Programming
Conditions
MACH230-10/15/20
25
INPUT/OUTPUT EQUIVALENT SCHEMATICS
VCC
100 kΩ
1 kΩ
VCC
ESD
Protection
Input
VCC
VCC
100 kΩ
1 kΩ
Preload
Circuitry
Feedback
Input
14132I-24
I/O
26
MACH230-10/15/20
POWER-UP RESET
The MACH devices have been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state
will depend on the logic polarity. This feature provides
extra flexibility to the designer and is especially valuable
in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the
synchronous operation of the power-up reset and the
Parameter
Symbol
wide range of ways VCC can rise to its steady state, two
conditions are required to insure a valid power-up reset.
These conditions are:
1. The VCC rise must be monotonic.
2. Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter Descriptions
Max
Unit
tPR
Power-Up Reset Time
10
µs
tS
Input or Feedback Setup Time
tWL
Clock Width LOW
See
Switching
Characteristics
VCC
Power
4V
tPR
Registered
Output
tS
Clock
tWL
14132I-25
Power-Up Reset Waveform
MACH230-10/15/20
27
USING PRELOAD AND OBSERVABILITY
In order to be testable, a circuit must be both controllable
and observable. To achieve this, the MACH devices
incorporate register preload and observability.
Preloaded
HIGH
D
In preload mode, each flip-flop in the MACH device can
be loaded from the I/O pins, in order to perform
functional testing of complex state machines. Register
preload makes it possible to run a series of tests from a
known starting state, or to load illegal states and test for
proper recovery. This ability to control the MACH
device’s internal state can shorten test sequences,
since it is easier to reach the state of interest.
Q1
Q
AR
Preloaded
HIGH
The observability function makes it possible to see the
internal state of the buried registers during test by
overriding each register’s output enable and activating
the output buffer. The values stored in output and buried
registers can then be observed on the I/O pins. Without
this feature, a thorough functional test would be
impossible for any designs with buried registers.
D Q2
Q
AR
While the implementation of the testability features is
fairly straightforward, care must be taken in certain
instances to insure valid testing.
One case involves asynchronous reset and preset. If the
MACH registers drive asynchronous reset or preset
lines and are preloaded in such a way that reset or
preset are asserted, the reset or preset may remove the
preloaded data. This is illustrated in Figure 2. Care
should be taken when planning functional tests, so that
states that will cause unexpected resets and presets are
not preloaded.
Another case to be aware of arises in testing combinatorial logic. When an output is configured as combinatorial, the observability feature forces the output into
registered mode. When this happens, all product terms
are forced to zero, which eliminates all combinatorial
data. For a straight combinatorial output, the correct
value will be restored after the preload or observe
function, and there will be no problem. If the function
implements a combinatorial latch, however, it relies on
feedback to hold the correct value, as shown in
Fugure 3. As this value may change during the preload
or observe operation, you cannot count on the data
being correct after the operation. To insure valid testing
in these cases, outputs that are combinatorial latches
should not be tested immediately following a preload or
observe sequence, but should first be restored to a
known state.
On
Preload
Mode
Off
Q1
AR
Q2
Figure 2. Preload/Reset Conflict
14132I-26
Set
All MACH 2 devices support both preload and
observability.
Contact individual programming vendors in order to
verify programmer support.
Reset
Figure 3. Combinatorial Latch
14132I-27
28
MACH230-10/15/20
PHYSICAL DIMENSIONS*
PL 084
84-Pin Plastic Leaded Chip Carrier (measured in inches)
1.185
1.195
1.150
1.156
.042
.056
.062
.083
1.090
1.130
1.000
REF
Pin 1 I.D.
1.185
1.195
1.150
1.156
.013
.021
.026
.032
.050 REF
.007
.013
TOP VIEW
.090
.130
.165
.180
SEATING PLANE
SIDE VIEW
16-038-SQ
PL 084
DF79
8-1-95 ae
*For reference only. BSC is an ANSI standard for Basic Space Centering.
MACH230-10/15/20
33