SN74ALS229B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS090 – MARCH 1990 – REVISED JUNE 1992 D D D D D D Independent Asychronous Inputs and Outputs 16 Words by 5 Bits Data Rates From 0 to 40 MHz Fall-Through Time . . . 14 ns Typ 3-State Outputs Package Options Include Plastic Small-Outline Packages (DW), Plastic Chip Carriers (FN), and Standard Plastic 300-mil DIPs (N) description DW OR N PACKAGE (TOP VIEW) OE FULL–2 FULL LDCK D0 D1 D2 D3 D4 GND This 80-bit memory uses advanced low-power Schottky technology and features high speed and fast fall-through times. It is organized as 16 words by 5 bits. Data is written into memory on a low-to-high transition at the load clock (LDCK) input and is read out on a low-to-high transition at the unload clock (UNCK). The memory is full when the number of words clocked in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect. When the memory is empty, UNCK signals have no effect. 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC EMPTY+2 UNCK EMPTY Q0 Q1 Q2 Q3 Q4 RST FULL FULL–2 OE VCC EMPTY+2 FN PACKAGE (TOP VIEW) LDCK D0 D1 D2 D3 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 UNCK EMPTY Q0 Q1 Q2 D4 GND RST Q4 Q3 A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. This FIFO is designed to process data at rates from 0 to 40 MHz in a bit-parallel format, word by word. 1 Status of the FIFO memory is monitored by the FULL, EMPTY, FULL–2, and FULL+2 output flags. The FULL output is low when the memory is full and high when it is not full. The FULL–2 output is low when the memory contains 14 data words. The EMPTY output is low when the memory is empty and high when it is not empty. The EMPTY+2 output is low when two words remain in memory. A low level on the reset (RST) input resets the internal stack control pointers and also sets EMPTY low and sets FULL, FULL–2, and EMPTY+2 high. The Q outputs are not reset to any specific logic level. The first low-to-high transition on LDCK after either a RST pulse or from an empty condition causes EMPTY to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Data outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the output flags. Cascading is easily accomplished in the word-width direction but is not possible in the word-depth direction. The SN74ALS229B is characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1992, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALS229B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS090 – MARCH 1990 – REVISED JUNE 1992 logic symbol† FIFO 16 × 5 CTR RST LDCK UNCK OE D0 D1 D2 D3 D4 11 4 18 CT = 0 CT = 14 1(+/C2) 3– 1 5 6 (CT = 16) G1 CT = 2 (CT = 0) G3 3 2 19 17 FULL FULL–2 EMPTY+2 EMPTY EN4 2D 4 16 15 7 14 8 13 9 12 Q0 Q1 Q2 Q3 Q4 † This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. The symbol is functionally accurate but does not show the details of implementation; for these, see the logic diagram. The symbol represents the memory as if it were controlled by a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is 0. Pin numbers shown are for the DW and N packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS229B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS090 – MARCH 1990 – REVISED JUNE 1992 logic diagram (positive logic) OE 1 Ring Counter CTR DIV 16 1D 4 C1 LDCK S R 18 Ring Counter CTR DIV 16 1 2 3 4 5 6 7 8 + 9 10 Read 11 Address 12 13 14 CT = 1 15 16 C1 UNCK 1 2 3 4 5 6 7 8 + 9 10 Write 11 Address 12 13 14 CT = 1 15 16 1D 11 RST 16 RAM 16 × 5 EN 16 16 1A 1 16 2A 1 16 C3 D0 D1 D2 D3 D4 16 5 1A, 3D 6 2A 16 15 7 14 8 13 9 12 16 Q0 Q1 Q2 Q3 Q4 COMP P=Q 17 P Q EMPTY S P=Q+2 3 P=Q–2 R 2 19 FULL FULL–2 EMPTY+2 Pin numbers shown are for the DW and N packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALS229B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS090 – MARCH 1990 – REVISED JUNE 1992 timing diagram RST LDCK ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D0 – D4 W1 W2 Don’t Care W3 W1 W2 W3 W14 W15 W16 UNCK Q0 – Q4 Invalid Word 1 Word 2 Word 3 Invalid Word 1 Word 2 Word 3 Word 4 EMPTY EMPTY+2 FULL FULL – 2 Initialize Pointers Unload W2 Empty Empty + 2 Full – 2 Full Load W1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS229B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS090 – MARCH 1990 – REVISED JUNE 1992 recommended operating conditions (see Note 1) VCC VIH Supply voltage VIL Low-level input voltage IOH High level output current High-level IOL Low level output current Low-level fclock l k Clock frequency High-level input voltage tw Pulse duration tsu Setup time th TA Hold time MIN NOM MAX 4.5 5 5.5 2 Q outputs – 1.6 Status flags – 0.4 Q outputs 24 Status flags 8 LDCK 0 40 UNCK 0 40 18 LDCK low 15 LDCK high 10 UNCK low 15 UNCK high 10 Data before LDCK↑ 8 RST (inactive) before LDCK↑ 5 LDCK (inactive) before RST↑ 5 Data after LDCK↑ 5 Operating free-air temperature V V 0.8 RST low UNIT V mA mA MHz ns ns ns 0 70 °C NOTE 1: To ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCK and UNCK clock inputs. Any excessive noise or glitching on the clock inputs that violates the VIL, VIH, or minimum pulse duration limits can cause a false clock or improper operation of the internal read and write pointers. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH Q outputs Status flags Q outputs VOL Status flags IOZH IOZL II IIH IIL IO‡ TEST CONDITIONS MIN TYP† MAX UNIT – 1.2 V VCC = 4.5 V, VCC = 4.5 V, II = – 18 mA IOL = – 2.6 mA VCC = 4.5 V to 5.5 V, VCC = 4.5 V, IOL = – 0.4 mA IOL = 12 mA 0.25 0.4 VCC = 4.5 V, VCC = 4.5 V, IOL = 24 mA IOL = 4 mA 0.35 0.5 0.25 0.4 VCC = 4.5 V, VCC = 5.5 V, IOL = 8 mA VO = 2.7 V 0.35 0.5 VCC = 5.5 V, VCC = 5.5 V, VO = 0.4 V VI = 7 V VCC = 5.5 V, VCC = 5.5 V, VI = 2.7 V VI = 0.4 V 2.4 3.2 V VCC – 2 20 V µA – 20 µA 0.1 mA 20 µA – 0.2 mA VCC = 5.5 V, VO = 2.25 V – 30 – 112 mA ICC VCC = 5.5 V 85 140 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALS229B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS090 – MARCH 1990 – REVISED JUNE 1992 switching characteristics (see Figure 1) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = 0°C to 70°C PARAMETER FROM (INPUT) fmax LDCK, UNCK 40 LDCK↑ 6 30 6 30 5 25 6 27 5 26 7 33 9 35 9 33 7 33 9 35 MIN tpd d tPLH tPHL tPHL tpd d tPLH tpd d tPLH tPHL tPLH ten tdis 6 UNCK↑ Any Q LDCK↑ UNCK↑ RST↓ EMPTY EMPTY LDCK↑ UNCK↑ RST↓ EMPTY 2 EMPTY+2 EMPTY+2 LDCK↑ UNCK↑ FULL 2 FULL– UNIT MAX MHz ns ns ns ns ns ns RST↓ FULL– 2 9 33 ns LDCK↑ FULL 6 27 ns 5 25 8 31 UNCK↑ FULL RST↓ ns OE↑ Q 2 15 ns OE↓ Q 1 15 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS229B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS090 – MARCH 1990 – REVISED JUNE 1992 PARAMETER MEASUREMENT INFORMATION 7V SWITCH POSITION TABLE Open S1 R1 = 500 Ω From Output Under Test CL = 50 pF (see Note A) Test Point R2 = 500 Ω TEST S1 tPLH tPHL Open Open tPZH tPZL Open Closed tPHZ Open tPLZ Closed LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V 0.3 V tw 3.5 V Timing Input 1.3 V 0.3 V th tsu 1.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATION 1.3 V 1.3 V 3.5 V Low-Level Pulse 3.5 V Data Input 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3.5 V Output Control 1.3 V tPZL 1.3 V tPLZ 0.3 V tPHL tPLH In-Phase Output VOH 1.3 V VOL 1.3 V Out-of-Phase Output 3.5 V Waveform 1 S1 Closed (see Note C) VOH 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.3 V tPHZ tPLH tPHL 1.3 V 0.3 V 3.5 V Input (see Note B) 1.3 V tPZH Waveform 2 S1 Open (see Note C) VOL 0.3 V VOH 1.3 V 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ALS229B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS090 – MARCH 1990 – REVISED JUNE 1992 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74ALS229BDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS229BN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ALS229BN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ALS229BN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Low Power Wireless www.ti.com/lpw Mailing Address: Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2007, Texas Instruments Incorporated