54ACT16543, 74ACT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B – MARCH 1990 – REVISED APRIL 1996
D
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
3-State True Outputs
Flow-Through Architecture Optimizes
PCB Layout
Distributed VCC and GND Pin
Configurations Minimize High-Speed
Switching Noise
EPIC t (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings, and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’ACT16543 are 16-bit registered transceivers
that contain two sets of D-type latches for
temporary storage of data flowing in either
direction. The ’ACT16543 can be used as two
8-bit transceivers or one 16-bit transceiver.
Separate latch enable (LEAB or LEBA) and
output-enable (OEAB or OEBA) inputs are
provided for each register to permit independent
control in either direction of data flow.
54ACT16543 . . . WD PACKAGE
74ACT16543 . . . DGG OR DL PACKAGE
(TOP VIEW)
1OEAB
1LEAB
1CEAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2CEAB
2LEAB
2OEAB
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2CEBA
2LEBA
2OEBA
The A-to-B enable (CEAB) and OEAB inputs must
be low to enter data from A or to output data to B.
Having CEAB low and LEAB low makes the
A-to-B latches transparent; a subsequent low-tohigh transition at LEAB puts the A latches in the
storage mode. Data flow from B to A is similar, but
requires using the CEBA, LEBA, and OEBA
inputs.
The 74ACT16543 is packaged in TI’s shrink small-outline package, which provides twice the functionality of
standard small-outline packages in the same printed-circuit-board area.
The 54ACT16543 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16543 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
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1
54ACT16543, 74ACT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B – MARCH 1990 – REVISED APRIL 1996
FUNCTION TABLE
(each octal register)
INPUTS
OEAB
LATCH
STATUS
A TO B†
OUTPUT
BUFFERS
B1–B8
Z
CEAB
LEAB
H
X
X
Storing
X
H
X
Storing
X
X
H
L
L
L
Z
Transparent
Current A data
L
H
L
Storing
Previous A data}
† A-to-B data flow is shown: B-to-A flow control is the same except that
it uses CEBA, LEBA, and OEBA.
‡ Data present before low-to-high transition of LEAB occurring while
CEAB is low
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
54ACT16543, 74ACT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B – MARCH 1990 – REVISED APRIL 1996
logic symbol†
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
56
54
55
1
G1
1C5
2EN4
3
G2
2
2C6
29
31
30
28
26
27
2LEAB
1A1
1EN3
7EN9
G7
7C11
8EN10
G8
8C12
5
3
6D
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
6
2A3
2A4
2A5
2A6
2A7
2A8
4
52
51
8
49
9
48
10
47
12
45
13
44
14
43
15
9
12D
2A2
5D
16
11D
10
42
41
17
40
19
38
20
37
21
36
23
34
24
33
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
54ACT16543, 74ACT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B – MARCH 1990 – REVISED APRIL 1996
logic diagram (positive logic)
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A1
56
54
55
1
3
2
C1
5
1D
52
1B1
C1
1D
To Seven Other Channels
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2A1
29
31
30
28
26
27
C1
15
1D
C1
1D
To Seven Other Channels
4
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• DALLAS, TEXAS 75265
42
2B1
54ACT16543, 74ACT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B – MARCH 1990 – REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DGG package . . . . . . . . . . . . . . . . . . 1 W
DL package . . . . . . . . . . . . . . . . . . . 1.4 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16543
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage (see Note 4)
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
Dt/Dv
Low-level output current
High-level input voltage
74ACT16543
MIN
2
2
0.8
Input transition rise or fall rate
0
TA
Operating free-air temperature
–55
NOTES: 3. Unused pins (inputs and I/O) must be held high or low to prevent them from floating.
4. All VCC and GND pins must be connected to the proper voltage power supply.
UNIT
V
V
0.8
V
VCC
VCC
V
–24
–24
mA
24
24
mA
VCC
VCC
0
0
V
10
0
10
ns/V
125
–40
85
°C
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
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5
54ACT16543, 74ACT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B – MARCH 1990 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
4.5 V
IOH = –50
50 mA
VOH
24 mA
IOH = –24
IOH = –75 mA{
MIN
TA = 25°C
TYP
MAX
IOL = 24 mA
54ACT16543
MIN
MAX
74ACT16543
MIN
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.8
3.8
5.5 V
4.94
5.5 V
IOL = 50 mA
VOL
VCC
4.8
4.8
3.85
3.85
MAX
UNIT
V
4.5 V
0.1
0.1
5.5 V
0.1
0.1
0.1
0.1
4.5 V
0.36
0.44
0.44
5.5 V
0.36
0.44
0.44
1.65
1.65
V
II
Control inputs
IOL = 75 mA{
VI = VCC or GND
5.5 V
±0.1
±1
±1
mA
IOZ
A or B ports}
VO = VCC or GND
5.5 V
±0.5
±5
±5
mA
VI = VCC or GND,
IO = 0
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
8
80
80
mA
5.5 V
0.9
1
1
mA
ICC
DICCw
Ci
Control inputs
Cio
A or B ports
VI = VCC or GND
VO = VCC or GND
5.5 V
5V
4.5
5V
12
pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
TA = 25°C
MIN
MAX
MIN
MAX
74ACT16543
MIN
MAX
UNIT
tw
tsu
Pulse duration, LEAB or LEBA low
7.5
7.5
7.5
ns
Setup time, data before LEAB or LEBA↑
2.5
2.5
2.5
ns
th
Hold time, data after LEAB or LEBA↑
4
4
4
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
54ACT16543
POST OFFICE BOX 655303
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54ACT16543, 74ACT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B – MARCH 1990 – REVISED APRIL 1996
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPLH
tPHL
LEBA or LEAB
A or B
tPZH
tPZL
OEBA or OEAB
A or B
tPHZ
tPLZ
OEBA or OEAB
A or B
tPZH
tPZL
CEBA or CEAB
A or B
tPHZ
tPLZ
CEBA or CEAB
A or B
MIN
TA = 25°C
TYP
MAX
54ACT16543
74ACT16543
MIN
MAX
MIN
MAX
3.5
6.9
9.5
3.5
10.5
3.5
10.5
3.1
7.3
10.7
3.1
11.6
3.1
11.6
3.9
8.6
12.3
3.9
13.8
3.9
13.8
3.9
8.7
12.2
3.9
13.5
3.9
13.5
2.6
7.1
10.3
2.6
11.4
2.6
11.4
3.5
8.3
11.9
3.5
13.2
3.5
13.2
4.1
8.2
10.5
4.1
11.1
4.1
11.1
5
7.3
9.3
5
9.6
5
9.6
3.1
7.3
10.7
3.1
11.7
3.1
11.7
3.9
8.5
12.2
3.9
13.5
3.9
13.5
4.6
8.5
11
4.6
11.6
4.6
11.6
5.2
7.4
9.7
5.2
10.5
5.2
10.5
UNIT
ns
ns
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
Power dissipation capacitance per transceiver
TEST CONDITIONS
Outputs enabled
Outputs disabled
pF
CL = 50 pF,
f = 1 MHz
TYP
45
12
UNIT
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
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54ACT16543, 74ACT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B – MARCH 1990 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
3V
Timing Input
(see Note B)
1.5 V
0V
tw
tsu
3V
Input
1.5 V
1.5 V
th
3V
1.5 V
1.5 V
Data Input
0V
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
3V
Input
1.5 V
1.5 V
0V
tPHL
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
3V
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
1.5 V
0V
tPZL
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
tPHL
Out-of-Phase
Output
Output
Control
(low-level
enabling)
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74ACT16543DGGR
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74ACT16543DGGRE4
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74ACT16543DL
ACTIVE
SSOP
DL
56
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74ACT16543DLR
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74ACT16543DLRG4
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
20
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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