ICS91718 Integrated Circuit Systems, Inc. Low EMI, Spread Modulating, Clock Generator Features: • ICS91718 is a Spread Spectrum Clock targeted for Mobile PC and LCD panel applications. Generates an EMI optimized clock signal (EMI peak reduction of 7-14 dB on 3rd-19th harmonics) through use of Spread Spectrum techniques. • ICS91718 operates with input frequencies at 14.318 - 80 MHz. • Spread modulation frequency range is 20kHz to 40kHz. • Spread percentage/type programming through I2C. Specifications: • Supply Voltages: VDD = 3.3V ±0.3V • Cyc to Cyc jitter: <150ps • Output duty cycle 45/55% • Guarantees +85°C operational condition • 8-pin SOIC (150 mil) package Pin Configuration CLKIN VDD GND **CLKOUT/FS_IN0 PD# FS_IN0:1 SD SDATA SCLK Control Logic Config. Reg. 0500D—07/15/04 PD#* SCLK SDATA REF_OUT/FS_IN1** 8-pin SOIC & TSSOP Input Select Functionality FS_IN1 FS_IN0 0 0 0 1 1 0 1 1 REFOUT PLL1 Spread Spectrum Spectr um 8 7 6 5 Notes: * Internal pull-up resistor ** Internal pull-down resistor Block Diagram CLKIN 1 2 3 4 CLKOUT CLK OUT MHz 14.318 in 48.00 out 14.318 in 66.66 out 48.00 in/out 66.66 in/out 48.00 in/out 66.66 in/out SPREAD % -1.0% down sprd -1.0% down sprd -1.0% down sprd +/-1.0% center sprd ICS91718 Pin Descriptions PIN # 1 2 3 PIN NAME CLKIN VDD GND 4 **CLKOUT/FS_IN0 5 REF_OUT/FS_IN1** 6 7 SDATA SCLK 8 PD#* PIN DESCRIPTION TYPE IN Input clock PWR Power supply, nominal 3.3V PWR Ground pin. CLKOUT modulated clock output I/O FS_IN0 latched input, selects modulation percentage/type REF_OUT, unmodulated reference clock output I/O FS_IN1 latched input, selects modulation percentage/type I/O Data pin for I2C circuitry 5V tolerant IN Clock pin of I2C circuitry 5V tolerant Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the IN crystal are stopped. The latency of the power down will not be greater than 1.8ms. * Internal Pull-Up Resistor ** Internal Pull-Down Resistor 0500D—07/15/04 2 ICS91718 Table 1: Frequency Configuration Table (See I2C Byte 0) 14in/48out 14in/66out 48in/48out 66in/66out FS4 FS3 FS2 FS1 FS0 Sprd Type Sprd % 0 0 0 0 0 0.80 0 0 0 0 1 1.00 DOWN 0 0 0 1 0 1.25 SPREAD 0 0 0 1 1 1.50 (-) 0 0 1 0 0 1.75 0 0 1 0 1 2.00 0 0 1 1 0 2.50 0 0 1 1 1 0.60 CENTER 0 1 0 0 0 1.00 SPREAD 0 1 0 0 1 1.25 (+/-) 0 1 0 1 0 1.50 0 1 0 1 1 2.00 0 1 1 0 0 1.25 DOWN 0 1 1 0 1 1.00 SPREAD 0 1 1 1 0 1.50 (-) 0 1 1 1 1 2.00 1 0 0 0 0 0.80 1 0 0 0 1 1.00 1 0 0 1 0 1.25 DOWN 1 0 0 1 1 1.50 SPREAD 1 0 1 0 0 1.75 (-) 1 0 1 0 1 2.00 1 0 1 1 0 2.50 1 0 1 1 1 3.00 1 1 0 0 0 0.30 1 1 0 0 1 0.40 1 1 0 1 0 0.50 CENTER 1 1 0 1 1 0.60 SPREAD 1 1 1 0 0 0.80 (+/-) 1 1 1 0 1 1.00 1 1 1 1 0 1.25 1 1 1 1 1 1.50 For 14.318 in 48.008 out default is… ..00001 For 14.318 in 66.66 out default is… … 01101 For 48/48 and 66/66 default is… … … .10001 0500D—07/15/04 3 ICS91718 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 • ICS clock will acknowledge each byte one at a time. • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 7 Controller (host) will need to acknowledge each byte • Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D4(H) How to Read: Controller (Host) Start Bit Address D5(H) ICS (Slave/Receiver) ACK ICS (Slave/Receiver) ACK Byte Count Dummy Command Code ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Dummy Byte Count Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 3 Byte 2 Byte 4 Byte 3 Byte 5 Byte 4 Byte 6 Byte 5 Byte 7 Byte 6 Byte 7 ACK Stop Bit Notes: 1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. 2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) 3. The input is operating at 3.3V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. 6. At power-on, all registers are set to a default condition, as shown. 0500D—07/15/04 4 Affected Pin BYTE 0 Pin # Name Control Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 - N/A N/A N/A N/A N/A N/A N/A FS0 FS1 FS2 FS3 FS4 PD# Tri_Sate Spread Enable Spread Spectrum Control FS 2:4 Hard/Software Select Bit 0 HW/SW Control Bit Control 0 1 1 0 0 0 0 1 1 RW 0 HW SW Bit Control 1 Pin # Name Control Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 5 REF_OUT REF_OUT FS_IN1 Readback FS_IN0 Readback CLK_OUT CLK_OUT Reserved Reserved REF_OUT ENABLE Slew Rate REF-OUT FS_IN1 Readback FS_IN0 Readback Slew Rate CLK-OUT CLK_OUT_Enable Reserved Reserved RW RW RW RW RW RW R R Disable Enable Nominal Fast Nominal Fast Disable Enable - Bit Control BYTE 4 4 Affected Pin 2 Pin # Name Control Function TYPE BYTE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 x x x x x x x x RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RW RW RW RW RW RW RW 0500D—07/15/04 5 PWD RW RW RW See ROM TABLE RW RW RW Hi-Z LOW RW OFF ON TYPE Affected Pin TYPE ICS91718 0 1 PWD 1 1 1 1 1 1 1 1 0 1 PWD Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable 1 1 1 1 1 1 1 1 Affected Pin BYTE 3 Pin # Name Control Function Bit 7 Bit 6 X X RESERVED RESERVED RESERVED RESERVED Bit 5 X RESERVED RESERVED Bit 4 X RESERVED RESERVED Bit 3 x RESERVED RESERVED Bit 2 Bit 1 Bit 0 X X RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED X Affected Pin 4 Pin # Name Control Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X X X X RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RW RW RW RW RW RW RW RW Affected Pin 5 Pin # Name Control Function TYPE BYTE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X X X X RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RW RW RW RW 0500D—07/15/04 6 Bit Control 0 1 RW Disable Enable RW Disable Enable Not RW Freerun Freerun Not RW Freerun Freerun Not RW Freerun Freerun RW Disable Enable RW Disable Enable RW Disable Enable TYPE BYTE TYPE ICS91718 PWD 1 1 1 1 1 1 1 1 Bit Control 0 1 PWD Disable Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable Enable 1 1 1 1 1 1 1 1 Bit Control 0 1 PWD Disable Disable Disable Disable Enable Enable Enable Enable 1 1 1 1 1 1 1 1 ICS91718 Affected Pin 6 Pin # Name Control Function TYPE BYTE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X X X X Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) R R R R R R R R Affected Pin 7 Pin # Name Control Function TYPE BYTE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X X X X DEVICE ID7 DEVICE ID6 DEVICE ID5 DEVICE ID4 DEVICE ID3 DEVICE ID2 DEVICE ID1 DEVICE ID0 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) R R R R R R R R Affected Pin 8 Pin # Name Control Function TYPE BYTE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X X X X Byte Count7 Byte Count6 Byte Count5 Byte Count4 Byte Count3 Byte Count2 Byte Count1 Byte Count0 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) R R R R R R R R 0500D—07/15/04 7 Bit Control 0 1 PWD - - 1 1 1 1 1 1 1 1 Bit Control 0 1 PWD - - 0 0 0 0 0 0 0 1 Bit Control 0 1 PWD - - 0 0 0 0 0 1 1 1 ICS91718 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Voltage on any pin with respect to GND . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . Operating Temperature . . . . . . . . . . . . . . . . . . Ambient Operating Temperature under Bias . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 3.3 V -0.5 to +7.0 V –55°C to +125°C 0°C to +85°C -55 to +125 °C 0.5 W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 85°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Supply Current Powerdown Current Pin Inductance Pin Capacitance1 Transition time1 Settling time1 Clk Stabilization1 Delay 1 1 SYMBOL CONDITIONS V IH V IL V IN = VDD IIH V IN = 0 V; Inputs with no pull-up resistors I IL1 f IN = 14.318MHz IDD f IN = 66.66MHz IDD3.3PD Lpin CIN Logic Inputs COUT Output pin capacitance Ttrans To 1st crossing of target frequency Ts From 1st crossing to 1% target frequency TSTAB From VDD = 3.3 V to 1% target frequency t PZH,t PZL Output enable delay (all outputs) MIN TYP 2 V SS - 0.3 -5 -5 27 42 3 MAX UNITS VDD + 0.3 V 0.8 V 5 µA µA 35 mA 50 mA mA 5 7 nH 5 pF 6 pF 3 ms 3 ms 1 3 10 TYP MAX 80 80 1 1 55 55 250 1 ms ns Guaranteed by design, not 100% tested in production. AC Electrical Characteristics TA = 0 - 70°C; Supply Voltage V DD = 3.3 V ±0.3V PARAMETER FIN f OUT tR tF IOD tID tJCYC DESCRIPTION Input Frequency Output Frequency Output Rise Time Output Fall Time Output Duty Cycle Input Duty Cycle Jitter, Cycle-to-Cycle TEST CONDITION Input Clock Spread Off 15 pF load, 0.8V - 2.4V 15 pF load, 2.4 - 0.8V 15 pf load 0500D—07/15/04 8 MIN 14.318 14.318 0.5 0.5 45 45 UNITS MHz MHz ns ns % % ps ICS91718 Electrical Characteristics - CLOCK_OUT TA = 0 - 85°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Current Source Output Impedance SYMBOL Output High Voltage Output Low Voltage Rise Time Fall Time VOH3 VOL3 tr3 tf3 Duty Cycle dt3 Jitter, Cycle to cycle tjcyc-cyc 1 Zo1 CONDITIONS V O = Vx IOH = -1 mA IOL = 1 mA VOL = 0.41V, VOH = 0.86V VOH = 0.86V VOL = 0.41V MIN MAX UNITS Ω V 3000 2.4 0.5 0.5 45 VT = 50% VT = 50% TYP 51 0.4 1 1 ns ns 55 % 250 ps 1 Guaranteed by design, not 100% tested in production. IOWT can be varied and is selectable thru the MULTSEL pin. 2 Electrical Characteristics - REF TA = 0 - 85°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Frequency SYMBOL FO1 Output Impedance RDSP11 Output High Voltage V OH1 V OL1 I OH1 I OL1 tr11 tf11 dt11 Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Accumulated Jitter Jitter t jlongterm t jcyc-cyc 1 CONDITIONS MIN V O = VDD*(0.5) 20 I OH = -1 mA 2.4 I OL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V V OL @MIN = 1.95 V, VOL @MAX = 0.4 V TYP MAX UNITS MHz 60 Ω V -29 29 0.4 -23 27 V mA mA V OL = 0.4 V, V OH = 2.4 V 0.5 1 ns V OH = 2.4 V, VOL = 0.4 V 0.5 1 ns V T = 1.5 V 45 55 % 2 ns 500 ps V T = 1.5 V 10us. V T = 1.5 V 1 Guaranteed by design, not 100% tested in production. 0500D—07/15/04 9 ICS91718 150 mil (Narrow Body) SOIC In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0.33 0.51 .013 .020 C 0.19 0.25 .0075 .0098 D SEE VARIATIONS SEE VARIATIONS E 3.80 4.00 .1497 .1574 e 0.050 BASIC 1.27 BASIC H 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 L 0.40 1.27 .016 .050 N SEE VARIATIONS SEE VARIATIONS a 0° 8° 0° 8° C N L INDEX AREA H E h x 45° 1 2 D α A A1 e SEATING PLANE B VARIATIONS .10 (.004) N 150mil Body, .50mil pitch 8 D mm. MIN 4.80 MAX 5.00 Reference Doc.: JEDEC Publication 95, MS-012 10-0030 Ordering Information ICS91718yMLF-T Example: ICS XXXX y M LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type M = SOIC Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0500D—07/15/04 10 D (inch) MIN MAX .1890 .1968 ICS91718 c N 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) L E1 INDEX AREA SYMBOL A A1 A2 b c D E E1 e L N a aaa E 1 2 α D A A2 N 8 -Cb In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 VARIATIONS A1 e (25.6 mil) In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0° 8° -0.10 SEATING PLANE aaa C D mm. MIN 2.90 D (inch) MAX 3.10 Reference Doc.: JEDEC Publication 95, MO-153 10-0035 Ordering Information ICS91718yGLF-T Example: ICS XXXX y G LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0500D—07/15/04 11 MIN .114 MAX .122