ICS ICS9250-38

ICS9250-38
Integrated
Circuit
Systems, Inc.
Frequency Generator with 200MHz Differential CPU Clocks
ICS9250-38
Recommended Application:
CK 408 clock for Almador-M mobile chipset with Tualatin
Pin Configuration
PIII processor.
VDDREF
1
56
REF
Output Features:
X1
2
55
FS1
•
3 Differential CPU Clock Pairs @ 3.3V
X2
3
54
FS0
GND
4
53
CPU_STOP#*
•
7 PCI (3.3V) @ 33.3MHz
PCICLK_F0
5
52
CPUCLKT0
PCICLK_F1
6
51
CPUCLKC0
•
3 PCI_F (3.3V) @ 33.3MHz
PCICLK_F2
7
50
VDDCPU
VDDPCI
8
49
CPUCLKT1
•
1 USB (3.3V) @ 48MHz
GND
9
48
CPUCLKC1
PCICLK0
10
47
GND
•
1 DOT (3.3V) @ 48MHz
PCICLK1
11
46
VDDCPU
PCICLK2
12
45
CPUCLKT2
•
1 REF (3.3V) @ 14.318MHz
PCICLK3
13
44
CPUCLKC2
•
1 3V66 (3.3V) @ 66.6MHz
VDDPCI
14
43
MULTSEL0*
GND
15
42
I REF
•
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
PCICLK4
16
41
GND
PCICLK5
17
40
FS2
•
3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN
PCICLK6
18
39
48MHz_USB
VDD3V66
19
38
48MHz_DOT
or 66.6MHz
GND
20
37
VDD48
•
1 66MHz_IN/3V66 (3.3V) @ Input/66MHz
66MHz_OUT0/3V66_2
21
36
GND
66MHz_OUT1/3V66_3
22
35
3V66_1/VCH_CLK
Features:
66MHz_OUT2/3V66_4
23
34
PCI_STOP#*
66MHz_IN/3V66_5
24
33
3V66_0
•
Almador Chipset has a DLL driving the clock buffer
*PD#
25
32
VDD3V66
path for the 3 buffer path 66.6 MHz outputs,
VDDA
26
31
GND
GND
27
30
SCLK
66Buf(0:2).
Vtt_PWRGD#
28
29
SDATA
Almador board level designs MUST use pin 22,
66Buf_1, as the feedback connection from the
clock buffer path to the Almador (GMCH)
56-Pin 300mil SSOP/TSSOP
chipset.
* These inputs have 150K internal pull-up resistor to VDD.
•
Supports spread spectrum modulation,
down spread 0 to -0.5%.
•
Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Key Specifications:
•
CPU Output Jitter <150ps
•
3V66 Output Jitter <250ps
•
66MHz Output Jitter (Buffered Mode Only) <100ps
Functionality
•
CPU Output Skew <100ps
Block Diagram
FS2
PLL2
XTAL
OSC
3V66_1/VCH_CLK
REF
66MHz_IN
PLL1
Spread
Spectrum
CPU
DIVDER
0404B—12/23/02
3
Stop
7
3
Control
Logic
Stop
3
PCI
DIVDER
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (2:0)
SDATA
SCLK
66MHz
DIVDER
3V66
DIVDER
3
5
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK (6:0)
PCICLK_F (2:0)
66Buff[2:0]
3V66[4:2]
(MHz)
PCI_F
PCI
(MHz)
0
0
0
66.66
66.66
66.66
33.33
0
0
1
100.00
66.66
66.66
33.33
0
1
0
200.00
66.66
66.66
33.33
0
1
1
133.33
66.66
66.66
33.33
1
0
0
66.66
66.66
66MHz_IN
66MHz_IN/2
1
0
1
100.00
66.66
66MHz_IN
66MHz_IN/2
1
1
0
200.00
66.66
66MHz_IN
66MHz_IN/2
66MHz_IN/2
1
1
1
133.33
66.66
66MHz_IN
66MHz_OUT (2:0)
Mid
0
0
Tristate
Tristate
Tristate
Tristate
3V66 (5:2,0)
Mid
0
1
TCLK/2
TCLK/4
TCLK/4
TCLK/8
Mid
1
0
Reserved Reserved Reserved
Reserved
I REF
Mid
1
1
Reserved Reserved Reserved
Reserved
Config.
Reg.
3V66
(MHz)
FS0
48MHz_USB
48MHz_DOT
X1
X2
CPU
(MHz)
FS1
ICS9250-38
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
1, 8, 14, 19, 26,
32, 37, 46, 50
VDD
PWR
2
X1
X2 Cr ystal Input
3
X2
X1 Cr ystal
Output
7, 6, 5
PCICLK_F (2:0)
OUT
Free running PCI clock not affected by PCI_STOP# for power
management as a function of the I2C stop control bits.
4, 9, 15, 20, 27,
31, 36, 41, 47
GND
PWR
Ground pins for 3.3V supply
18, 17, 16, 13,
12,11, 10
PCICLK (6:0)
OUT
PCI clock outputs
66MHz_OUT (2:0)
OUT
66MHz buffered 66MHz_OUT from 66MHz_IN input.
3V66 (4:2)
OUT
66MHz reference clocks, from internal VCO
66MHz_IN
IN
3V66_5
OUT
25
PD#
IN
Invokes power-down mode. Active Low.
28
Vtt_PWRGD#
IN
This 3.3V LVTTL input is a level sensitive strobe used to determine
when FS[0:2] and MULTISEL0 inputs are valid and are ready to be
sampled
(active low)
29
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
30
SCLK
IN
Clock pin of I2C circuitry 5V tolerant
33
3V66_0
OUT
23, 22, 21
24
DESCRIPTION
3.3V power supply
Cr ystal input,nominally 14.318MHz, with internal loading cap.
Cr ystal output, nominally 14.318MHz, with internal loading cap.
66MHz input to buffered 66MHz_OUT and PCI clocks
66MHz reference clock, from internal VCO
66MHz reference clocks, from internal VCO
Stops all PCICLKs at logic 0 level, when input low besides the PCICLK_F
clocks which are controllable by I2C bits whether they are free running or
stopped by PCI_STOP.
34
PCI_STOP#
IN
35
3V66_1/VCH_CLK
OUT
3.3V output selectable through I2C to be 66MHz from internal VCO or
48MHz (non-SSC)
38
48MHz_DOT
OUT
48MHz output clock for DOT
39
48MHz_USB
OUT
40
FS2
IN
42
I REF
OUT
43
MULTSEL0
IN
48MHz output clock for USB
Special 3.3V input for Mode selection
This pin establishes the reference current for the CPUCLK pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the
appropriate current.
3.3V LVTTL input for selecting the current multiplier for CPU outputs
44, 48, 51
CPUCLKC (2:0)
OUT
"Complementor y" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
45, 49, 52
CPUCLKT (2:0)
OUT
"True" clocks of differential pair CPU outputs. These are current outputs and
external resistors are required for voltage bias.
53
CPU_STOP#
IN
55, 54
FS (1:0)
IN
56
REF
OUT
Stops all CPUCLKs at logic 0 level, when input low. The individual CPU clocks
are controllable by I2C bits whether they are free running or stopped by
CPU_STOP.
Frequency select pins
14.318MHz reference clock.
Power Groups
(Analog)
VDDA = PLL1
VDD48 = 48MHz, PLL
VDDREF = VDD for Xtal, POR
(Digital)
VDDPCI
VDD3V66
VDDCPU
0404B—12/23/02
2
ICS9250-38
Truth Table
FS2
FS1
FS0
CPU
(MHz)
3V66
(1:0)
(MHz)
66Buff (2:0)
3V66 (4:2)
(MHz)
66MHz_IN/
3V66_5
PCI_F
PCI
(MHz)
REF0
(MHz)
USB/DOT
(MHz)
0
0
0
66.66
66.66
66.66
66.66
33.33
14.318
48.00
0
0
1
100.00
66.66
66.66
66.66
33.33
14.318
48.00
0
1
0
200.00
66.66
66.66
66.66
33.33
14.318
48.00
0
1
1
133.33
66.66
66.66
66.66
33.33
14.318
48.00
1
0
0
66.66
66.66
66MHz_IN
Input
66MHz_IN/2
14.318
48.00
1
0
1
100.00
66.66
66MHz_IN
Input
66MHz_IN/2
14.318
48.00
1
1
0
200.00
66.66
66MHz_IN
Input
66MHz_IN/2
14.318
48.00
1
1
1
133.33
66.66
66MHz_IN
Input
66MHz_IN/2
14.318
48.00
Mid
0
0
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
TCLK/2
TCLK/4
Mid
0
1
TCLK/4
TCLK/4
TCLK/8
TCLK
TCLK/2
Mid
1
0
Reser ved Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Mid
1
1
Reser ved Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Maximum Allowed Current
Condition
Max 3.3V supply consumption
Max discrete cap loads,
Vdd = 3.465V
All static inputs = Vdd or GND
Powerdown Mode
(PWRDWN# = 0)
40mA
Full Active
360mA
Host Swing Select Functions
MULTISEL0
Board Target
Trace/Term Z
Reference R,
Iref =
VDD/(3*Rr)
Output
Current
Voh @ Z
0
50 ohms
Rr = 221 1%,
Iref = 5.00mA
Ioh = 4* I REF
1.0V @ 50
1
50 ohms
Rr = 475 1%,
Iref = 2.32mA
Ioh = 6* I REF
0.7V @ 50
0404B—12/23/02
3
ICS9250-38
Byte 0: Control Register
Bit
Bit 0
Bit 1
Bit 2
Pin#
54
55
40
Name
FS0
FS1
FS2
Bit 3
34
PCI_STOP#3
PWD2
X
X
X
Type1
R
R
R
X
R
1
RW
Bit 4
53
CPU_STOP#
X
R
Bit 5
35
3V66_1/VCH
0
RW
Bit 6
Bit 7
-
Spread Enabled
0
0
RW
Description
Reflects the value of FS0 pin sampled on power up
Reflects the value of FS1 pin sampled on power up
Reflects the value of FS2 pin sampled on power up
Hardware mode: Reflects the value of PCI_STOP#
pin sampled on PWD
Software mode:
0=PCICLK stopped
1=PCICLK not stopped
Reflects the current value of the external
CPU_STOP# pin
VCH Select 66MHz/48MHz
0=66MHz, 1=48MHz
(Reser ved)
0=Spread Off, 1=Spread On
PWD2
Type1
Description
1
RW
0=Disabled 1=Enabled 4
1
RW
0=Disabled 1=Enabled
4
1
RW
0=Disabled 1=Enabled
4
0
RW
0
RW
0
RW
0
X
R
Byte 1: Control Register
Bit
Pin#
Bit 0
52, 51
Bit 1
49, 48
Bit 2
45, 44
Bit 3
52, 51
Bit 4
49, 48
Bit 5
45, 44
Bit 6
Bit 7
43
Name
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
CPUCLKT2
CPUCLKC2
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
CPUCLKT2
CPUCLKC2
MULTSEL0
Allow control of CPUCLKT0/C0 with asser tion of
CPU_STOP# 0=Not free running 1=Free running
Allow control of CPUCLKT1/C1 with asser tion of
CPU_STOP# 0=Not free running 1=Free running
Allow control of CPUCLKT2/C2 with asser tion of
CPU_STOP# 0=Not free running 1=Free running
(Reser ved)
Reflects the current value of MULTSEL0
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways.
Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert
PCI_STOP functionality via I2C Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the I2C Byte 0 Bit3. In Software mode it is not allowed to pull the
external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped
PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it
is not allowed to mix these modes.
In Hardware mode the I2C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip
is in PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I2C Byte 0 Bit 3 = 0)].
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
0404B—12/23/02
4
ICS9250-38
Byte 2: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
10
11
12
13
16
17
18
-
Name
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
-
PWD2
1
1
1
1
1
1
1
0
Type1
RW
RW
RW
RW
RW
RW
RW
-
Description
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
(Reser ved)
Description
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
Allow control of PCICLK_F0 with asser tion of
PCI_STOP#. 0=Free Running, 1=Not free running
Allow control of PCICLK_F1 with asser tion of
PCI_STOP#. 0=Free Running, 1=Not free running
Allow control of PCICLK_F2 with asser tion of
PCI_STOP#. 0=Free Running, 1=Not free running
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
Byte 3: Control Register
Bit
Bit 0
Bit 1
Bit 2
Pin#
5
6
7
Name
PCICLK_F0
PCICLK_F1
PCICLK_F2
PWD2
1
1
1
Type1
RW
RW
RW
Bit 3
5
PCICLK_F0
0
RW
Bit 4
6
PCICLK_F1
0
RW
Bit 5
7
PCICLK_F2
0
RW
Bit 6
Bit 7
39
38
48MHz_USB
48MHz_DOT
1
1
RW
RW
Byte 4: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
21
22
23
24
35
33
-
Name
3V66-2
3V66-3
3V66-4
3V66_5
3V66_1/VCH_CLK
3V66_0
-
PWD2
1
1
1
1
1
1
0
0
Type1
RW
RW
RW
RW
RW
RW
R
R
Description
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
(Reser ved)
(Reser ved)
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
0404B—12/23/02
5
ICS9250-38
Byte 5: Programming Edge Rate
(1 = enable, 0 = disable)
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Pin#
X
X
X
X
Name
48MHz_USB
48MHz_USB
48MHz_DOT
48MHz_DOT
PWD2
0
0
0
0
Type1
RW
RW
RW
RW
Bit 4
X
66MHz_OUT[2:0]
0
RW
Bit 5
X
66MHz_OUT[2:0]
0
RW
Bit 6
Bit 7
X
X
-
0
0
-
Name
Vendor ID Bit0
Vendor ID Bit1
Vendor ID Bit2
Vendor ID Bit3
Revision ID Bit0
Revision ID Bit1
Revision ID Bit2
Revision ID Bit3
PWD2
1
0
0
0
X
X
X
X
Type1
R
R
R
R
R
R
R
R
Description
USB edge rate cntrol
USB edge rate cntrol
DOT edge rate control
DOT edge rate control
Tpd 66MHz_IN to 66MHz_OUT
propagation delay control
Tpd 66MHz_IN to 66MHz_OUT
propagation delay control
(Reserved)
(Reserved)
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
X
X
X
X
X
X
X
X
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
0404B—12/23/02
6
Description
(Reser ved)
(Reser ved)
(Reser ved)
(Reser ved)
Revision ID values will be based on
individual device's revision
ICS9250-38
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High
Voltage
Input Low
Voltage
Input High
Current
Input Low
Current
Operating Supply
Current
Powerdown
Current
Input Frequency
Pin Inductance
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VIH
2
VDD + 0.3
V
VIL
VSS - 0.3
0.8
V
-5
5
mA
IIH
VIN = VDD
IIL1
IIL2
IDD3.3OP
IDD3.3OP
IDD3.3OP
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = Full load; Select @ 100 MHz
CL =Full load; Select @ 133 MHz
CL = Full load; Select @ 200 MHz
IDD3.3PD
IREF=2.32 mA
-5
-200
229
220
234
mA
240
236
245
360
360
360
mA
mA
mA
25
mA
7
5
6
45
3
MHz
nH
pF
pF
pF
ms
Transition time1
Fi
Lpin
CIN
COUT
CINX
Ttrans
Settling time1
Ts
From 1st crossing to 1% target frequency
3
ms
Clk Stabilization1
TSTAB
From VDD = 3.3 V to 1% target frequency
3
ms
10
10
ns
ns
Input
Capacitance1
VDD = 3.3 V
14.32
Logic Inputs
Output pin capacitance
X1 & X2 pins
To 1st crossing of target frequency
tPZH,tPZL Output enable delay (all outputs)
tPHZ,tPLZ Output disable delay (all outputs)
1
Guaranteed by design, not 100% tested in production.
Delay1
0404B—12/23/02
7
27
1
1
36
ICS9250-38
Electrical Characteristics - CPU
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Current Source
1
VO = Vx
Zo
Output Impedance
IOH = -1 mA
VOH3
Output High Voltage
Output Low Voltage
VOL3
Rise Time
Fall Time
Duty Cycle
Skew
tr3
tf3
dt3
tsk3
Jitter, Cycle to cycle
tjcyc-cyc1
1
2
MIN
TYP
MAX
UNITS
3000
Ω
2.4
V
IOL = 1 mA
0.4
VOL = 0.175V, VOH = 0.525V
VOH = 0.175V VOL = 0.525V
VT = 50%
VT = 50%
175
175
45
VT = 50%
298
380
50.9
50
700
700
55
100
ps
ps
%
ps
95
150
ps
Guaranteed by design, not 100% tested in production.
IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
1
IOH = -18mA
Output High Voltage
VOH
1
IOL = 9.4mA
Output Low Voltage
VOL
1
V OH = 2.0 V
Output High Current
IOH
1
VOL = 0.8 V
Output Low Current
IOL
1
VOL = 0.4 V, VOH = 2.4 V
Rise Time
tr1
1
VOH = 2.4 V, VOL = 0.4 V
Fall Time
tf1
1
VT = 1.5 V
Duty Cycle
dt1
1
VT = 1.5 V
Skew
tsk1
1
VT = 1.5 V
Jitter,cycle to cyc
tjcyc-cyc
1
Guaranteed by design, not 100% tested in production.
0404B—12/23/02
8
MIN
2.1
16
45
TYP
MAX
0.4
-22
57
2
2
55
500
500
UNITS
V
V
mA
mA
ns
ns
%
ps
ps
ICS9250-38
Electrical Characteristics- 3V66 - Buffered Mode: 3V66 [1:0] 66MHz_OUT [2:0]
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Frequency
FO1
VO = VDD*(0.5)
Output Impedance
RDSP11
1
Output High Voltage
VOH
IOH = -1 mA
IOL = 1 mA
Output Low Voltage
VOL1
1
V [email protected] = 1.0 V, V [email protected] = 3.135 V
Output High Current
IOH
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
Output Low Current
IOL1
1
VOL = 0.4 V, VOH = 2.4 V
Rise Time
tr1
VOH = 2.4 V, VOL = 0.4 V
Fall Time
tf11
1
Duty Cycle
VT = 1.5 V
dt1
1
1
Skew
tsk1
Jitter
Skew
Jitter
tjcyc-cyc1
tsk11
tadditive1
VT = 1.5 V
MIN
TYP
MAX
12
2.4
33
55
-33
30
0.5
0.5
1.28
1.35
0.4
-33
38
2
2
45
53
55
UNITS
MHz
Ω
V
V
mA
mA
ns
ns
%
109
500
ps
132
133
75
250
175
100
ps
ps
ps
3V66 [1:0]
VT = 1.5 V 3V66 [1:0]
VT = 1.5 V 66MHz_OUT [2:0]
VT = 1.5 V 66MHz_OUT [2:0]
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66 -Un-Buffered Mode: 3V66 [5:0]
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Output Frequency
Output Impedance
FO1
RDSP11
VO = VDD*(0.5)
12
33
Output High Voltage
VOH1
IOH = -1 mA
2.4
Output Low Voltage
VOL1
IOL = 1 mA
Output High Current
Output Low Current
Rise Time
1
Fall Time
Duty Cycle
MHz
Ω
V
0.55
V
mA
mA
ns
-33
30
0.5
1.28
-33
38
2
1
VOH = 2.4 V, VOL = 0.4 V
0.5
1.36
2
ns
1
VT = 1.5 V
45
53.1
55
%
90
250
ps
128
250
ps
dt1
1
VT = 1.5 V
tsk1
1
V
=
1.5 V 3V66
Jitter
tjcyc-cyc
T
1
Guaranteed by design, not 100% tested in production.
Skew
55
[email protected] = 1.0 V, V [email protected] = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
IOH
IOL1
tr11
tf1
MAX UNITS
0404B—12/23/02
9
ICS9250-38
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Frequency
FO1
Output Impedance
RDSP11 VO = VDD*(0.5)
Output High Voltage
VOH1 IOH = -1 mA
Output Low Voltage
VOL1
IOL = 1 mA
1
V [email protected] = 1.0 V, V [email protected] = 3.135 V
Output High Current
IOH
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
Output Low Current
IOL1
1
48DOT Rise Time
tr1
VOL = 0.4 V, VOH = 2.4 V
48DOT Fall Time
tf11
VOH = 2.4 V, VOL = 0.4 V
1
VCH 48 USB Rise Time
tr1
VOL = 0.4 V, VOH = 2.4 V
1
VCH 48 USB Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
1
Duty Cycle
VT = 1.5 V
dt1
tjcyc-cyc1 VT = 1.5 V
Jitter
1
MIN
TYP
MAX
20
2.4
48
60
677
952
1.11
1.28
0.4
-23
27
1
1
2
2
53
194
55
350
-29
29
0.5
0.5
1
1
45
UNITS
MHz
Ω
V
V
mA
mA
ns
ns
ns
ns
%
ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Frequency
FO1
VO = VDD*(0.5)
Output Impedance
RDSP11
1
IOH = -1 mA
Output High Voltage
VOH
IOL = 1 mA
Output Low Voltage
VOL1
1
V [email protected] = 1.0 V, V [email protected] = 3.135 V
Output High Current
IOH
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
Output Low Current
IOL1
1
VOL = 0.4 V, VOH = 2.4 V
Rise Time
tr1
VOH = 2.4 V, VOL = 0.4 V
Fall Time
tf11
1
Duty Cycle
VT = 1.5 V
dt1
1
tjcyc-cyc
VT = 1.5 V
Jitter
1
Guaranteed by design, not 100% tested in production.
0404B—12/23/02
10
MIN
TYP
20
2.4
48
-29
29
1
1
45
1.25
1.21
52.2
675
MAX
UNITS
MHz
60
Ω
V
0.4
V
-23
mA
27
mA
2
ns
2
ns
%
55
1000
ps
ICS9250-38
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
Dummy Command Code
ACK
ICS (Slave/Receiver)
ACK
Byte Count
Dummy Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Byte 6
Byte 6
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
0404B—12/23/02
11
ICS9250-38
Buffered Mode - 3V66[0:1], 66MHz_IN, 66MHz_OUT[0:2] and PCI Phase Relationship
All 3V66 clocks are to be in phase with each other. All 66MHz_OUT clocks are to be in phase with each other. There
is NO phase relationship between the 3V66 clocks and the 66MHz_OUT and PCI clocks. In the case where 3V66_1
is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks.
The PCI group should lag 3V66 by the standard skew described below as Tpci.
The 66MHz_IN to 66MHz_OUT delay is shown in the figure below and is specified to be within a min and max
propagation value.
66MHz_IN
Tpd
66MHz_OUT
Tpci
PCICLK_F
3V66
No Relationship
Group Skews at Common Transition Edges: (Buffered Mode)
GROUP
3V66
66MHz_OUT
PCI
66MHz_IN
66MHz_OUT
66MHz_OUT to PCI
SYMBOL
CONDITIONS
3V66
3V66 (1:0) pin to pin skew
66OUT
66MHz_OUT (2:0) pin to pin skew
PCI
Tpd
Tpci
PCI_F (2:0) and PCI (6:0) pin to pin skew
Propogation delay from 66MHz_IN to
66MHz_OUT (2:0)
66MHz_OUT (2:0) leads 33 MHz PCI
1
Guaranteed by design, not 100% tested in production.
0404B—12/23/02
12
MIN
0
0
TYP
MAX UNITS
500
ps
175
ps
0
500
ps
2.5
4.5
nS
1.5
3.5
nS
ICS9250-38
Un-Buffered Mode 3V66 & PCI Phase Relationship
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock,
there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66
by the standard skew described below as Tpci.
3V66 (1:0)
3V66 (4:2)
3V66_5
Tpci
PCICLK_F (2:0) PCICLK (6:0)
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP
3V66
PCI
3V66 to PCI
SYMBOL
CONDITIONS
3V66
3V66 (5:0) pin to pin skew
PCI
S3V66-PCI
PCI_F (2:0) and PCI (6:0) pin to pin skew
3V66 (5:0) leads 33MHz PCI
1
Guaranteed by design, not 100% tested in production.
0404B—12/23/02
13
MIN
0
TYP
MAX UNITS
500
ps
0
500
ps
1.5
3.5
ns
ICS9250-38
Normal operation transition to Suspend State S1 Entry sequence of events:
1. Power-Down (PD#) pin is taken from a high to low to start into S1 Suspend state with digital filtering of the
transition in the clock circuit.
2. The first clocks to be forced to a Stop Low power down condition are the PCI buffer output clocks after a full
clock cycle. If the PCI_Stop# is low, then the free-running PCI clocks (for PCI and APIC signals) are the
remaining PCI buffer clocks stopped.
3. Immediately after the PCI clocks have been stopped the 66Buf_0:2 clocks are stopped low after the next
high to low transition. It will always be a sequence of PCI stopping, THEN the 66Buf clocks.
4. Following the two buffer output clocks being stopped (PCI then 66.6Buffer outputs), the remaining clocks
within a short delay will transition to a stopped power-down state. The first of these driven clocks that
transition to a stopped state are all of the CPU PLL clocks: the CPU and the driven 3V66 clocks.
5. After the CPU PLL clocks are stopped, the 48 MHz clocks (USB, DOT clocks) will stop low, then the REF
clock 14.318 MHz clock will stop low.
6. After the clocks have all been stopped, the internal PLL stages and the Crystal oscillator will all be driven to
a low power stopped condition.
7. As a note to power management calculations, please be aware that the CPU design requires that in the
Power-Down (S1 mode) the CPU outputs have a differential bias voltage driving the differential input stage of
the CPU in this S1 state. For this PD condition of the clock generator, the IDD_PD is running around 30 to
45 mA from having the Iref running (5 mA), the output multiplier bias generator at a 2X condition and the
output current source outputs are running at a 2xIref bias level (for approx 10 mA each CPU output). This
results in a higher level of Clock generator IDD_PD than in prior generations of clocks due to the CPU output
differential requirements.
Suspend State S1 Exit transition to normal operation sequence of events:
1. Power-Down (PD#) pin is taken from Low to High with digital filtering of the transition in the clock circuit to
return to normal running operation.
2. The Crystal Oscillator and the two PLL stages are released from PD to start-up to normal operation. No
clocks will operate until the Lock detect circuitry verifies the PLL has reached stable final frequency (the
same as normal initial power-up).
3. The CPU PLL clocks (differential CPU outputs and the driven 3V66_(0:1) clocks are operating first as soon
as the Lock detect releases the clocks. With the release of these clocks, the single 66Buf_1 buffer driven
output (at pin 22) is also released from the PD stopped state (but NOT the other 66Buf0,2 and not the PCI
outputs). This allows the GMCH chipset 66.6 MHz DLL stage to start operating and have an operating
feedback path before the other buffer outputs are released. This change is why the requirement is made that
pin 22 be the connection from the clock to the GMCH chipset. Note that along with the 66Buf_0,2 and the
PCI clocks, the 48 MHz and REF (14.318 MHz) clocks are also NOT released at this point.
4. A delay is built into the clock generator that allows the CPU, driven 3V66_0,1 and the single buffer clock
66Buf_1 (at pin 22) to operate before other clocks are released. This delay is larger than 30 uS and shorter
than 400 uS, and after this the other clocks are staged for a sequential release.
5. The initial clocks released after the delay are the 66Buf_0, 2 outputs.
6. After the 66Buf_0,2 clocks are released, then the PCI clocks are released.
7. It will always be the sequence of 66_1 (pin 22) released with the CPU clocks, then after the delay the
remaining 66Buf_0,2 first, THEN the PCI clocks.
8. Following the 66Buf_0,2 clocks, the 48 MHz (DOT and USB clocks) and the REF (14.318MHz) clocks are
released.
9. Note, the initial power-up time is the same as this PD release, the PLL will power-up and the outputs will be
running within a 3 ms time point.
0404B—12/23/02
14
ICS9250-38
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will
latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized
by the next rising edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable
via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling
as shown. The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the
output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC
signal will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUT
CPUC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
Normal
Normal
0
iref * Mult
Float
0404B—12/23/02
15
ICS9250-38
PD# - Assertion (transition from logic "1" to logic "0")
When PD# is sampled low by two consecutive rising edges of CPU clock then all clock outputs except CPU clocks
must be held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with
a value of 2x Iref, and CPUC undriven. Note the example below shows CPU = 100MHz, this diagram and description
is applicable for all valid CPU frequencies 66, 100, 133, 200MHz.
Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more
than one clock cycle to complete.
Power Down Assertion of Waveforms - Buffered Mode
25ns
0ns
50ns
PD#
CPUT 100MHz
CPUC 100MHz
3V66MHz
66MHz_IN
66MHz_OUT
PCI 33MHz
USB 48MHz
REF 14.318MHz
PD# Functionality
CPU_STOP#
CPUT
CPUC
3V66
66MHz_OUT
PCICLK_F
PCICLK
PCICLK
USB/DOT
48MHz
1
Normal
Normal
66MHz
66MHz_IN
66MHz_IN
66MHz_IN
48MHz
0
iref * Mult
Float
Low
Low
Low
Low
Low
0404B—12/23/02
16
ICS9250-38
c
N
SYMBOL
L
E1
INDEX
AREA
E
1 2
α
h x 45°
D
A
A
A1
b
c
D
E
E1
e
h
L
N
α
A1
-Ce
SEATING
PLANE
b
.10 (.004) C
N
56
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
VARIATIONS
D mm.
MIN
MAX
18.31
18.55
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
D (inch)
MIN
.720
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS9250yF-38-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0404B—12/23/02
17
MAX
.730
ICS9250-38
c
N
L
E1
INDEX
AREA
E
1 2
D
A
A2
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
D
SEE VARIATIONS
SEE VARIATIONS
E
8.10 BASIC
0.319 BASIC
E1
6.00
6.20
.236
.244
e
0.50 BASIC
0.020 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
α
0°
8°
0°
8°
aaa
-0.10
-.004
A1
-Ce
b
VARIATIONS
N
SEATING
PLANE
aaa C
56
D mm.
MIN
13.90
D (inch)
MAX
14.10
MIN
.547
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
(240 mil)
Ordering Information
ICS9250yG-38-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0404B—12/23/02
18
MAX
.555