Integrated Circuit Systems, Inc. ICS9179-06 Zero Delay Buffers General Description Features The ICS9179-06 generates low skew clock buffers required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. An output enable is provided for testability. The device is a buffer with low output to output skew. This is a zero delay buffer device, using an internal PLL. This buffer can be used for phase synchronization to a master clock. With the wide PLL loop BW, this buffer is compatible to Spread Spectrum input clocks from clock generator products such as the ICS9148-27. The individual clock outputs are addressable through I2C to be enabled, or stopped in a low state for reduced EMI when the lines are not needed. The device defaults to zero-delay mode, but can be programmed with I2C for selectable delays -2.7, +2.0, -0.7 ns (nominal target values). Zero delay buffer, 16 outputs Supports up to four SDRAM DIMMS Wide PLL loop bandwidth makes this part ideal in Spread Spectrum applications. Skew Input to FB_IN ±250ps default, with selectable skew -2.7, +2.0, -0.7ns nominal. Synchronous clocks skew matched to 250 ps window on output. 33 to 133MHz input or output frequency. I2C Serial Configuration interface to allow individual clocks to be stopped, or selectable delays. Multiple VDD, VSS pins for noise reduction Slew rate 1.5V/ns into 30pF. VDD = 3.3 ±5%, 0 to 70°C All outputs (0:15) tristate with OE low (FB_OUT stays running). 48-Pin SSOP package Block Diagram Pin Configuration Functionality OE# OUTPUT (0:15) FB_OUT 0 Hi-Z 1 X INPUT 1 1 X INPUT 1 X INPUT 48-Pin SSOP PentiumPro is a trademark of Intel Corporation I2C is a trademark of Philips Corporation 9179-06 Rev F 6/22/99 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9179-06 Pin Descriptions PIN NUMBER P I N NA M E TYPE 2 OE IN 5, 6, 9, 10 OUTPUT (0:3) OUT DESCRIPTION Tri-states all outputs except FB_OUT when held LOW. Has internal pull-up.2 SDRAM Byte 0 clock outputs1 15, 16, 19, 20 OUTPUT (4:7) OUT SDRAM Byte 1 clock outputs1 29, 30, 33, 34 40, 41, 44, 45 12 13 24 25 37 3, 7, 11, 17, 21, 31, 35, 38, 42, 46 4, 8, 14, 18, 28, 32, 36, 39, 43, 47 OUTPUT (8:11) OUTPUT (12:15) INPUT FB_IN SDATA SCLK FB_OUT OUT OUT IN IN I/O I/O OUT SDRAM Byte 2 clock outputs1 SDRAM Byte 3 clock outputs1 Input for reference clock. Feedback input. D a t a p i n f o r I 2C c i r c u i t r y 3 C l o c k p i n f o r I 2C c i r c u i t r y 3 Feedback output to input FB_IN. VDD PWR 3.3V Power supply for output buffers GND PWR Ground for output buffers 22 VDDA PWR 3.3V Power supply for Analog PLL stages 23 VDDS PWR 3.3V Power supply for I2C circuitry 26 27 GNDS GNDA PWR PWR G r o u n d f o r I 2C c i r c u i t r y Ground for Analog PLL stages 1, 48 N/C - Pins are not internally connected Notes: 1. At power up all sixteen outputs are enabled and active. 2. OE has a 100K Ohm internal pull-up resistor to keep all outputs active. 3. The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for complete platform flexibility. 4. I2C Byte0, bits 0 & 1 used to select delay. Default* values at power up is 0 5. Subject to design engineering verification of target value. Delay Selection Table4 Power Groups VDD = Power supply for OUTPUT buffers VDDS = Power supply for I 2C circuitry VDDA = Power supply for Analog PLL circuitry Ground Groups GND = Ground supply for OUTPUT buffer GNDS = Ground supply for I2C circuitry GNDA = Ground supply for Analog PLL circuitry 2 Nominal Target5 Delay, INPUT to FB_IN pins. INPUT Control Byte0 bit1 FB_IN Control Byte0 bit0 0* 0* 0ns 0 1 -2.7ns 1 0 +2.0ns 1 1 -0.7ns ICS9179-06 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK Byte Count ACK Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. ICS (Slave/Receiver) The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 3 ICS9179-06 ICS9179-06 Power Management The values below are estimates of target specifications. Max 3.3V supply consumption Max discrete cap loads VDD = 3.465V All static inputs = VDD or GND Condition No Clock Mode (BUF_IN - VDD1 or GND) I2C Circuitry Active Active 66MHz (BUF_IN = 66.66MHz) Active 100MHz (BUF_IN = 100.00MHz) 30mA 150mA 180mA Byte 2: OUTPUT Clock Register (Default = 1) BIT PIN# PWD Bit 7 45 1 Bit 6 44 1 Bit 5 41 1 Bit 4 40 1 Bit 3 34 1 Bit 2 33 1 Bit 1 30 1 Bit 0 29 1 DESCRIPTION OUTPUT 15 (Act/Inact) OUTPUT 14 (Act/Inact) OUTPUT 13 (Act/Inact) OUTPUT 12 (Act/Inact) OUTPUT 11 (Act/Inact) OUTPUT 10 (Act/Inact) OUTPUT 9 (Active/Inactive) OUTPUT 8 (Active/Inactive) Byte 3: OUTPUT Clock Register BIT PIN# PWD Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 1 Notes: 1 = Enabled; 0 = Disabled, outputs held low DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d Notes: 1 = Enabled; 0 = Disabled, outputs held low Note: PWD = Power-Up Default Serial Configuration Command Bitmaps Byte 0: OUTPUT Clock Register (default = 0) BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 12 Bit 02 PIN# 12 13 PWD 0 0 0 0 0 0 0 0 Byte 1: OUTPUT Clock Register BIT Bit7 Bit6 Bit5 Bit4 DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d Clock INPUT Skew Control FBIN Skew Control Bit3 Bit2 Bit1 Bit0 Notes: 2 = Default = 0; 1 = Delay element enabled, 0 = No delay path. PIN# PWD 20 1 19 1 16 1 15 1 10 1 9 1 6 1 5 1 DESCRIPTION OUTPUT 7 (Act/Inact) OUTPUT 6 (Act/Inact) OUTPUT 5 (Act/Inact) OUTPUT 4 (Act/Inact) OUTPUT 3 (Act/Inact) OUTPUT 2 (Act/Inact) OUTPUT 1 (Act/Inact) OUTPUT 0 (Act/Inact) Notes: 1 = Enabled; 0 = Disabled, outputs held low Note: PWD = Power-Up Default 4 ICS9179-06 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V DD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input & Supply TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Output Disabled Supply Current Input frequency Input Capacitance 1 SYMBOL VIH VIL IIH IIL1 IIL2 IDD IDD Fi CIN CONDITIONS MIN 2 VSS-0.3 VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; FIN @ 66M CL = 0 pF; FIN @ 100M CL = 0 pF; FIN @ 66M CL = 0 pF; FIN @ 100M VDD = 3.3 V; All Outputs Loaded Logic Inputs -5 -60 TYP -33 115 170 33 MAX UNITS VDD+0.3 V 0.8 V 5 uA uA uA 150 mA 180 mA 30 mA 30 mA 105 MHz 5 pF Guarenteed by design, not 100% tested in production. Electrical Characteristics - Input & Supply TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Operating Supply Current Input frequency Input Capacitance 1 SYMBOL VIH VIL IIH IIL IIL IDD1 IDD2 Fi 1 CIN1 CONDITIONS VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with 100K pull-up resistors CL = 0 pF; FIN @ 66M CL = 0 pF; FIN @ 100M VDD = 3.3 V; All Outputs Loaded Logic Inputs Guarenteed by design, not 100% tested in production. 5 MIN 2 VSS-0.3 -5 -60 10 TYP -33 115 170 MAX UNITS VDD+0.3 V 0.8 V 5 uA uA uA 150 mA 180 mA 150 MHz 5 pF ICS9179-06 Electrical Characteristics - SDRAM TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output Frequency FO3 VO = VDD*(0.5) Output Impedance RDSP3 VO = VDD*(0.5) Output Impedance RDSN3 IOH = -30 mA Output High Voltage VOH3 IOL = 23 mA Output Low Voltage VOL3 VOH = 2.0 V Output High Current IOH3 VOL = 0.8 V Output Low Current IOL3 VOL = 0.4 V, VOH = 2.4 V Rise Time Tr3 VOH = 2.4 V, VOL = 0.4 V Fall Time Tf3 VT = 1.5 V Duty Cycle Dt3 Output to Output VT = 1.5 V Tsk3 Skew Window VT = 1.5 V default Zero delay I2 C Tskd1 B0 bits 0, 1 = 00 1, 2 T VT = 1.5 V bits 0, 1 = 10 IN to FB_IN Skew skd2 VT = 1.5 V bits 0, 1 = 01 Tskd3 VT = 1.5 V bits 0, 1 = 11 Tskd4 MIN 33 10 10 2.6 TYP 40 45 MAX UNITS 133 MHz 24 Ohm 24 Ohm V 0.4 V -54 mA mA 1.33 nS 1.33 nS 55 % 250 pS -250 0 250 pS -2.2 +1.5 -0.2 -2.7 +2.0 -0.7 -3.2 +2.5 -1.2 nS nS nS Notes: 1. Guarenteed by design, not 100% tested in production 2. Delay elements FBIN and clock INPUT path are selected by I2C BYTE2; bit 0 = clock input control, bit 1 = Clock INPUT Control. (Default is 0). A 0 = No delay in path, 1 = Delay element selected. Note: PWD = Power-Up Default Input Pulse MIN TYP MAX UNITS Input Pulse Low Time Tim-Low Vpulse_Low ≤ 0.8V 1.0 ns Input Pulse High Time Tim-High Vpulse_High ≥ 2.0V 1.5 ns 6 ICS9179-06 General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance. Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. Capacitor Values: All unmarked capacitors are 0.01µF ceramic 7 ICS9179-06 SSOP Package SYMBOL A A1 A2 B C D E e H h L N ∝ X COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0° 5° 8° .085 .093 .100 VARIATIONS AC MIN. .620 D NOM. .625 N MAX. .630 48 Ordering Information ICS9179F-06 Example: ICS XXXX F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 8 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.