ICS93725 Integrated Circuit Systems, Inc. DDR and SDRAM Zero Delay Buffer Recommended Application: DDR & SDRAM Zero Delay Buffer for SIS 635/640/645/ 650 & 735/740/746 style chipsets. Pin Configuration Product Description/Features: • Low skew, Zero Delay Buffer • 1 to 13 SDRAM PC133 clock distribution • 1 to 6 pairs of DDR clock distribution • I2C for functional and output control • Separate feedback path for both memory mode to adjust synchronization. • Supports up to 2 DDR DIMMs or 3 SDRAM DIMMs • Frequency support for up to 200MHz • Individual I2C clock stop for power mananagement • CMOS level control signal input Switching Characteristics: • OUTPUT - OUTPUT skew: <100ps • Output Rise and Fall Time for DDR outputs: 550ps 1150ps • DUTY CYCLE: 47% - 53% Functionality PLL1 DDRFB_OUT Control SDATA SCLK 3 3 Config. Reg. 0606A—08/01/03 MODE PIN 48 VDD 3.3_2.5 DDR Mode SEL_DDR=1 2.5V DDR/SD Mode SEL_DDR=0 3.3V SDRAMFB_OUT Logic SEL_DDR* DDRFB_IN DDRFB_OUT VDD2.5 DDRT5 DDRC5 DDRT4 DDRC4 GND VDD2.5 DDRT3 DDRC3 DDRT2 DDRC2 GND VDD2.5 DDRT1 DDRC1 DDRT0 DDRC0 GND VDD2.5 SCLK SDATA *Internal Pull-up Resistor of 120K to VDD SDRAM (12:0) SEL_DDR* 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48-Pin SSOP Block Diagram BUFFER_IN SDRAMFB_IN DDRFB_IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS93725 VDD3.3 SDRAM0 SDRAM1 SDRAM2 SDRAM3 GND VDD3.3 SDRAM4 SDRAM5 BUFFER_IN SDRAM6 SDRAM7 GND VDD3.3 SDRAM8 SDRAM9 SDRAM10 SDRAM11 GND VDD3.3 SDRAM12 SDFB_OUT SDFB_IN GND DDRT (5:0) DDRCC (5:0) ICS93725 Pin Descriptions PIN NUMBER 1, 7, 14, 20 PIN NAME TYPE DESCRIPTION VDD3.3 PWR 3.3V voltage supply for SDRAM. GND PWR Ground 44, 42, 38, 36, 32, 30 DDRT (5:0) OUT "Tr ue" Clock of differential pair outputs. 43, 41, 37, 35, 31, 29 DDRC (5:0) OUT "Complementor y" clocks of differential pair outputs. OUT SDRAM clock outputs PWR 2.5V voltage supply for DDR. 6, 13, 19, 24, 34, 28, 40 21, 18, 17, 16, 15, 12, 11, 9, 8, 5, SDRAM (12:0) 4, 3, 2 27, 39, 45 VDD2.5 10 BUFFER_IN IN 22 SDRAMFB_OUT 23 SDFB_IN IN Feedback input for SDRAM 25 SDATA I/O Data pin for I2C circuitr y 5V tolerant 26 SCLK IN Clock input of I2C input, 5V tolerant input 46 DDRFB_OUT 47 DDRFB_IN IN Feedback input for DDR 48 SEL_DDR IN Select input for DDR mode or DDR/SD mode 0=SD mode 1=DDR mode OUT OUT Single ended buffer input Feedback output for SDRAM Feedback output for DDR 0606A—08/01/03 2 ICS93725 Byte 6: Output Control (1= enable, 0 = disable) BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 48 44, 43 42, 41 38, 37 36, 35 32, 31 PWD 1 1 1 1 1 1 1 Byte 7: Output Control (1= enable, 0 = disable) DESCRIPTION SEL_DDR (Read back only) (Reserved) (Reserved) DDRT5, DDRC5 DDRT4, DDRC4 DDRT3, DDRC3 DDRT2, DDRC2 DDRT1, DDRC1 0606A—08/01/03 3 BIT Bit 7 Bit 6 PIN# 30, 29 21 Bit 5 17, 18 Bit 4 15, 16 Bit 3 11, 12 Bit 2 8, 9 Bit 1 4, 5 Bit 0 2, 3 PWD DESCRIPTION 1 DDRT0, DDRC0 1 SDRAM12 SDRAM10 1 SDRAM11 SDRAM8 1 SDRAM9 SDRAM6 1 SDRAM7 SDRAM4 1 SDRAM5 SDRAM2 1 SDRAM3 SDRAM1 1 SDRAM0 ICS93725 Absolute Maximum Ratings Supply Voltage (VDD & VDD2.5) . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 3.6V GND –0.5 V to VDD +0.5 V 0°C to +85°C 115°C –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters SEL_DDR=0 SDRAM Outputs VDD=3.3V, TA=0 - 85°C; (unless otherwise stated) PARAMETER Operating Supply Current SYMBOL IDD3.3 Output High Current Output Low Current IOH IOL High-level output voltage VOH Low-level output voltage VOL CONDITIONS MIN TYP 100MHz, RL=0Ω, CL = 0pF 130 133MHz, RL=0Ω, CL = 0pF 173 200MHz, RL=0Ω, CL = 0pF VDD=3.3V, VOUT=1V VDD=3.3V, VOUT=1.2V VDD=3.3V IOH = -12 mA VDD=3.3V IOH = 12 mA VI = GND or VDD 247 26 -40 34 1.7 2 1 CIN Input Capacitance Guaranteed by design, not 100% tested in production. 0.4 MAX UNITS mA mA -18 mA mA V 0.6 2 V pF 1 Recommended Operating Condition SEL_DDR=0 SDRAM Outputs VDD=3.3V, TA=0 - 85°C; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN V 3 Power Supply Voltage DD3.3 VIH SEL_DDR, PD# input 2 Input High Voltage VIL SEL_DDR, PD# input Input Low Voltae VIN Input Voltage Level 0 1 Guaranteed by design, not 100% tested in production. 0606A—08/01/03 4 TYP 3.3 MAX 3.6 3.3 0.8 3.6 UNITS V V V V ICS93725 Electrical Characteristics - Input/Supply/Common Output Parameters SEL_DDR=1 DDR Outputs VDD=2.5V, TA=0 - 85°C; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS 100MHz, RL=0Ω, CL = 0pF IDD2.5 Operating Supply Current 133MHz, RL=0Ω, CL = 0pF 200MHz, RL=0Ω, CL = 0pF VDD=2.5V, VOUT=1V IOH Output High Current VDD=2.5V, VOUT=1.2V IOL Output Low Current VDD=2.5V VOH High-level output voltage IOH = -12 mA VDD=2.5V VOL Low-level output voltage IOH = 12 mA VDD = 2.5V Output differential-pair VOC 100/133/166/ 200 Mhz Crossing voltage 1 CIN VI = GND or VDD Input Capacitance 1 MIN 26 TYP 141 188 271 -43 38 1.7 2 1.05 MAX -18 UNITS mA mA mA mA mA V 0.4 0.6 V 1.25 1.45 V 2 pF Guaranteed by design, not 100% tested in production. Recommended Operating Condition SEL_DDR=1 DDR Outputs VDD=2.5V, TA=0 - 85°C; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS VDD2.5 Power Supply Voltage VIH SEL_DDR, PD# input Input High Voltage VIL SEL_DDR, PD# input Input Low Voltage VIN Input Voltage Level 1 Guaranteed by design, not 100% tested in production. 0606A—08/01/03 5 MIN 2.3 2 0 TYP 2.5 MAX 2.7 2.5 0.8 2.7 UNITS V V V V ICS93725 Switching Characteristics PARAMETER Operating Frequency Input Clock Duty Cycle DDR Static Phase Error SDRAM Static Phase Error SYMBOL DDR output to output Skew Tskewd SDRAM output to output Skew Tskews din tped tpes DDR Duty Cycle DC 2 SDRAM Duty Cycle DC 2 DDR Rise Time trd DDR Fall Time tfd SDRAM Rise Time SDRAM Fall Time trs tfs DDR Cycle to Cycle Jitter t(C-C)D SDRAM Cycle to Cycle Jitter t(C-C)S 1 2 CONDITIONS Not including FBOUT to outputs Not including FBOUT to outputs 66MHz to 100MHz 101MHz to 200MHz 66MHz to 100MHz 101MHz to 200MHz Measured between 20% and 80% output, CL=16pF VOL = 0.4V, VOH = 2.4V, CL=30pF SEL_DDR=1,VDD=2.5V , CL=16pF SEL_DDR=0,VDD=3.3V , CL=30pF MIN 66 40 -100 -100 TYP -50 -20 MAX 200 60 100 100 UNITS MHz % ps ps 60 100 ps 200 300 ps 48 48 48 48 0.55 0.68 52 53 52 56 0.95 % % % % ns 0.63 0.91 1.15 ns 0.5 0.5 1.4 1.65 1.7 1.8 ns ns 23 38 ps 36 57 ps Guaranteed by design, not 100% tested in production. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=t2/t1, where the cycle (t1) decreases as the frequency goes up. Switching Waveforms Duty Cycle Timing t2 1.5V 1.5V t1 1.5V SDRAM Buffer LH and HL Propagation Delay INPUT OUTPUT t6 t7 0606A—08/01/03 6 ICS93725 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: • • • • • • • • • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 • ICS clock will acknowledge each byte one at a time. • Controller (host) sends a Stop bit How to Write: Controller (Host) Start Bit Address D4(H) Controller (host) will send start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 7 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Read: ICS (Slave/Receiver) Controller (Host) Start Bit Address D5(H) ACK ICS (Slave/Receiver) ACK Byte Count Dummy Command Code ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Dummy Byte Count Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Byte 6 Byte 6 Byte 7 Byte 7 ACK Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 0606A—08/01/03 7 ICS93725 c N SYMBOL A A1 b c D E E1 e h L N α L E1 INDEX AREA E 1 2 α h x 45° D A N 48 A1 -C- In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° VARIATIONS D mm. MIN MAX 15.75 16.00 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° D (inch) MIN .620 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 e SEATING PLANE b .10 (.004) C 300 mil SSOP Package Ordering Information ICS93725yFT Example: ICS XXXX y F - T Designation for tape and reel packaging Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0606A—08/01/03 8 MAX .630