ICS ICS9248-138

ICS9248-138
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Celeron & PII/III™
1
*SEL24_48#/REF0
VDDREF
X1
X2
GNDREF
GND3V66
3V66-0
3V66-1
3V66-2
VDD3V66
VDDPCI
1
*FS0/PCICLK0
1
**FS1/PCICLK1
GNDPCI
PCICLK2
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
GNDPCI
PD#
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS9248-138
Pin Configuration
Recommended Application:
810/810E and Solano type chipset.
Output Features:
•
2- CPUs @ 2.5V
•
9 - SDRAM @ 3.3V, including 1 free running
•
7 - PCICLK @ 3.3V
•
1 - IOAPIC @ 2.5V,
•
3 - 3V66MHz @ 3.3V
•
2 - 48MHz, @ 3.3V fixed.
•
1 - 24/48MHz, @3.3V selectable by I2C
•
1 - REF @v3.3V, 14.318MHz.
Features:
•
Up to 200MHz frequency support
•
Support FS0-FS4 strapping status bit for I2C read back.
•
Support power management: Through Power down
Mode from I2C programming.
•
Spread spectrum for EMI control ( ± 0.25% center).
•
Uses external 14.318MHz crystal
Skew Specifications:
•
CPU – CPU: <175ps
•
SDRAM - SDRAM: < 250ps
•
3V66 – 3V66: <175ps
•
PCI – PCI: <500ps
•
For group skew specifications, please refer to group
timing relationship.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDLAPIC
1
IOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
24_48MHz/FS2**
48MHz/FS3*
1
48MHz/FS4*
VDD48
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDD.
* * These inputs have a 120K pull down to GND.
1 These are double strength.
Functionality
Block Diagram
PLL2
2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz [1:0]
24_48MHz
/2
X1
X2
REF0
CPU
DIVDER
2
SDRAM
DIVDER
8
CPUCLK [1:0]
SDRAM [7:0]
SDRAM_F
SEL24_48#
Control
SDATA
SCLK
PD#
IOAPIC
DIVDER
IOAPIC
Logic
PCI
DIVDER
FS[4:0]
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3V66
DIVDER
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
160.00
160.00
166.67
166.67
FS0
SDRAM
(MHz)
100.00
100.30
103.00
107.00
100.00
100.30
103.00
107.00
133.33
133.73
137.33
120.00
100.00
100.30
103.00
90.00
3V66
(MHz)
66.67
66.87
68.67
71.34
66.67
66.87
68.67
71.34
66.67
66.87
68.67
60.00
66.67
66.87
68.67
60.00
PCICLK
(MHz)
33.33
33.43
34.33
35.66
33.33
33.43
34.33
35.66
33.33
33.43
34.33
30.00
33.33
33.43
34.33
30.00
I OA P I C
(MHz)
16.67
16.72
17.16
17.83
16.67
16.72
17.17
17.84
16.67
16.72
17.17
15.00
16.67
16.72
17.17
15.00
160.00
120.00
166.67
125.00
80.00
80.00
83.34
83.34
40.00
40.00
41.67
41.67
20.00
20.00
20.84
20.84
PCICLK [6:0]
Config.
Reg.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CPU
(MHz)
66.67
66.87
68.67
71.34
100.00
100.30
103.00
107.00
133.33
133.73
137.33
120.00
133.33
133.73
137.33
120.00
FS4 FS3 FS2 FS1
3V66 [2:0]
3
Additional frequencies selectable through I2C programming.
9248- 138 Rev A 10/03/00
Third party brands and names are the property of their respective owners.
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
ICS9248-138
Preliminary Product Preview
General Description
The ICS9248-138 is the single chip clock solution for designs using the 810/810E and Solano style chipset. It provides all
necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-138 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
SEL24_48M Hz#
IN
REF0
OUT
VDD
PWR
X1
X2
IN
OUT
DESCRIPTION
Logic inputs frequency select I/O/USB output,
When a "0" is latched, output frequency = 48M Hz
When a "1" is latched, output frequency = 24M Hz
14.318 M Hz reference clock.
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48M Hz output
Crystal input,nominally 14.318M Hz.
Crystal output, nominally 14.318M Hz.
GND
PWR
Ground pin for 3V outputs.
20, 19, 17, 16, 15
3V66 [2:0]
FS0
PCICLK0
FS1
PCICLK1
PCICLK [6:2]
OUT
IN
OUT
IN
OUT
OUT
3.3V Clocks
Frequency select pin.
PCI clock output
Frequency select pin.
PCI clock output
PCI clock outputs.
22
PD#
IN
23
24
SCLK
SDATA
FS4
48M Hz
FS3
48M Hz
IN
IN
IN
OUT
IN
OUT
IN
1
2, 10, 11, 18, 25,
30, 38
3
4
5, 6, 14, 21, 29, 34,
42
9, 8, 7
12
13
26
27
28
31
32, 33, 35, 36, 37,
39, 40, 41,
43
44, 45
46
47
FS2
24_48M Hz
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
Clock input of I2C input, 5V tolerant input
Data input for I2C serial input, 5V tolerant input
Frequency select pin.
48MHz output clocks
Frequency select pin.
48MHz output clocks
Frequency select pin.
OUT
24 or 48M Hz output
SDRAM _F
OUT
Free running SDRAM - used for feed back to chipset, should remain on
always.
SDRAM [7:0]
OUT
SDRAM clock outputs
GNDLCPU
CPUCLK [1:0]
VDDLCPU
IOAPIC
PWR
OUT
PWR
OUT
Ground pin for the CPU clocks.
CPU clock outputs.
Power pin for the CPUCLKs. 2.5V
2.5V clock output
Third party brands and names are the property of their respective owners.
2
ICS9248-138
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit
2, 7:4
Bit 3
Bit 1
Bit 0
Description
bit2 bit7 bit6 bit5 bit4 CPUCLK SDRAM
3V66
(MHz)
(MHz)
(MHz)
FS4 FS3 FS2 FS1 FS0
0
0
0
0
0
66.67
100.00
66.67
0
0
0
0
1
66.87
100.30
66.87
0
0
0
1
0
68.67
103.00
68.67
0
0
0
1
1
71.34
107.00
71.34
0
0
1
0
0
100.00
100.00
66.67
0
0
1
0
1
100.30
100.30
66.87
0
0
1
1
0
103.00
103.00
68.67
0
0
1
1
1
107.00
107.00
71.34
0
1
0
0
0
133.33
133.33
66.67
0
1
0
0
1
133.73
133.73
66.87
0
1
0
1
0
137.33
137.33
68.67
0
1
0
1
1
120.00
120.00
60.00
0
1
1
0
0
133.33
100.00
66.67
0
1
1
0
1
133.73
100.30
66.87
0
1
1
1
0
137.33
103.00
68.67
0
1
1
1
1
120.00
90.00
60.00
1
0
0
0
0
136.00
136.00
68.00
1
0
0
0
1
140.00
140.00
70.00
1
0
0
1
0
142.67
142.67
71.34
1
0
0
1
1
145.33
145.33
72.67
1
0
1
0
0
136.00
102.00
68.00
1
0
1
0
1
140.00
105.00
70.00
1
0
1
1
0
142.67
107.00
71.34
1
0
1
1
1
145.33
109.00
72.67
1
1
0
0
0
146.67
146.67
73.34
1
1
0
0
1
153.33
153.33
76.67
1
1
0
1
0
160.00
160.00
80.00
1
1
0
1
1
166.67
166.67
83.34
1
1
1
0
0
146.67
110.00
73.34
1
1
1
0
1
160.00
120.00
80.00
1
1
1
1
0
166.67
125.00
83.34
1
1
1
1
1
200.00
200.00
66.67
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 6:4
0 - Normal
1 - Spread Spectrum Enabled ± 0.25% Center Spread
0 - Running
1- Tristate all outputs
PWD
PCICLK IOAPIC
(MHz)
(MH)
33.33
33.43
34.33
35.67
33.33
33.43
34.33
35.67
33.33
33.43
34.33
30.00
33.33
33.43
34.33
30.00
34.00
35.00
35.67
36.33
34.00
35.00
35.67
36.33
36.67
38.33
40.00
41.67
36.67
40.00
41.67
33.33
16.67
16.72
17.16
17.83
16.67
16.72
17.17
17.84
16.67
16.72
17.17
15.00
16.67
16.72
17.17
15.00
17.00
17.50
17.84
18.17
17.00
17.50
17.84
18.17
18.34
19.17
20.00
20.84
18.34
20.00
20.84
16.67
Spread Precentage
0 to -0.5% Down Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
0 to -0.5% Down Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
0 to -0.5% Down Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
0 to -0.5% Down Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
Note 1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
I2C is a trademark of Philips Corporation
Third party brands and names are the property of their respective owners.
3
0,0000
0
1
0
ICS9248-138
Preliminary Product Preview
Byte 1: SDRAM Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
31
32
33
35
36
37
PWD
X
X
1
1
1
1
1
1
Byte 2: PCI, Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DESCRIPTION
FS2#
FS1#
SDRAM_F
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
Byte 3: 3V66, Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
7
8
9
PWD
X
1
1
X
1
1
1
1
PIN#
1
47
44
45
39
40
41
PWD
X
1
1
1
1
1
1
1
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
FS0#
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Byte 4: Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DESCRIPTION
FS4#
R e s e r ve d
R e s e r ve d
FS3#
R e s e r ve d
3V66-0
3V66-1
3V66-2
Byte 5: Control Register
(1= enable, 0 = disable)
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PIN#
20
19
17
16
15
13
12
PIN#
26
27
28
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
48MHz-0
48MHz-1
24_48MHz
Byte 6: Control Register
(1= enable, 0 = disable)
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DESCRIPTION
SEL24_48#
REF0
IOAPIC
CPUCLK1
CPUCLK0
SDRAM2
SDRAM1
SDRAM0
Notes:
PWD
0
0
0
0
0
1
1
0
DESCRIPTION
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
Note: Don’t write into this register, writing into this
register can cause malfunction
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
PIN#
-
4
ICS9248-138
Preliminary Product Preview
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Group Timing Relationship Table
Group
CPU 66MHz
SDRAM 100MHz
CPU 100MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 133MHz
Offset
Tolerance
Offset
Tolerance
Offset
Tolerance
Offset
Tolerance
CPU to SDRAM
2.5ns
500ps
5.0ns
500ps
0.0ns
500ps
3.75ns
500ps
CPU to 3V66
7.5ns
500ps
5.0ns
500ps
0.0ns
500ps
0.0ns
500ps
SDRAM to 3V66
0.0ns
500ps
0.0ns
500ps
0.0ns
500ps
3.75ns
500ps
3V66 to PCI
1.5-3.5ns
500ps
1.5-3.5ns
500ps
1.5-3.5ns
500ps
1.5 -3.5ns
500ps
PCI to PCI
USB & DOT
0.0ns
Asynch
1.0ns
N/A
0.0ns
Asynch
1.0ns
N/A
0.0ns
Asynch
1.0ns
N/A
0.0ns
Asynch
1.0ns
N/A
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
Supply Current
Power Down
Supply Current
Input frequency
Pin Inductance
Input Capacitance1
Transition Time
IDD3.3PD
CONDITIONS
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66M
MIN
2
VSS-0.3
-5
-5
-200
TYP
CL = 0 pF; With input address to Vdd or GND
Fi
Lpin
VDD = 3.3 V;
CIN
Cout
CINX
Logic Inputs
Out put pin capacitance
X1 & X2 pins
Ttrans
MAX UNITS
VDD+0.3
V
0.8
V
µA
5
µA
µA
100
mA
600
µA
7
MHz
nH
5
6
45
pF
pF
pF
14.318
27
To 1st crossing of target Freq.
3
mS
Settling Time1
Ts
From 1st crossing to 1% target Freq.
3
mS
Clk Stabilization1
TSTAB
tPZH,tPZH
tPLZ,tPZH
From VDD = 3.3 V to 1% target Freq.
output enable delay (all outputs)
output disable delay (all outputs)
3
10
10
mS
nS
nS
Delay
1
1
SYMBOL
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
5
1
1
ICS9248-138
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Impedance
RDSP2B1
RDSN2B1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
MIN
TYP
MAX UNITS
VO = VDD*(0.5)
13.5
45
Ω
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @MIN= 1.0V , VOH@ MAX= 2.375V
VOL @MIN= 1.2V , VOL@ MAX= 0.3V
13.5
2
45
-27
27
0.4
-27
30
Ω
V
V
mA
mA
Rise Time
tr2B1
VOL = 0.4 V, VOH = 2.0 V
0.4
1.6
ns
Fall Time
VOH = 0.4 V, VOL = 2.0 V
0.4
1.6
ns
VT = 1.25 V
45
55
%
Skew
tf2B1
dt2B1
tsk2B1
250
ps
Jitter
tjcyc-cyc1
250
ps
Duty Cycle
1
VOH2B
VOL2B
IOH2B
IOL2B
CONDITIONS
VT = 1.25 V
VT = 1.25 V
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP1
1
VO = VDD*(0.5)
12
55
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN1
VOH1
VOL1
IOH1
IOL1
1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
12
2.4
55
-33
30
0.55
-33
38
Ω
V
V
mA
mA
Rise Time
tr11
VOL = 0.4 V, VOH = 2.4 V
0.5
2
ns
Fall Time
1
VOH = 2.4 V, VOL = 0.4 V
0.5
2
ns
1
VT = 1.5 V
45
55
%
1
VT = 1.5 V
VT = 1.5 V
175
500
ps
ps
Output Impedance
Duty Cycle
Skew
Jitter
1
tf1
dt1
tsk1
tjcyc-cyc
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9248-138
Preliminary Product Preview
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
1
Output Impedance
RDSP4B
VO = VDD*(0.5)
Output Impedance
RDSN4B1
VO = VDD*(0.5)
Output High Voltage
VOH4\B
IOH = -5.5 mA
Output Low Voltage
VOL4B
IOL = 9.0 mA
Output High Current
IOH4B
VOH@ min = 1.0 V, VOH@ MAX = 2.375 V
Output Low Current
IOL4B
VOL@ MIN = 1.2 V, VOL@ MAX= 0.3 V
1
Rise Time
tr4B
VOL = 0.4 V, VOH = 2.0 V
Fall Time
tf4B1
VOH = 2.0 V, VOL = 0.4 V
1
Duty Cycle
dt4B
VT = 1.25 V
1
Skew
tsk4
tjcyc-cyc
VT = 1.25 V
Jitter
MIN
9
9
2
TYP
-27
27
0.4
0.4
45
MAX UNITS
Ω
30
Ω
30
V
0.4
V
-27
mA
30
mA
1.6
ns
1.6
ns
55
%
250
ps
500
ps
1
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP3
1
VO = VDD*(0.5)
10
24
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN3
VOH3
VOL3
IOH3
IOL3
1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @MIN= 2.0 V, VOH@ MAX=3.135 V
VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V
10
2.4
24
-54
54
0.4
-46
53
Ω
V
V
mA
mA
Rise Time
Tr3 1
VOL = 0.4 V, VOH = 2.4 V
0.4
1.6
ns
Fall Time
Tf3
1
VOH = 2.4 V, VOL = 0.4 V
0.4
1.6
ns
Dt3
1
VT = 1.5 V
45
55
%
250
250
ps
ps
Output Impedance
Duty Cycle
Skew
Jitter
1
1
Tsk3
tj cyc-cyc
VT = 1.5 V
VT = 1.5 V
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
ICS9248-138
Preliminary Product Preview
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP1
1
VO = VDD*(0.5)
12
55
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN1
VOH1
VOL1
IOH1
IOL1
1
VO = VDD*(0.5)
12
IOH = -1 mA
2.4
IOL = 1 mA
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
30
55
0.55
-33
38
Ω
V
V
mA
mA
Rise Time
tr11
VOL = 0.4 V, VOH = 2.4 V
0.5
2
ns
Fall Time
1
VOH = 2.4 V, VOL = 0.4 V
0.5
2
ns
1
VT = 1.5 V
45
55
%
1
VT = 1.5 V
VT = 1.5 V
500
500
ps
ps
MAX
60
60
UNITS
Ω
Ω
V
V
mA
mA
ns
ns
%
ps
ps
ps
Output Impedance
Duty Cycle
Skew
Jitter
1
tf1
dt1
tsk1
tjcyc-cyc
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0
TA = 0 - 70C; V DD = V DDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
1
Output Impedance
RDSP5
V O = V DD *(0.5)
20
1
Output Impedance
RDSN5
V O = V DD *(0.5)
20
Output High Voltage
VOH5
IOH = 1 mA
2.4
IOL = -1 mA
Output Low Voltage
VOL5
V OH @MIN=1 V, VOH@MAX= 3.135 V
-29
Output High Current
IOH5
V OL@MIN=1.95 V, V OL@MIN =0.4 V
29
Output Low Current
IOL5
1
V OL = 0.4 V, VOH = 2.4 V
Rise Time
tr5
1
Fall Time
tf5
V OH = 2.4 V, V OL = 0.4 V
Duty Cycle
dt51
V T = 1.5 V
45
V T = 1.5 V
Skew
T sk
tjcyc-cyc1
V T = 1.5 V; Fixed Clocks
Jitter
1
tjcyc-cyc
V T = 1.5 V; Ref Clocks
1
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
TYP
0.4
-23
27
4
4
55
250
500
1000
ICS9248-138
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
Dummy Command Code
ACK
ICS (Slave/Receiver)
ACK
Byte Count
Dummy Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
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9
ICS9248-138
Preliminary Product Preview
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS9248138 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K Via to Gnd
Device
Pad
8.2K Clock trace to load
Series Term. Res.
Fig. 1
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10
ICS9248-138
Preliminary Product Preview
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. The REF and 48MHz clocks
are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding
the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLK
3V66
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
11
ICS9248-138
Preliminary Product Preview
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
2.413
2.794
.095
A1
0.203
0.406
.008
.016
b
0.203
0.343
.008
.0135
c
D
0.127
0.254
SEE VARIATIONS
.005
.010
SEE VARIATIONS
E
10.033
10.668
.395
.420
E1
7.391
7.595
.291
.299
e
0.635 BASIC
h
0.381
L
0.508
1.016
SEE VARIATIONS
N
α
0.025 BASIC
0.635
0°
.110
.015
.025
.020
.040
SEE VARIATIONS
8°
0°
8°
MIN
MAX
MIN
MAX
48
15.748
16.002
.620
.630
56
18.288
18.542
.720
.730
JEDEC MO-118
DOC# 10-0034
6/1/00
REV B
VARIATIONS
N
D mm.
D (inch)
Ordering Information
ICS9248yF-138
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
12
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.