ICS ICS9248-99

ICS9248-99
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Pin Configuration
Recommended Application:
810/810E style chipset
Output Features:
•
2- CPUs @2.5V @ 150MHz (up to 200MHz. achievable
through I2C)
•
9 - SDRAM @ 3.3V @ 150MHz (up to 200MHz.
achievable through I2C)
•
8 - PCICLK @ 3.3V
•
1 - IOAPIC @ 2.5V,
•
2 - 3V66MHz @ 3.3V
•
2- 48MHz, @ 3.3V fixed.
•
1- 24/48MHz, @ 3.3V
•
1- REF @3.3V, 14.318MHz.
Features:
•
Up to 200.4MHz frequency support
•
Support FS0-FS3 trapping status bit for I2C read back.
•
Support power management: Power down Mode form I2C
programming.
•
Spread spectrum for EMI control ( ± 0.25% center).
•
FS0, FS1, FS2, FS3 must have a internal 120K pull-Down
to GND.
•
Uses external 14.318MHz crystal
Skew Specifications:
•
CPU – CPU: <175ps
•
SDRAM - SDRAM: < 250ps
•
3V66 – 3V66: <175ps
•
PCI – PCI: <500ps
•
For group skew specifications, please refer to group
timing relationship table.
Block Diagram
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1 These are double strength.
Functionality
FS3 FS2 FS1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
9248- 99 Rev A 8/27/99
Third party brands and names are the property of their respective owners.
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
CPU
(MHz)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
75.33
125.00
129.00
150.29
150.00
112.00
145.00
143.64
68.30
105.00
138.00
140.00
66.67
100.00
133.60
133.33
SDRAM
(MHz)
3V66
(MHz)
113.00 75.33
125.00 83.33
129.00 86.00
113.00 75.33
150.00 100.00
112.00 74.67
145.00 96.67
108.00 72.00
102.50 68.33
105.00 70.00
138.00 92.00
105.00 70.00
100.00 66.67
100.00 66.67
133.60 89.07
100.00 66.67
PCICLK
(3V66*
1/2)
(MHz)
37.67
41.67
43.00
37.67
50.00
37.33
48.33
36.00
34.17
35.00
46.00
35.00
33.33
33.33
44.53
33.33
I OA P I C
(PCI*
1/2)
(MHz)
18.83
20.83
21.50
18.83
25.00
18.67
24.17
18.00
17.08
17.50
23.00
17.50
16.67
16.67
22.27
16.67
I OA P I C
(PCI)
(MHz)
37.67
41.67
43.00
37.67
50.00
37.33
48.33
36.00
34.17
35.00
46.00
35.00
33.33
33.33
44.53
33.33
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
ICS9248-99
Preliminary Product Preview
General Description
Power Groups
The ICS9248-99 is the single chip clock solution for Desktop
designs using 810/810/E style chipset. It provides all necessary
clock signals for such a system.
GNDREF, VDDREF = REF1, X1, X2
GNDPCI , VDDPCI = PCICLK [7:0]
GNDSDR, VDDSDR = SDRAM [8:0]
GNDCOR, VDDCOR = supply for PLL core
GND3V66 , VDD3V66 = 3V66
VDD48 = 48MHz, 24_48MHz,
VDDLAPIC = IOAPIC
GNDLCPU , VDDLCPU = CPUCLK [1:0]
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-99
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection.
Pin Configuration
PIN NUMBER
PIN NAME
REF1
FS3
TYPE
OUT
IN
VDD
PWR
X1
X2
IN
OUT
14.318 MHz reference clock.
Frequency select pin.
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
GND
PWR
Ground pin for 3V outputs.
3V66 [1:0]
FS0
PCICLK0
FS1
PCICLK1
FS2
PCICLK2
PCICLK [7:3]
48MHz
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
SEL24_48#
IN
25
28
24_48MHz
SDATA
SCLK
OUT
IN
IN
29
PD#
IN
3.3V clock outputs
Frequency select pin.
PCI clock output.
Frequency select pin.
PCI clock output.
Frequency select pin.
PCI clock output.
PCI clock outputs.
48MHz output clocks
Select pin for enabling 24MHz or 48MHz
H=24MHz L=48MHz
Clock output for super I/O/USB
Data input for I2C serial input, 5V tolerant input
Clock input of I2C input, 5V tolerant input
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
SDRAM [8:0]
OUT
SDRAM clock outputs
GNDLCPU
CPUCLK [1:0]
VDDLCPU
IOAPIC
VDDLAPIC
PWR
OUT
PWR
OUT
PWR
Ground pin for the CPU clocks.
CPU clock outputs.
Power pin for the CPUCLKs. 2.5V
2.5V clock output.
Power pin for the IOAPIC. 2.5V
1
2, 6, 16, 24, 27, 34,
42
3
4
5, 9, 13, 20, 26, 30,
38
8, 7
10
11
12
19, 18, 17, 15, 14
21, 22
23
31, 32, 33, 35, 36,
37, 39, 40, 41
43
44, 45
46
47
48
Third party brands and names are the property of their respective owners.
DESCRIPTION
2
ICS9248-99
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
Dummy Command Code
ACK
ICS (Slave/Receiver)
ACK
Byte Count
Dummy Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I 2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
3
ICS9248-99
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte4: Functionality and Frequency Select Register (default = 0)
Bit
Description
Bit (2, 7:4)
Bit 2,
Bit 7:4
Bit 3
Bit 1
Bit 0
CPUCLK
(MHz)
SDRAM
(MHz)
3V66
(MHz)
0
0
0
0
0
75.33
113.00
0
0
0
0
1
125.00
125.00
0
0
0
1
0
129.00
129.00
0
0
0
1
1
150.29
113.00
0
0
1
0
0
150.00
150.00
0
0
1
0
1
112.00
112.00
0
0
1
1
0
145.00
145.00
0
0
1
1
1
143.64
108.00
0
1
0
0
0
68.30
102.50
0
1
0
0
1
105.00
105.00
0
1
0
1
0
138.00
138.00
0
1
0
1
1
140.00
105.00
0
1
1
0
0
66.67
100.00
0
1
1
0
1
100.00
100.00
0
1
1
1
0
133.60
133.60
0
1
1
1
1
133.33
100.00
1
0
0
0
0
156.94
118.00
1
0
0
0
1
160.00
120.00
1
0
0
1
0
146.30
110.00
1
0
0
1
1
127.00
95.25
1
0
1
0
0
127.00
127.00
1
0
1
0
1
121.00
121.00
1
0
1
1
0
117.00
117.00
1
0
1
1
1
114.00
114.00
1
1
0
0
0
80.00
120.00
1
1
0
0
1
78.00
117.00
1
1
0
1
0
200.00
200.00
1
1
0
1
1
180.00
180.00
1
1
1
0
0
166.00
166.00
1
1
1
0
1
110.00
110.00
1
1
1
1
0
107.00
107.00
1
1
1
1
1
90.00
90.00
0 - Frequency is selected by hardware select, Latched
1 - Frequency is selected by Bit 2, 7:4
0 - Normal
1 - Spread Spectrum Enabled ± 0.25% Center Spread
0 - Running
1- Tristate all outputs
75.33
83.33
86.00
75.33
100.00
74.67
96.67
72.00
68.33
70.00
92.00
70.00
66.67
66.67
89.07
66.67
78.67
80.00
73.33
63.50
84.67
80.67
78.00
76.00
80.00
78.00
133.33
120.00
110.67
73.33
71.33
60.00
Inputs
PCICLK
(MHz
37.67
41.67
43.00
37.67
50.00
37.33
48.33
36.00
34.17
35.00
46.00
35.00
33.33
33.33
44.53
33.33
39.33
40.00
36.67
31.75
42.33
40.33
39.00
38.00
40.00
39.00
66.67
60.00
55.33
36.67
35.67
30.00
PWD
IOAPIC
(MHz)
=PCI/2 =PCI
18.83 37.67
20.83 41.67
21.50 43.00
18.83 37.67
25.00 50.00
18.67 37.33
24.17 48.33
18.00 36.00
17.08 34.17
17.50 35.00
23.00 46.00
17.50 35.00
16.67 33.33
16.67 33.33 00011
22.27 44.53 Note1
16.67 33.33
19.67 39.33
20.00 40.00
18.33 36.67
15.88 31.75
21.17 42.33
20.17 40.33
19.50 39.00
19.00 38.00
20.00 40.00
19.50 39.00
33.33 66.67
30.00 60.00
27.67 55.33
18.33 36.67
17.83 35.67
15.00 30.00
1
0
Note 1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
1) The IOAPIC Frequency change from IOAPIC=PCICLK/2 to IOAPIC=PCICLK is controlled by
IOAPC_Freq control in I 2C Byte 3 Bit 1
2) The I2C readback of the power up default indicate the revision ID in bits 2, 7:4
I 2C is a trademark of Philips Corporation
Third party brands and names are the property of their respective owners.
0
4
ICS9248-99
Preliminary Product Preview
Byte 0: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PIN# PWD
0
0
0
0
0
23
1
21,22
1
0
Byte 1: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DESCRIPTION
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
24/48MHz
48MHz
R e s e r ve d
PIN#
19
18
17
15
14
12
11
10
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PIN#
-
PWD
0
0
0
0
0
0
0
0
DESCRIPTION
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
PIN#
47
-
PWD
0
X
X
X
1
X
Bit1
-
1
Bit0
-
X
DESCRIPTION
R e s e r ve d
FS2#
FS1#
FS0#
IOAPIC
(SEL24_48#)#
FREQ_IOAPIC
=1=>IOAPIC=PCICLK/2
FREQ_IOAPIC=0=>
IOAPIC= PCICLK
FS3#
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
DESCRIPTION
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
PWD
1
1
1
1
1
1
1
1
Byte 3: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PIN#
32
33
35
36
37
39
40
41
PIN#
-
PWD
0
0
0
0
0
1
1
0
DESCRIPTION
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
Note: Don’t write into this register, writing into this
register can cause malfunction
5
ICS9248-99
Preliminary Product Preview
Shared Pin Operation Input/Output Pins
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
The I/O pins designated by (input/output) on the ICS924899 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 4-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the device’s
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
Fig. 1
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6
ICS9248-99
Preliminary Product Preview
Fig. 2a
Fig. 2b
Third party brands and names are the property of their respective owners.
7
ICS9248-99
Preliminary Product Preview
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and
CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to
be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-99 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
8
ICS9248-99
Preliminary Product Preview
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Group Timing Relationship Table
Group
CPU 66MHz
CPU 100MHz
CPU 133MHz
Offset
Tolerance
Offset
Tolerance
Offset
Tolerance
CPU to SDRAM
CPU to 3V66
2.5ns
7.5ns
500ps
500ps
5.0ns
5.0ns
500ps
500ps
0.0ns
0.0ns
500ps
500ps
SDRAM to 3V66
0.0ns
500ps
0.0ns
500ps
0.0ns
500ps
3V66 to PCI
1.5-3.5ns
500ps
1.5-3.5ns
500ps
1.5-3.5ns
500ps
PCI to PCI
USB & DOT
0.0ns
Asynch
1.0ns
N/A
0.0ns
Asynch
1.0ns
N/ A
0.0ns
Asynch
1.0ns
N/A
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Input High Voltage
2
VDD+0.3
V
VIH
Input Low Voltage
VSS-0.3
0.8
V
VIL
Input High Current
µA
VIN = VDD
-5
5
IIH
Input Low Current
µA
VIN = 0 V; Inputs with no pull-up resistors
-5
2.0
IIL1
Input Low Current
µA
VIN = 0 V; Inputs with pull-up resistors
-200
-100
IIL2
Operating
IDD3.3OP
CL = 0 pF; Select @ 66M
60
100
mA
Supply Current
Power Down
400
600
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
µA
Supply Current
Input frequency
VDD = 3.3 V;
14.318
MHz
Fi
Pin Inductance
7
nH
Lpin
Logic Inputs
5
pF
CIN
Input Capacitance1
Out put pin capacitance
6
pF
C out
X1 & X2 pins
27
45
pF
C INX
Transition Time1
Ttrans
To 1st crossing of target Freq.
3
mS
Settling Time1
Ts
From 1st crossing to 1% target Freq.
3
mS
Clk Stabilization 1
TSTAB
From VDD = 3.3 V to 1% target Freq.
3
mS
Delay
1
tPZH,tPZH
tPLZ,tPZH
output enable delay (all outputs)
output disable delay (all outputs)
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
1
1
10
10
nS
nS
ICS9248-99
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Impedance
RDSP2B1
VO = VDD*(0.5)
13.5
45
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN2B1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @MIN= 1.0V , [email protected] MAX= 2.375V
VOL @MIN= 1.2V , [email protected] MAX= 0.3V
13.5
2
45
0.4
-27
30
Ω
V
V
mA
mA
Rise Time
tr2B1
VOL = 0.4 V, VOH = 2.0 V
0.4
1.1
1.6
ns
Fall Time
tf2B1
VOH = 0.4 V, VOL = 2.0 V
0.4
1.1
1.6
ns
dt2B1
dt2B1
dt2B1
tsk2B1
VT = 1.25 V CPUMHz <133
45
49
55
%
VT = 1.25 V CPUMHz =133
40
44
50
%
VT = 1.25 V CPUMHz >133
45
51
55
%
VT = 1.25 V
30
175
ps
VT = 1.25 V CPUMHz = SDRAMMHz
VT = 1.25 V CPUMHz = SDRAMMHz
120
250
ps
330
350
ps
Duty Cycle
Skew
Jitter
1
VOH2B
VOL2B
IOH2B
IOL2B
tjcyc-cyc1
tjcyc-cyc1
CONDITIONS
MIN
TYP
-27
27
MAX UNITS
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP1
1
VO = VDD*(0.5)
12
55
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN1
VOH1
VOL1
IOH1
IOL1
1
VO = VDD*(0.5)
12
IOH = -1 mA
2.4
IOL = 1 mA
[email protected] MIN = 1.0 V, [email protected] MAX = 3.135 V -33
[email protected] MIN = 1.95 V, [email protected] MAX= 0.4
30
55
0.55
-33
38
Ω
V
V
mA
mA
Rise Time
tr11
VOL = 0.4 V, VOH = 2.4 V
0.4
1.4
1.9
ns
Fall Time
1
VOH = 2.4 V, VOL = 0.4 V
0.4
1.3
1.6
ns
1
VT = 1.5 V
45
48
55
%
1
VT = 1.5 V
VT = 1.5 V
30
270
175
500
ps
ps
Output Impedance
Duty Cycle
Skew
Jitter
1
tf1
dt1
tsk1
tjcyc-cyc
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
10
ICS9248-99
Preliminary Product Preview
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Impedance
RDSP4B1
RDSN4B1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
MIN
TYP
MAX UNITS
VO = VDD*(0.5)
9
30
Ω
VO = VDD*(0.5)
IOH = -5.5 mA
IOL = 9.0 mA
[email protected] min = 1.4 V, [email protected] MAX = 2.5 V
[email protected] MIN = 1.0 V, [email protected] MAX= 0.2
9
2
30
-36
36
0.4
-21
31
Ω
V
V
mA
mA
ns
Rise Time
tr4B1
VOL = 0.4 V, VOH = 2.0 V
0.4
0.9
1.6
Fall Time
tf4B1
dt4B1
VOH = 2.0 V, VOL = 0.4 V
0.4
1.5
1.9
ns
VT = 1.25 V
VT = 1.25 V
45
50
120
55
250
%
ps
250
ps
Duty Cycle
Jitter
Skew
1
VOH4\B
VOL4B
IOH4B
IOL4B
CONDITIONS
tjcyc-cyc
Tska1
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP3
1
VO = VDD*(0.5)
10
24
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN3
VOH3
VOL3
IOH3
IOL3
1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @MIN= 2.0 V, [email protected] MAX=3.135 V
[email protected] MIN= 1.0 V, [email protected] MAX=0.4 V
10
2.4
24
-54
54
0.4
-46
53
Ω
V
V
mA
mA
Rise Time
Tr31
VOL = 0.4 V, VOH = 2.4 V
0.4
1.0
1.6
ns
Fall Time
Tf3
1
VOH = 2.4 V, VOL = 0.4 V
0.4
1.0
1.6
ns
Dt3
1
VT = 1.5 V
45
50
55
%
50
140
250
250
ps
ps
Output Impedance
Duty Cycle
Skew
Jitter
1
1
Tsk3
tj cyc-cyc
VT = 1.5 V
VT = 1.5 V
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
11
ICS9248-99
Preliminary Product Preview
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP1
1
VO = VDD*(0.5)
12
55
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN1
VOH1
VOL1
IOH1
IOL1
1
VO = VDD*(0.5)
12
IOH = -1 mA
2.4
IOL = 1 mA
[email protected] MIN = 1.0 V, [email protected] MAX = 3.135 V -33
[email protected] MIN = 1.95 V, [email protected] MAX= 0.4
30
55
0.55
-33
38
Ω
V
V
mA
mA
Rise Time
tr11
VOL = 0.4 V, VOH = 2.4 V
0.5
2.0
2.5
ns
Fall Time
1
VOH = 2.4 V, VOL = 0.4 V
0.5
1.9
2.3
ns
1
VT = 1.5 V
45
50
55
%
1
VT = 1.5 V
VT = 1.5 V
390
110
500
500
ps
ps
Output Impedance
Duty Cycle
Skew
Jitter
1
tf1
dt1
tsk1
tjcyc-cyc
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF1, 48MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP5
1
VO = VDD*(0.5)
20
60
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN5
VOH5
VOL5
IOH5
IOL5
1
VO = VDD*(0.5)
IOH = 1 mA
IOL = -1 mA
VOH @MIN=1 V, [email protected]= 3.135 V
[email protected]=1.95 V, [email protected]=0.4 V
20
2.4
60
0.4
-23
27
Ω
V
V
mA
mA
Rise Time
tr51
VOL = 0.4 V, VOH = 2.4 V
4
nS
Fall Time
1
VOH = 2.4 V, VOL = 0.4 V
4
nS
1
VT = 1.5 V
55
%
VT = 1.5 V; Fixed Clocks
500
ps
VT = 1.5 V; Ref Clocks
VT = 1.5 V
1000
250
ps
ps
Output Impedance
1
tf5
Duty Cycle
dt5
Jitter
tjcyc-cyc1
tjcyc-cyc1
Skew
Tsk
45
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
-29
29
12
ICS9248-99
Preliminary Product Preview
SYMBOL
A
A1
A2
B
C
D
E
e
H
h
L
N
µ
X
COMMON DIMENSIONS
MIN.
NOM.
MAX.
.095
.101
.110
.008
.012
.016
.088
.090
.092
.008
.010
.0135
.005
.010
See Variations
.292
.296
.299
0.025 BSC
.400
.406
.410
.010
.013
.016
.024
.032
.040
See Variations
0°
5°
8°
.085
.093
.100
VARIATIONS
AC
AD
MIN.
.620
.720
D
NOM.
.625
.725
N
MAX.
.630
.730
48
56
SSOP Package
Ordering Information
ICS9248yF-99
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
13
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.