ICS ICS9248-136

ICS9248-136
Integrated
Circuit
Systems, Inc.
Advance Information
Frequency Generator & Integrated Buffers for K7 Processor
VDDA
*(AGPSEL)REF1
1
*(FS3)REF0
GND
X1
X2
VDDPCI
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GND
VDDAGP
AGPCLK0
AGPCLK1
GND
GND
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
SDATA
SCLK
1
PLL2
48MHz
24_48MHz
/2
XTAL
OSC
2
CPU
DIVDER
FS (3:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
MODE
AGP_SEL
Control
Logic
SDRAM
DIVDER
Stop
PCI
DIVDER
Stop
REF (1:0)
CPUCLKC0
Stop
2
SDATA
SCLK
13
5
CPUCLKT (1:0)
SDRAM (12:0)
PCICLK (4:0)
PCICLK_F
AGP
DIVDER
Config.
VDDCPU
CPUCLKT0
CPUCLKC0
CPUCLKT1
GND
VDDSDR
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM8/PD#
SDRAM9/SDRAM_STOP#
GND
SDRAM10/PCI_STOP#
SDRAM11/CPU_STOP#
SDRAM12
VDDSDR
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1 These are double strength.
FS3 FS2 FS1 FS0
PLL1
Spread
Spectrum
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Functionality
Block Diagram
X1
X2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS9248-136
Pin Configuration
Recommended Application:
Single chip clock solution for SIS 730S K7 chipset.
Output Features:
•
1 - Differential pair open drain CPU clock
•
1 - Single-ended open drain CPU clock
•
13 - SDRAM @ 3.3V
•
6- PCI @3.3V,
•
2 - AGP @ 3.3V
•
1- 48MHz, @3.3V fixed.
•
1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
•
2- REF @3.3V, 14.318MHz.
Features:
•
Up to 166MHz frequency support
•
Support FS0-FS3 trapping status bit for I2C read back.
•
Support power management: CPU, PCI, SDRAM stop
and Power down Mode from I2C programming.
•
Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
•
Uses external 14.318MHz crystal
Skew Specifications:
•
CPU - CPU: < 175ps
•
SDRAM - SDRAM < 250ps
•
PCI - PCI: < 500ps
•
CPU - SDRAM: < 500ps
•
CPU (early) - PCI: 1-4ns (typ. 2ns)
2
AGP (1:0)
Reg.
9248-136 Rev - 03/29/01
Third party brands and names are the property of their respective owners.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
100.00
100.00
100.00
100.00
112.00
125.00
124.00
133.33
133.33
150.00
111.11
110.00
166.67
90.00
48.00
45.00
SDRAM PCICLK
100.00
133.33
150.00
66.67
112.00
100.00
124.00
100.00
133.33
150.00
166.67
165.00
166.67
90.00
48.00
60.00
33.33
33.33
30.00
33.33
33.60
31.25
31.00
33.33
33.33
30.00
33.33
33.00
33.33
30.00
32.00
30.00
AGP
SEL = 0
66.67
66.67
60.00
66.67
67.20
62.50
62.00
66.67
66.67
60.00
66.67
66.00
66.67
60.00
64.00
60.00
AGP
SEL = 1
50.00
50.00
50.00
50.00
56.00
50.00
46.50
50.00
50.00
50.00
55.56
55.00
55.56
45.00
48.00
45.00
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
ICS9248-136
Advance Information
Pin Configuration
PIN NUMBER
1, 7, 15, 22, 25,
35, 43, 48
PIN NAME
TYPE
VDD
PWR
AGPSEL
REF1
FS3
REF0
IN
OUT
IN
OUT
DESCRIPTION
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
AGP frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
GND
PWR
Ground pin for 3V outputs.
X1
X2
FS1
PCICLK_F
FS2
PCICLK0
PCICLK (4:1)
AGPCLK (1:0)
FS0
48MHz
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
M ODE
IN
23
24_48M Hz
SDATA
OUT
I/O
Crystal input,nominally 14.318M Hz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
Frequency select pin.
PCI clock output.
PCI clock outputs.
AGP outputs defined as 2X PCI. These may not be stopped.
Frequency select pin.
48M Hz output clock
Pin 27, 28, 30, & 31 function select pin
0=Desktop 1=M obile mode
Clock output for super I/O/USB default is 24M Hz
24
SCLK
IN
CPU_STOP#
IN
SDRAM 11
OUT
PCI_STOP#
IN
SDRAM 10
OUT
SDRAM_STOP#
IN
SDRAM9
OUT
PD#
IN
2
3
4, 14, 18, 19, 29,
32, 39, 44
5
6
8
9
13, 12, 11, 10
17, 16
20
21
27
28
30
31
SDRAM8
26, 33, 34, 36, 37,
SDRAM (12, 7:0)
38, 40, 41, 42
2
Data pin for I C circuitry 5V tolerant
2
OUT
Clock pin of I C circuitry 5V tolerant
Stops all CPUCLKs clocks at logic 0 level, when input low
(when M ODE active).
SDRAM clock output
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low (when M ODE active).
SDRAM clock output
Stops all SDRAM clocks at logic 0 level, when input low
(when M ODE active)
SDRAM clock output
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms. (when
M ODE active)
SDRAM clock output
OUT
SDRAM clock outputs
46
CPUCLKC0
OUT
45, 47
CPUCLKT (1:0)
OUT
Complementory"" clocks of differential pair CPU outputs. These clocks are
180° out of phase with SDRAM clocks. These open drain outputs need an
external 1.5V pull-up.
"True" clocks of differential pair CPU outputs. These clocks are in phase with
SDRAM clocks. These open drain outputs need an external 1.5V pull-up.
Third party brands and names are the property of their respective owners.
2
ICS9248-136
Advance Information
General Description
The ICS9248-136 is the single chip clock solution for Desktop/Notebook designs using the SIS 630S style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-136
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDD48 = 48MHz, 24MHz, fixed PLL
VDDA = Core, PLL, X1, X2
VDDAGP=AGP, REF
MODE Pin Power Management Control Input
M ODE
Pin 21
Pin 27
Pin 28
Pin 30
Pin 31
0
SDRAM11
SDRAM10
SDRAM9
SDRAM8
1
CPU_STOP#
PCI_STOP#
SDRAM_STOP#
PD#
Third party brands and names are the property of their respective owners.
3
ICS9248-136
Advance Information
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
Bit 7 Bit 6 Bit 5 Bit 4
AGP
Bit 2
CPU
SDRAM
PCI
SEL = 0
FS3 FS2 FS1 FS0
0
0
0
0
0
100.00
100.00
33.33
66.67
0
0
0
0
1
100.00
133.33
33.33
66.67
0
0
0
1
0
100.00
150.00
30.00
60.00
0
0
0
1
1
100.00
66.67
33.33
66.67
0
0
1
0
0
112.00
112.00
33.60
67.20
0
0
1
0
1
125.00
100.00
31.25
62.50
0
0
1
1
0
124.00
124.00
31.00
62.00
0
0
1
1
1
133.33
100.00
33.33
66.67
0
1
0
0
0
133.33
133.33
33.33
66.67
0
1
0
0
1
150.00
150.00
30.00
60.00
0
1
0
1
0
111.11
166.67
33.33
66.67
0
1
0
1
1
110.00
165.00
33.00
66.00
0
1
1
0
0
166.67
166.67
33.33
66.67
0
1
1
0
1
90.00
90.00
30.00
60.00
0
1
1
1
0
48.00
48.00
32.00
64.00
Bit 2
Bit 7:4
0
1
1
1
1
45.00
60.00
30.00
60.00
1
0
0
0
0
100.30 100.30
33.43
66.87
1
0
0
0
1
100.30
133.73
33.43
66.87
1
0
0
1
0
105.00
157.50
31.50
63.00
1
0
0
1
1
100.30
66.87
33.43
66.87
1
0
1
0
0
110.00 110.00
33.00
66.00
1
0
1
0
1
103.00 103.00
34.33
68.67
1
0
1
1
0
103.00
137.33
34.33
68.67
1
0
1
1
1
133.73 100.30
33.43
66.87
1
1
0
0
0
133.73 133.73
33.43
66.87
1
1
0
0
1
140.00 140.00
35.00
70.00
1
1
0
1
0
137.33 103.00
34.33
68.67
1
1
0
1
1
137.33 137.33
34.33
68.67
1
1
1
0
0
105.00 105.00
35.00
70.00
1
1
1
0
1
138.33 138.33
34.58
69.17
1
1
1
1
0
200.00 200.00
33.33
66.67
1
1
1
1
1
104.25 139.00
34.75
69.50
0
F
r
e
q
u
e
n
c
y
i
s
s
e
l
e
c
t
e
d
b
y
h
a
r
d
w
a
r
e
s
e
l
e
c
t
,
L
a
t
c
h
e
d
I
n
p
u
t
s
Bit 3 1 - Frequency is selected by Bit , 2 7:4
al
Bit 1 10 -- SNporrem
ad Spectrum Enabled
Bit 0 10- -TRriusntantienagll outputs
PWD
AGP
SEL = 1
50.00
50.00
50.00
50.00
56.00
50.00
46.50
50.00
50.00
50.00
55.56
55.00
55.56
45.00
48.00
45.00
50.15
50.15
52.50
50.15
55.00
51.50
51.50
50.15
50.15
52.50
51.50
51.50
52.50
51.88
50.00
52.13
Spread Precentage
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
00000
Note1
0
0
0
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Note: PWD = Power-Up Default
I2C is a trademark of Philips Corporation
Third party brands and names are the property of their respective owners.
4
ICS9248-136
Advance Information
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
PIN#
PWD
Bit 7
-
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
47
46
45
-
1
1
1
1
1
1
1
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DESCRIPTION
Sel24_48
(1:24MHz, 0:48MHz)
R e s e r ve d
R e s e r ve d
R e s e r ve d
CPUCLKT0
CPUCLKC0
CPUCLKT1
R e s e r ve d
PIN#
33
34
36
37
38
40
41
42
PWD
1
1
1
1
1
1
1
1
BIT PIN# PWD
Bit 7
1
Bit 6
21
1
Bit 5
20
1
Bit 4
26
1
Bit 3
27
1
Bit 2
28
1
Bit 1
30
1
Bit 0
31
1
DESCRIPTION
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 5: AGP, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
3
1
Bit 2
2
1
Bit 1
17
1
Bit 0
16
1
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
R e s e r ve d
R e s e r ve d
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCICLK_F
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
13
12
11
10
9
8
DESCRIPTION
FS3 (Readback)
FS2 (Readback)
FS1 (Readback)
FS0 (Readback)
REF1
REF0
AGPCLK1
AGPCLK0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
5
DESCRIPTION
R e s e r ve d
24_48MHz
48MHz
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
ICS9248-136
Advance Information
Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit7
PIN#
2,3
Bit6
45
Bit5
Bit4
Bit3
Bit2
Bit1
-
Bit0
-
PWD
DESCRIPTION
0
REF strength 0=1X, 1=2X
CPUCLKT1 - Stop - Control
0
0 = C P U _ S TO P # w i l l c o n t r o l C P U C L K T 1 ,
1=CPUCLKT1 is free running even if CPU_STOP# is low
X
AGPSEL (Readback)
X
MODE (Readback)
X
C P U _ S TO P # ( R e a d b a c k )
X
P C I _ S TO P # ( R e a d b a c k )
X
S D R A M _ S TO P # ( R e a d b a c k )
AGP Speed Toggle
1
0=AGPSEL (pin2) will be determined by latch input setting,
1=AGPSEL will be opposite of latch input setting
Byte 7: Vendor ID Register
(1= enable, 0 = disable)
BIT PIN# PWD
Bit 7
0
Bit 6
0
Bit 5
1
Bit 4
0
Bit 3
1
Bit 2
0
Bit 1
0
Bit 0
0
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Third party brands and names are the property of their respective owners.
6
ICS9248-136
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . . . . .
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .
5.5 V
GND –0.5 V to VDD +0.5 V
0°C to +70°C
115°C
–65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T A = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAM ETER
Input High Voltage
Input Low Voltage
Supply Current
Input frequency
Input Capacitance 1
Transition Time 1
Settling Time
1
Clk Stabilization 1
1
Skew
Skew 1
1
SYM BOL
VIH
VIL
IDD
IDDL
Fi
C IN
C INX
T tran s
CONDITIONS
M IN
2
VSS -0.3
C L = 0 pF; Select @ 66M
VDD = 3.3 V;
Logic Inputs
X1 & X2 pins
27
To 1st crossing of target Freq.
Ts
From 1st crossing to 1% target Freq.
T STAB
From VDD = 3.3 V to 1% target Freq.
T CPU-PCI
VT = 1.5 V;
T CPU-SPREAD VT = 1.5 V;
Third party brands and names are the property of their respective owners.
7
M AX UNITS
VDD+0.3
V
0.8
V
180
mA
30
mA
M Hz
5
pF
45
pF
3
ms
ms
1.0
Guarenteed by design, not 100% tested in production.
TYP
3
ms
4.0
ms
500.0
ps
ICS9248-136
Advance Information
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
SYMBOL
ZO
Output High Voltage
VOH2B
Output Low Voltage
VOL2B
Output Low Current
IOL2B
CONDITIONS
VO = VX
Termination to
Vpull-up(external)
Termination to
Vpull-up(external)
VOL = 0.3 V
tr2B
VOL = 0.3 V, VOH = 1.2 V
0.9
ns
tf2B
VOH = 1.2 V, VOL = 0.3 V
0.9
ns
Differential voltage-AC1
VDIF
Note 2
0.4
Differential voltage-DC1
VDIF
Note 2
0.2
VX
Note 3
550
1100
mV
dt2B
tsk2B
VT = 50%
VT = 50%
VT = VX
VT = 50%
45
55
200
250
+250
%
ps
ps
ps
Rise Time
Fall Time
1
1
Differential Crossover
Voltage1
Duty Cycle1
Skew1
Jitter, Cycle-to-cycle1
Jitter, Absolute1
tjcyc-cyc2B
tjabs2B
MIN
TYP
1
MAX
UNITS
Ω
1.2
V
0.4
V
18
mA
Vpullup(external)
+ 0.6
Vpullup(external)
+ 0.6
-250
V
V
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true"
input level and VCP is the "complement" input level.
3 - Vpullup(external) = 1.5V, Min = Vpullup (external)/2-150mV; Max=(Vpullup (external)/2)+150mV
Electrical Characteristics - 24M , 48M , REF, AGP
T A = 0 - 70C; V DD = VDDL = 3.3 V +/-5%; C L = 20 pF (unless otherwise stated)
PARAM ETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Ris e Time
Fall Time
Duty Cycle
Jitter
1
SYM BOL
RD SP 5
1
RD SN 5
VO H 5
VO L 5
IO H 5
IO L 5
t r5
t f5
1
1
d t5
1
t j1 s5
1
1
CONDITIONS
M IN
TYP
M AX
UNITS
VO = VD D *(0.5)
20
60
Ω
VO = VD D *(0.5)
IO H = -14 mA
IO L = 6.0 mA
VO H = 2.0 V
VO L = 0.8 V
20
2.4
60
Ω
V
V
mA
mA
0.4
-20
10
VO L = 0.4 V, VO H = 2.4 V
4.0
ns
VO H = 2.4 V, VO L = 0.4 V
4.0
ns
55.0
%
500
ps
VT = 1.5 V
45.0
VT = 1.5 V
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-136
Advance Information
Electrical Characteristics - PCI
T A = 0 - 70C; VDD = 3.3 V +/-5%; C L = 30 pF (unless otherwise stated)
PARAM ETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
CONDITIONS
R DSP1
1
VO = VDD*(0.5)
R DSN1
VOH1
VOL1
IOH1
IOL1
1
VO = VDD*(0.5)
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
t r1
1
VOL = 0.4 V, VOH = 2.4 V
Fall Time
t f1
1
VOH = 2.4 V, VOL = 0.4 V
Duty Cycle
d t1 1
VT = 1.5 V
1
VT = 1.5 V
VT = 1.5 V
Rise Time
Skew Window
Jitter
1
SYM BOL
t sk 1
t j1s 1 1
M IN
TYP
M AX
UNITS
12
55
Ω
12
2.4
55
Ω
V
V
mA
mA
0.4
-22
25
45.0
2.0
ns
2.0
ns
55.0
%
250
ps
150
ps
M AX
UNITS
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
T A = 0 - 70C; VDD =VDDL 3.3 V +/-5%; C L = 30 pF (unless otherwise stated)
PARAM ETER
SYM BOL
Output Impedance
R DSP2 A1
R DSN2 A1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew Window ( output to output )
Jitter1
1
VOH2 A
V OL2 A
IOH2 A
IOL2 A
t r2 A1
t f2 A1
d t2 A1
t s k2 A1
t cy c-cyc
CONDITIONS
M IN
TYP
VO = VDD*(0.5)
10
20
Ω
VO = VDD*(0.5)
IOH = -28 mA
IOL = 19 mA
VOH = 2.0 V
VOL = 0.8 V
10
2.4
20
Ω
V
V
mA
mA
VOL = 0.4 V, VOH = 2.4 V
0.5
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
0.4
-42
33
2.0
ns
0.5
2
ns
45
55
%
250
ps
250.0
ps
ICS9248-136
Advance Information
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 7
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Read:
How to Write:
Controlle r (Host)
Start Bit
Address
D2(H )
Controlle r (Host)
Start Bit
Address
D3(H )
ICS (Sla ve/Re ceiver)
ICS (Slave/Rece ive r)
A CK
Byte Count
A CK
Dummy Command Code
A CK
ACK
A CK
ACK
A CK
ACK
A CK
ACK
A CK
ACK
A CK
ACK
A CK
ACK
A CK
ACK
A CK
Stop Bit
Byte 0
Dummy Byte Count
Byte 1
Byte 0
Byte 2
Byte 1
Byte 3
Byte 2
Byte 4
Byte 3
Byte 5
Byte 4
Byte 6
Byte 5
Byte 7
Byte 6
Byte 7
A CK
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
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10
ICS9248-136
Advance Information
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS9248136 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K Via to Gnd
Device
Pad
8.2K Clock trace to load
Series Term. Res.
Fig. 1
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11
ICS9248-136
Advance Information
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-136. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be
stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is
less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL
CPUCLK
PCICLK
CPU_STOP#
PD# (High)
CPUCLKT
CPUCLKC
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-136.
3. All other clocks continue to run undisturbed.
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12
ICS9248-136
Advance Information
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-136. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-136 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-136 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248-136.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
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13
ICS9248-136
Advance Information
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an asychronous input to the clock synthesizer. It is used to stop SDRAM clocks for low power operation.
SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS9248-136. All other clocks will continue to run
while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner
that guarantees the high pulse width is a full pulse.
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to the
SDRAM clocks inside the ICS9248-136.
3. All other clocks continue to run undisturbed.
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14
ICS9248-136
Advance Information
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the
clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to
a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power
down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and
CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to
be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-136 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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15
ICS9248-136
Advance Information
SYMBOL
In Millimeters
COMMON DIMENSIONS
MIN
MAX
In Inches
COMMON DIMENSIONS
MIN
MAX
A
2.413
2.794
.095
.110
A1
0.203
0.406
.008
.016
b
0.203
0.343
.008
.0135
c
D
0.127
0.254
SEE VARIATIONS
.005
.010
SEE VARIATIONS
E
10.033
10.668
.395
.420
E1
7.391
7.595
.291
.299
e
0.635 BASIC
h
0.381
L
0.508
1.016
SEE VARIATIONS
N
α
0.635
0°
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
8°
0°
8°
MAX
MIN
MAX
VARIATIONS
D mm.
N
MIN
D (inch)
28
9.398
9.652
.370
.380
34
11.303
11.557
.445
.455
48
15.748
16.002
.620
.630
56
18.288
18.542
.720
.730
20.828
21.082
.820
.830
64
Ordering Information
ICS9248yF-136-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
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16