ICS9250-14 Integrated Circuit Systems, Inc. Preliminary Product Preview Frequency Timing Generator for Pentium II Systems General Description The ICS9250-14 is a single chip clock for Intel Pentium II. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-14 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Block Diagram Features Generates the following system clocks: - 2 - CPUs @ 2.5V, up to 150MHz. - 1 - IOAPIC @ 2.5V, PCI or PCI/2MHz. - 13 SDRAMs (3.3V) @ 150MHz. - 2 - 3V66 @ 3.3V, 2x PCIMHz. - 8 - PCIs @ 3.3V. - 1 - 48MHz, @ 3.3V fixed. - 2 - REF @ 3.3V, 14.318Hz. - 1 - 24MHz, @ 3.3V fixed. Supports spread spectrum modulation , ± .25% center spread. I2C support for power management Efficient power management scheme through PD# Uses external 14.138 MHz crystal Skew Specifications CPU CPU: <175ps SDRAM - SDRAM: < 250ps 3V66 3V66: <250ps PCI PCI: <500ps CPU-SDRAM<500ps CPU(early)-PCI: MIN=1.0ns,TYP=2.0,MAX=4.0 CPU-3V66<500ps 3V66(early)-PCI: MIN=1.5ns,TYP=2.0,MAX=4.0 IOAPIC-PCI<500ps Pin Configuration Power Groups GNDREF, VDDREF = REF, Crystal GND3V66, VDD3V66 = 3V66 GNDPCI, VDDPCI = PCICLKs GNDCOR, VDDCOR = PLLCORE GND48, VDD48 = 48 GNDSDR, VDDSDR = SDRAM GNDLCPU, VDDLCPU = CPUCLK GNDLPCI, VDDLAPIC = IOAPIC Pentium II is a trademark of Intel Corporation I2C is a trademark of Philips Corporation 9250-14 Rev A 2/5/00 56-Pin 300 mil SSOP 1. These pins will have 2X drive strength. * 120K ohm pull-up to VDD on indicated inputs. PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ICS9250-14 Preliminary Product Preview Pin Descriptions PIN P I N NA M E NUMBER 1 REF1 2, 9, 10, 18, 25, VDD 32, 37, 45 TYPE DESCRIPTION OUT 3.3V, 14.318MHz reference clock output. PWR 3.3V power supply Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) 3 X1 IN 4 X2 OUT GND PWR Ground pins for 3.3V supply 3V66 (0;1) OUT 3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B PCICLK01 FS0 OUT IN 3.3V PCI clock outputs, with Synchronous CPUCLKS Logic input frequency select bit. Input latched at power on. PCICLK11 IN 3.3V PCI clock outputs, with Synchronous CPUCLKS FS1 IN Logic input frequency select bit. Input latched at power on. 5, 6, 14, 21, 28, 29, 36, 41, 49 7, 8 11 12 13, 15, 16, 17, 19, 20 PCICLK (2:7) OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS 22 PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 23 SCLK IN Clock input of I2C input 24 SDATA IN Data input for I2C serial input. 48MHz OUT 34 35 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t f o r U S B FS3 IN Logic input frequency select bit. Input latched at power on. FS2 IN Logic input frequency select bit. Input latched at power on. 24MHz OUT 3.3V fixed 24MHz output 38 26, 27, 30, 31, 39, 40, 42, 43, 44, 47, 48 50 SDRAM_F OUT 3.3V free running 100MHz SDRAM not affected by I2C SDRAM (11:0) OUT 3.3V output running 100MHz. All SDRAM outputs can be turned off t h r o u g h I 2C GNDL PWR 51, 52 CPUCLK (0:1) OUT 53, 55 54 VDDL IOAPIC FS4 PWR OUT IN Ground for 2.5V power supply for CPU & APIC 2.5V Host bus clock output. 66MHz or 100MHz depending on FS (0:1) pins Refer page 3. 2.5V power suypply for CPU, IOAPIC 2.5V clock outputs running at 16.67MHz. Logic input frequency select bit. Input latched at power on. REF01 OUT 3.3V, 14.318MHz reference clock output. 56 Note: 1. These pins will have 2X drive strength. 2 ICS9250-14 Preliminary Product Preview Frequency Selection FS4 FS3 FS2 FS1 FS0 CPU MHz SDRAM MHz 3V66 MHz PCI MHz IOAPIC MHz 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 67.81 70.00 72.01 66.67 73.01 75.00 77.00 78.01 80.00 83.00 84.49 100.00 86.08 88.00 90.00 95.00 49.90 100.00 74.85 66.58 82.84 89.81 94.80 100.50 104.78 111.77 114.77 100.00 123.75 132.74 139.75 149.69 101.71 105.00 108.01 100.00 109.51 112.50 115.50 117.01 120.00 124.51 126.74 150.00 129.12 132.00 135.00 142.50 49.90 100.00 74.85 66.58 82.84 89.81 94.80 100.50 104.78 111.77 114.77 100.00 123.75 132.74 139.75 149.69 67.81 70.00 72.01 66.67 73.01 75.00 77.00 78.01 80.00 83.00 84.49 100.00 86.08 88.00 90.00 95.00 33.26 66.66 49.90 44.39 55.23 59.88 63.20 67.00 69.86 74.52 76.51 66.66 82.50 88.49 93.16 99.79 33.90 35.00 36.00 33.33 36.50 37.50 38.50 39.00 40.00 41.50 42.25 50.00 43.04 44.00 45.00 47.50 16.63 33.33 24.95 22.19 27.61 29.94 31.60 33.50 34.93 37.26 38.26 33.33 41.25 44.25 46.58 49.90 16.95 17.50 18.00 16.67 18.25 18.75 19.25 19.50 20.00 20.75 21.12 25.00 21.52 22.00 22.50 23.75 8.32 16.67 12.47 11.10 13.81 14.97 15.80 16.75 17.46 18.63 19.13 16.67 20.62 22.12 23.29 24.95 Note: * These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation. Clock Enable Configuration PD# CPUCLK SDRAM IOAPIC 66MHz PCICLK REF, 48MHz Osc VCOs 0 LOW LOW LOW LOW LOW LOW OFF OFF 1 ON ON ON ON ON ON ON ON 3 ICS9250-14 Preliminary Product Preview Power Down Waveform Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz 4 ICS9250-14 Preliminary Product Preview General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. ICS (Slave/Receiver) The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 5 ICS9250-14 Preliminary Product Preview Byte 0: Functionality and frequency select register (Default=0) (1 = enable, 0 = disable) Bit Bit (2,7:4) Bit (2, 7:4) Bit 3 Bit 1 Bit 0 PWD Description CPUCLK MHz SDRAM MHz 3V66 MHz PCICLK IOAPIC MHz 0 0 0 0 0 67.81 101.71 67.81 33.90 16.95 0 0 0 0 1 70.00 105.00 70.00 35.00 17.50 0 0 0 1 0 72.01 108.01 72.01 36.00 18.00 0 0 0 1 1 66.67 100.00 66.67 33.33 16.67 0 0 1 0 0 73.01 109.51 73.01 36.50 18.25 0 0 1 0 1 75.00 112.50 75.00 37.50 18.75 0 0 1 1 0 77.00 115.50 77.00 38.50 19.25 0 0 1 1 1 78.01 117.01 78.01 39.00 19.50 0 1 0 0 0 80.00 120.00 80.00 40.00 20.00 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 83.00 84.49 100.00 86.08 88.00 124.51 126.74 150.00 129.12 132.00 83.00 84.49 100.00 86.08 88.00 41.50 42.25 50.00 43.04 44.00 20.75 21.12 25.00 21.52 22.00 90.00 95.00 33.26 66.66 49.90 44.39 55.23 59.88 63.20 67.00 69.86 74.52 76.51 66.66 82.50 88.49 93.16 99.79 45.00 47.50 16.63 33.33 24.95 22.19 27.61 29.94 31.60 33.50 34.93 37.26 38.26 33.33 41.25 44.25 46.58 49.90 22.50 23.75 8.32 16.67 12.47 11.10 13.81 14.97 15.80 16.75 17.46 18.63 19.13 16.67 20.62 22.12 23.29 24.95 0 1 1 1 0 90.00 135.00 0 1 1 1 1 95.00 142.50 1 0 0 0 0 49.90 49.90 1 0 0 0 1 100.00 100.00 1 0 0 1 0 74.85 74.85 1 0 0 1 1 66.58 66.58 1 0 1 0 0 82.84 82.84 1 0 1 0 1 89.81 89.81 1 0 1 1 0 94.80 94.80 1 0 1 1 1 100.50 100.50 1 1 0 0 0 104.78 104.78 1 1 0 0 1 111.77 111.77 1 1 0 1 0 114.77 114.77 1 1 0 1 1 100.00 100.00 1 1 1 0 0 123.75 123.75 1 1 1 0 1 132.74 132.74 1 1 1 1 0 139.75 139.75 1 1 1 1 1 149.69 149.69 0-Frequency is selected by hardware select, latched inputs 1- Frequency is selected by Bit 2,6:4 0- Normal 1- Spread spectrum enable ± 0.25% Center Spread 0- Running 1- Tristate all outputs Notes: 1. Default at power-up will be for latched logic inputs to define frequency, as diplayed by Bit 3. 6 XXXX Note 1 0 1 0 ICS9250-14 Preliminary Product Preview Byte 2: Control Register (1 = enable, 0 = disable) Byte 1: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 35 34 38 PWD X X X 1 1 1 1 1 Description FS3# FS0# FS2# 24_48MHz (Reserved) 48MHz (Reserved) SDRAM_F Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 20 19 17 16 15 13 12 11 PWD 1 1 1 1 1 1 1 1 Pin# 39 40 42 43 44 46 47 48 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Byte 4: Control Register (1 = enable, 0 = disable) Description PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 7 8 54 51 52 PWD 1 1 1 X 1 X 1 1 Description (Reserved) 3V66_0 3V66_0 FS4# IOAPIC FS1# CPUCLK1 CPUCLK0 Byte 5: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 26 27 30 31 PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) SDRAM11 SDRAM10 SDRAM9 SDRAM8 Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default 7 ICS9250-14 Preliminary Product Preview Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Pin Inductance Input Capacitance Transition Time Settling Time 1 1 Clk Stabilization Delay 1 1 1 SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP IDD3.3P D CONDITIONS VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M MIN 2 VSS-0.3 -5 -5 -200 CL = 0 pF; With input address to Vdd or GND Fi Lpin VDD = 3.3 V; CIN Cout CINX Logic Inputs Out put pin capacitance X1 & X2 pins Ttrans To 1st crossing of target Freq. TYP 2.0 -100 60 400 MAX UNITS VDD +0.3 V 0.8 V µA 5 µA µA 100 mA 600 µA 14.318 7 MHz nH 5 22.5 pF pF pF 3 mS 6 13.5 Ts From 1st crossing to 1% target Freq. TSTAB tP ZH ,tP ZH tP LZ,tP ZH From VDD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs) Guarenteed by design, not 100% tested in production. 8 mS 1 1 3 10 10 mS nS nS ICS9250-14 Preliminary Product Preview Electrical Characteristics - CPU TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Frequency SYMBOL FO2 Output Impedance RDSP2B1 VO = VDD*(0.5) 13.5 45 Ω Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN2B1 VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 1.0V , VOH@ MAX= 2.375V VOL @MIN= 1.2V , VOL@ MAX= 0.3V 13.5 2 45 -27 27 0.4 -27 30 Ω V V mA mA Rise Time tr2B1 VOL = 0.4 V, VOH = 2.0 V 0.4 1.6 ns Fall Time tf2B1 dt2B1 tsk2B1 VOH = 0.4 V, VOL = 2.0 V 0.4 VT = 1.25 V 45 Duty Cycle Skew VOH2B VOL2B IOH2B IOL2B tjcyc-cyc1 CONDITIONS MIN 66 TYP MAX UNITS 100 MHz 1.6 ns 55 ns VT = 1.25 V 175 ps VT = 1.25 V 250 ps 50 Jitter 1 Guarenteed by design, not 100% tested in production. Electrical Characteristics - 3V66 TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Frequency SYMBOL FO1 Output Impedance RDSP11 1 CONDITIONS MIN TYP 66 MAX UNITS MHz 12 55 Ω VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 55 0.55 -33 38 Ω V V mA mA VO = VDD*(0.5) Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN1 VOH1 VOL1 IOH1 IOL1 Rise Time tr11 VOL = 0.4 V, VOH = 2.4 V 0.4 1.6 ns Fall Time 1 VOH = 2.4 V, VOL = 0.4 V 0.4 1.6 ns 1 VT = 1.5 V 45 55 % 1 VT = 1.5 V VT = 1.5 V 175 500 ps ps Duty Cycle Skew Jitter 1 tf1 dt1 tsk1 tjcyc-cyc Guarenteed by design, not 100% tested in production. 9 ICS9250-14 Preliminary Product Preview Electrical Characteristics - IOAPIC TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Frequency Output Frequency SYMBOL FO4 FO5 Output Impedance RDSP4B1 VO = VDD*(0.5) 9 30 Ω Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN4B1 VO = VDD*(0.5) IOH = -5.5 mA IOL = 9.0 mA VOH@ min = 1.4 V, VOH@ MAX = 2.5 V VOL@ MIN = 1.0 V, VOL@ MAX= 0.2 9 2 30 -36 36 0.4 -21 31 Ω V V mA mA Rise Time tr4B1 VOL = 0.4 V, VOH = 2.0 V 0.4 1.6 nS Fall Time tf4B1 dt4B1 VOH = 2.0 V, VOL = 0.4 V 0.4 1.6 nS VT = 1.25 V VT = 1.25 V 45 55 500 % pS Duty Cycle Jitter 1 VOH4\B VOL4B IOH4B IOL4B tjcyc-cyc CONDITIONS MIN TYP 16.67 33 MAX UNITS MHz MHz Guarenteed by design, not 100% tested in production. Electrical Characteristics - SDRAM TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER Output Frequency SYMBOL FO3 Output Impedance RDSP 3 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN3 VOH3 VOL3 IOH3 IOL3 Rise Time Tr3 Fall Time Duty Cycle Skew Jitter 1 1 Tf3 1 1 1 Dt3 1 1 Tsk3 tj cyc-cyc CONDITIONS MIN TYP 100 MAX UNITS MHz VO = VDD *(0.5) 10 24 Ω VO = VDD *(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN = 2.0 V, VOH@ MAX=3.135 V VOL@ MIN = 1.0 V, VOL@ MAX=0.4 V 10 2.4 24 -54 54 0.4 -46 53 Ω V V mA mA VOL = 0.4 V, VOH = 2.4 V 0.4 1.6 ns VOH = 2.4 V, VOL = 0.4 V 0.4 1.6 ns VT = 1.5 V 45 55 % 250 250 ps ps VT = 1.5 V VT = 1.5 V Guarenteed by design, not 100% tested in production. 10 ICS9250-14 Preliminary Product Preview Electrical Characteristics - PCI TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Frequency SYMBOL FO1 Output Impedance RDSP11 VO = VDD*(0.5) 12 55 Ω Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN11 VOH1 VOL1 IOH1 IOL1 VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 55 0.55 -33 38 Ω V V mA mA Rise Time tr11 VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns Fall Time 1 VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 VT = 1.5 V 45 55 % 1 VT = 1.5 V VT = 1.5 V 500 500 ps ps Duty Cycle Skew Jitter 1 tf1 dt1 tsk1 tjcyc-cyc CONDITIONS MIN TYP 33 MAX UNITS MHz Guarenteed by design, not 100% tested in production. Electrical Characteristics - 48M, REF TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated) PARAMETER Output Frequency Output Frequency SYMBOL FO48M FOREF Output Impedance RDSP5 1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN5 VOH5 VOL5 IOH5 IOL5 Rise Time tr5 Fall Time Duty Cycle Jitter tf5 1 1 1 dt5 1 1 tjcyc-cyc 1 tjcyc-cyc Skew 1 Tsk CONDITIONS MIN TYP 48 14.318 MAX UNITS MHz MHz VO = VDD *(0.5) 20 60 Ω VO = VDD *(0.5) IOH = 1 mA IOL = -1 mA VOH @MIN =1 V, VOH@MAX= 3.135 V VOL@MIN =1.95 V, VOL@MIN=0.4 V 20 2.4 60 0.4 -23 27 Ω V V mA mA -29 29 VOL = 0.4 V, VOH = 2.4 V 1.8 4 nS VOH = 2.4 V, VOL = 0.4 V 1.7 4 nS 55 % VT = 1.5 V; Fixed Clocks 500 pS VT = 1.5 V; Ref Clocks VT = 1.5 V 1000 250 pS pS VT = 1.5 V 45 Guarenteed by design, not 100% tested in production. 11 ICS9250-14 Preliminary Product Preview Group Offset Waveforms Group Skews at Common Transition Edges: CPU & IOAPIC load (lumped) = 20pf; PCI, SDRAM, 3V66 LOAD (LUMPED) = 30pf. GROUP SYMBOL CONDITIONS MIN CPU @ 1.25V, 3V66 @ 1.5V (Note: 180° CPU (at 66MHz) to 0 SCPU1-3V66 offset between CPU & 3V66 3V66 CPU (at 100MHz) to CPU @ 1.25V, SDRAM @ 1.5V (Note: 180° SCPU2-SDRAM 0 SDRAM offset between CPU & SDRAM 1.5 3V66 to PCI S3V66-PCI 3V66 @ 1.5V, PCI @ 1.5V 0 IOAPIC to PCI SIOAPIC-PCI IOAPIC @ 1.25V, PCI @1.5V 12 TYP 2.1 MAX UNITS 500 ps 500 ps 4 500 ns ps ICS9250-14 Preliminary Product Preview Pin 1 Index Area .093 DIA. PIN (Optional) D/2 E/2 PARTING LINE H L DETAIL “A” TOP VIEW BOTTOM VIEW -eA2 c SEE DETAIL “A” A .004 C -E- A A1 A2 B c D E e H h L N µ SEATING PLANE -DEND VIEW SYMBOL B COMMON DIMENSIONS MIN. NOM. MAX. .095 .102 .110 .008 .012 .016 .087 .090 .094 .008 .0135 .005 .010 See Variations .291 .295 .299 0.025 BSC .395 .420 .010 .013 .016 .020 .040 See Variations 0° 8° SIDE VIEW VARIATIONS AD MIN. .720 -C- A1 D NOM. .725 N MAX. .730 56 “For current dimensional specifications, see JEDEC 95.” Dimensions in inches 56 Pin 300 mil SSOP Package Ordering Information ICS9250yF-14-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 13 PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.