Integrated Circuit Systems, Inc. ICS9248-77 Frequency Timing Generator for PENTIUM II Systems General Description Pin Configuration The ICS9248-77 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the ICS9212-01. Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS924877 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. The CPU/2 clocks are inputs to the DRCG. Features Generates the following system clocks: - 3 - CPUs @ 2.5V, up to 150MHz. - 3 - IOAPIC @ 2.5V, PCI or PCI/2 - 3 - 3V66MHz @ 3.3V. - 11 - PCIs @ 3.3V. - 1 - 48MHz, @ 3.3V fixed. - 1 - 24MHz, @ 3.3V fixed. - 1 - CPU/2, @ 2.5V. ± .25% center spread, or 0 to -.5% down spread. Uses external 14.318MHz crystal. 48-pin SSOP *120K ohm pull-up to VDD on indicated inputs. Block Diagram Key Specification CPU Output Jitter: <250ps CPU/2 Output Jitter. <250ps IOAPIC Output Jitter: <500ps 48MHz, 3V66, PCI Output Jitter: <500ps Ref Output Jitter. <1000ps CPU Output Skew: <175ps IOAPIC Output Skew <250ps PCI Output Skew: <500ps 3V66 Output Skew <250ps CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads) 3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads) CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads) 9248-77 Rev C 10/20/99 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-77 Power Groups: VDDREF, GNDREF = REF, X1, X2 GNDPCI, VDDPCI = PCICLK VDD66, GND66 = 3V66 VDD48, GND48 = 48MHz VDDCOR, GNDCOR = PLL Core VDDLCPU/2 , GNDLCPU/2 = CPU/2 VDDLIOAPIC, GNDIOAPIC = IOAPIC Pin Descriptions Pin number Pin name 1, 7, 13, 19, 25, 31 GND 2 REF0 REF1 3 SEL24_48 4, 10, 16, 23, VDD 28, 35 5 X1 6 X2 8 9 11 12 26 Description Ground pins 14.318MHz reference clock outputs at 3.3V 14.318MHz reference clock outputs at 3.3V Logic input to select 24 or 48MHz for pin 26 output PWR Power pins 3.3V IN OUT PCICLK_F OUT FS0 PCICLK1 FS1 PCICLK2 FS2 PCICLK3 FS3 IN OUT IN OUT IN OUT IN XTAL_IN 14.318MHz crystal input XTAL_OUT Crystal output Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not affected by the PCI_STOP# input. Logic - input for frequency selection PCI clock output at 3.3V. Synchronous to CPU clocks. Logic - input for frequency selection PCI clock output at 3.3V. Synchronous to CPU clocks. Logic - input for frequency selection PCI clock output at 3.3V. Synchronous to CPU clocks. Logic - input for frequency selection OUT PCI clock outputs at 3.3V. Synchronous to CPU clocks. 14, 15, 17, 18, 20, PCICLK [4:10] 21, 22 24 Type PWR OUT OUT IN PD# 24_48MHz FREQ_APIC 27 48MHz/SEL_3V66 29 SCLK 30 SDATA This asynchronous input powers down the chip when drive active(Low). The internal PLLs are disabled and all the output clocks are held at a Low state. 24 or 48MHz output selectable by OUT SEL24_48# (0=48MHz 1=24MHz) IN Logic input for frequency selection of IOAPIC Fixed 48MHz clock output. 3.3V / Logic input to select the OUT/IN frequency of the 3V66 outputs 2 IN Clock input of I C input IN IN 2 32, 33, 34 3V66[0:2] OUT 36 37, 38, 40 39 41 42 43 45 44, 46, 47 GNDLCPU CPUCLK[0:2] VDDLCPU GNDLCPU/2 CPU/2 VDDLCPU/2 GNDLIOAPIC IOAPIC[0:2] PWR OUT PWR PWR OUT PWR PWR OUT Data input for I C serial input. 3.3V clock outputs. These outputs are stopped when CPU_STOP# is driven active.. Ground pin for the CPUCLKs Host bus clock output at 2.5V. Power pin for the CPUCLKs. 2.5V Ground pin for the CPU/2 clocks. 2.5V clock outputs at 1/2 CPU frequency. Power pin for the CPU/2 clocks. 2.5V Ground pin for the IOAPIC outputs. IOAPIC clocks at 2.5V. Synchronous with CPUCLKs 48 VDDLIOAPIC PWR Power pin for the IOAPIC outputs. 2.5V. 2 ICS9248-77 Frequency Selection 3V66 MHz IOAPIC MHz FS3 FS2 FS1 FS0 CPU MHz CPU/2 MHz PCI MHz SEL_3V66=0 SEL_3V66=1 0 0 0 0 105 52.5 35 70 70 17.5 35 0 0 0 1 75 37.5 37.5 64* 75 18.75 37.5 0 0 1 0 100.3 50.15 33.4 66.6 66.6 16.7 33.4 0 0 1 1 66.8 33.4 33.4 66.6 66.6 16.67 33.4 FREQ_APIC=0 FREQ_APCI=1 0 1 0 0 110 55 36.6 64* 73.3 18.3 36.6 0 1 0 1 115 57.5 38.3 64* 76.6 19.16 38.3 0 1 1 0 117 58.5 39 64* 78 19.5 39 0 1 1 1 120 60 40 64* 80 20 40 1 0 0 0 125 62.5 41.6 64* 83.3 20.8 41.6 1 0 0 1 127 63.5 42.3 64* 84.6 21.16 42.3 1 0 1 0 133.3 66.5 33.3 66.6 66.6 16.6 33.3 1 0 1 1 135 67.5 33.75 67.5 67.5 16.8 33.75 1 1 0 0 137 68.5 34.25 68.5 68.5 17.125 34.25 1 1 0 1 140 70 35 70 70 17.5 35 1 1 1 1 1 1 0 1 145 150 72.5 75 36.25 37.5 64* 64* 72.5 75 18.125 18.75 36.25 37.5 Note: * These output frequencies are Not synchronous to CPUCLK and Do Not have Spread Spectrum modulation. 3 ICS9248-77 Power Management Features: PD# CPUCLK CPU/2 IOAPIC 3V66 PCI PCI_F REF. 48MHz Osc VCOs 0 LOW LOW LOW LOW LOW LOW LOW OFF OFF 1 ON ON ON ON ON ON ON ON ON Note: 1. LOW means outputs held static LOW as per latency requirement next page. 2. On means active. 3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs. Power Management Requirements: Latency Signal PD# Signal State 1 (normal operation) 0 (power down) No. of rising edges of PCICLK 3mS 2max. Note: 1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/ high to the first valid clock comes out of the device. 2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device. 4 ICS9248-77 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK Byte Count ACK Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. ICS (Slave/Receiver) The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 5 ICS9248-77 Serial Configuration Command Bitmap Byte 0: Functionality and frequency select register (Default = 0) Bit Bit 7 Description PWD 0 - ±0.25% Center Spread Spectrum 1 - Down Spread Spectrum 0 to -.5% 0 3V66 PCICLK 3V66_SEL=0 3V66_SEL=1 0000 105 70 70 35 0001 75 64* 75 37.5 0010 100.3 66.6 66.6 33.4 0011 66.8 66.6 66.6 33.4 0100 110 64* 73.3 36.6 0101 115 64* 76.6 38.3 Bit 0110 117 64* 78 39 0111 120 64* 80 40 (2, 6:4) 1000 125 64* 83.3 41.6 1001 127 64* 84.6 42.3 1010 133.3 66.6 66.6 33.3 1011 135 67.5 67.5 33.75 1100 137 68.5 68.5 34.25 1101 140 70 70 35 1110 145 64* 72.5 36.25 1111 150 64* 75 37.5 0 F r e q u e n c y i s s e l e c t e d b y h a r d w a r e s e l e c t , l a t c h e d i n p u t s Bit 3 1 - Frequency is selected by Bit 2, 6:4 al Bit 1 10 -- SNporrem ad spectrum enabled Running Bit 0 10 -- T ristate all outputs Bit (2, 6:4) CPUCLK IOAPIC FREQ_APIC=0 FREQ_APIC=1 17.5 35 18.75 37.5 16.7 33.4 16.67 33.4 18.3 36.6 19.16 38.3 19.5 39 20 40 20.8 41.6 21.16 42.3 16.6 33.3 16.8 33.75 17.125 34.25 17.5 35 18.125 36.25 18.75 37.5 Note 1: Default at power-up will be for latched logic inputs to define frequency. * These output frequencies are not synchronous to CPUCLK and do not have Spread Spectrum modulation. 6 Note 1 0 0 0 ICS9248-77 Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 40 38 37 42 47 46 2 3 PWD 1 1 1 1 1 1 1 1 Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable) Description CPUCLK 0 CPUCLK 1 CPUCLK 2 CPU/2 IOAPIC0 IOAPIC1 REF1 REF0 Bit Pin # PWD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 18 17 15 14 12 11 9 8 1 1 1 1 1 1 1 1 Description PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK_F Note: 1. Inactive means outputs are held LOW and are disabled from switching. Notef: 1. Inactive means outputs are held LOW and are disabled from switching. Byte 3: 3V66 Active/Inactive Register (1 = enable, 0 = disable) Byte 4: PCI Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 34 33 32 - PWD 1 1 1 X 1 1 X X Description 3V66_0 3V66_1 3V66_2 FS1# (Reserved) (Reserved) FS3# FS2# Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Note: 1. Inactive means outputs are held LOW and are disabled from switching. Bit Pin # PWD - 0 0 0 0 0 1 1 0 Description R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d PWD 1 1 X 1 1 1 1 1 Description 24_48MHz 48MHz FS0 PCICLK10 PCICLK9 PCICLK8 (Reserved) (Reserved) Note: 1. Inactive means outputs are held LOW and are disabled from switching. Byte 5: Active/Inactive Register (1= enable, 0 = disable) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin # 26 27 22 21 20 - (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) Note: Dont write into this register, writing into this register can cause malfunction 7 ICS9248-77 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. 8 ICS9248-77 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V GND 0.5 V to VDD +0.5 V 0°C to +70°C 65°C to +150°C 115°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70º C; VDD, VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resistors Operating Supply Current Input frequency Input Capacitance1 Transition Time 1 1 Settling Time Clk Stabilization 1 1 IDD3.3OP 100 IDD3.3OP 133 Fi CIN CINX CL = 0 pF; Select @ 100 MHz CL = 0 pF; Select @ 133 MHz VDD = 3.3 V; Logic Inputs X1 & X2 pins Ttrans To 1st crossing of target Freq. Ts TSTAB From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. MIN 2 VSS-0.3 TYP 11 0.1 2.0 -100 81 85 14.318 27 36 -5 -200 5 MAX UNITS VDD+0.3 V 0.8 V µA 5 µA µA 160 160 16 5 45 mA mA MHz pF pF 3 ms 3 ms 3 ms Guaranteed by design, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70º C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Power Down Supply Current 1 SYMBOL IDD2.5OP 100 IDD2.5OP 133 IDD2.5P D CONDITIONS CL = 0 pF; Select @ 100 MHz CL = 0 pF; Select @ 133 MHz CL = 0 pF; PWRDWN# = 0 Guaranteed by design, not 100% tested in production. 9 MIN TYP 16 19 0.1 MAX 75 90 100 UNITS mA mA µA ICS9248-77 Group Offset Group CPU to 3V66 3V66 to PCI CPU to IOAPIC Offset 0.0-1.5ns CPU leads 1.5-4.0ns 3V66 leads 1.5-4.0ns CPU leads Measurement Loads CPU @ 20pF, 3V66 @ 30pF 3V66 @ 30pF, PCI @ 30pF CPU @ 20pF, IOAPIC @ 20pF Measure Points CPU @1.25V, 3V66 @ 1.5V 3V66 @ 1.5V, PCI @ 1.5V CPU @1.25V, IOAPIC @ 1.5V No te: 1 . All o ffsets are to be meas u red at ris in g edg es. Electrical Characteristics - CPUCLK TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current SYMBOL VOH2B VOL2B IOH2B IOL2B MIN 2 19 TYP 2.24 0.31 -31 25 MAX UNITS V 0.4 V -19 mA mA Rise Time tr2B 1 VOL = 0.4 V, VOH = 2.0 V 1.35 1.6 ns Fall Time tf2B1 VOH = 2.0 V, VOL = 0.4 V 1.4 1.6 ns Duty Cycle d t2B1 VT = 1.25 V 47 55 % 1 VT = 1.25 V 63 175 ps VT = 1.25 V 125 250 ps VT = 1.25 V VT = 1.25 V 65 150 ps 148 +250 ps TYP 2.24 0.31 -31 26 MAX UNITS V 0.4 V -19 mA mA Skew tsk2B Jitter, Cycle-to-cycle tjcyc-cyc2B1 tj1s2B1 tjabs2B1 Jitter, One Sigma Jitter, Absolute 1 CONDITIONS IOH = -12.0 mA IOL = 12.0 mA VOH = 1.7 V VOL = 0.7 V 45 -250 Guaranteed by design, not 100% tested in production. Electrical Characteristics - CPU/2 TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current SYMBOL VOH2B VOL2B IOH2B IOL2B CONDITIONS IOH = -12.0 mA IOL = 12.0 mA VOH = 1.7 V VOL = 0.7 V 19 Rise Time tr2B 1 VOL = 0.4 V, VOH = 2.0 V Fall Time tf2B1 VOH = 2.0 V, VOL = 0.4 V Duty Cycle d t2B1 VT = 1.25 V Jitter, Cycle-to-cycle tjcyc-cyc2B1 VT = 1.25 V Jitter, One Sigma Jitter, Absolute 1 1 tj1s2B tjabs2B1 MIN 2 45 VT = 1.25 V VT = 1.25 V -250 Guaranteed by design, not 100% tested in production. 10 1.2 1.6 ns 1.2 1.6 ns 49 55 % 125 250 ps 50 150 ps 97 +250 ps ICS9248-77 Electrical Characteristics - 3V66 TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -11 mA 2.4 Output High Voltage VOH1 Output Low Voltage VOL1 IOL = 9.4 mA Output High Current IOH1 VOH = 2.0 V Output Low Current IOL1 VOL = 0.8 V 16 Rise Time1 Fall Time 1 Duty Cycle 1 1 Skew Jitter, Cycle-to-cycle1 1 Jitter, One Sigma Jitter, Absolute1 1 TYP 3.1 0.17 -51 41 MAX UNITS V 0.4 V -22 mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 1.8 2 ns tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 1.6 2 ns dt1 VT = 1.5 V 45 49 55 % tsk1 Tjcyc-cyc1 VT = 1.5 V VT = 1.5 V 50 299 250 500 ps ps tj1s1 VT = 1.5 V 87 150 ps tjabs1 VT = 1.5 V 235 500 ps -500 Guaranteed by design, not 100% tested in production. Electrical Characteristics - PCICLK TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output High Voltage VOH1 IOH = -11 mA 2.4 Output Low Voltage VOL1 IOL = 9.4 mA Output High Current IOH1 VOH = 2.0 V Output Low Current IOL1 VOL = 0.8 V 16 1 Rise Time 1 Fall Time 1 Duty Cycle 1 Skew Jitter, Cycle-to-cycle1 Jitter, One Sigma 1 Jitter, Absolute 1 TYP 3.1 0.16 -50 42 MAX UNITS V 0.4 V -22 mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 2 2 ns tf1 VOH = 2.4 V, VOL = 0.4 V 1.74 2 ns dt1 VT = 1.5 V 49 55 % tsk1 Tjcyc-cyc1 VT = 1.5 V VT = 1.5 V 290 290 500 500 ps ps tj1s1 VT = 1.5 V 30 150 ps tjabs1 VT = 1.5 V 121 250 ps 45 -250 1 Guaranteed by design, not 100% tested in production. 11 ICS9248-77 Electrical Characteristics - 48 MHz TA = 0 - 70ºC; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -16 mA 2.4 Output High Voltage VOH5 Output Low Voltage VOL5 IOL = 9 mA Output High Current IOH5 VOH = 2.0 V Output Low Current IOL5 VOL = 0.8 V 16 Rise Time1 Fall Time 1 1 Duty Cycle 1 Jitter, Cycle-to-cycle 1 Jitter, One Sigma Jitter, Absolute1 1 TYP 2.62 0.3 -27 22 MAX UNITS V 0.4 V -22 mA mA tr5 VOL = 0.4 V, VOH = 2.4 V 2.1 4 ns tf5 VOH = 2.4 V, VOL = 0.4 V 2.2 4 ns dt5 Tjcyc-cyc5 VT = 1.5 V VT = 1.5 V 51 488 55 500 % ps tj1s5 VT = 1.5 V 0.29 3 % tjabs5 VT = 1.5 V 1.05 5 % 45 -5 Guaranteed by design, not 100% tested in production. Electrical Characteristics - REF TA = 0 - 70ºC; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -16 mA 2.4 Output High Voltage VOH5 Output Low Voltage VOL5 IOL = 9 mA Output High Current IOH5 VOH = 2.0 V Output Low Current IOL5 VOL = 0.8 V 16 Rise Time1 Fall Time 1 1 Duty Cycle 1 Jitter, Cycle-to-cycle 1 Jitter, One Sigma Jitter, Absolute1 1 TYP 2.6 0.3 -26 22 MAX UNITS V 0.4 V -22 mA mA tr5 VOL = 0.4 V, VOH = 2.4 V 2.2 4 ns tf5 VOH = 2.4 V, VOL = 0.4 V 2.2 4 ns dt5 Tjcyc-cyc5 VT = 1.5 V VT = 1.5 V 52 600 55 1000 % ps tj1s5 VT = 1.5 V 0.44 3 % tjabs5 VT = 1.5 V 0.94 5 % 45 -5 Guaranteed by design, not 100% tested in production. 12 ICS9248-77 Electrical Characteristics - IOAPIC TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output High Voltage VOH4B IOH = -12.0 mA 2 Output Low Voltage VOL4B IOL = 12.0 mA Output High Current IOH4B VOH = 1.7 V Output Low Current IOL4B VOL = 0.7 V 19 Rise Time1 Fall Time 1 1 Duty Cycle 1 Skew 1 Jitter, Cycle-to-cycle 1 Jitter, One Sigma Jitter, Absolute1 1 TYP 2.24 0.31 -31 26 MAX UNITS V 0.4 V -19 mA mA Tr4B VOL = 0.4 V, VOH = 2.0 V 1.46 2 ns Tf4B VOH = 2.0 V, VOL = 0.4 V 1.44 2 ns Dt4B tsk4B Tjcyc-cyc4B VT = 1.25 V VT = 1.25 V VT = 1.25 V 49 139 167 55 250 500 % ps ps Tj1s4B VT = 1.25 V 30 150 ps Tjabs4B VT = 1.25 V 104 250 ps 45 -250 Guaranteed by design, not 100% tested in production. 13 ICS9248-77 SSOP Package SYMBOL A A1 A2 B C D E e H h L N µ X COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0° 5° 8° .085 .093 .100 VARIATIONS MIN. .620 AC D NOM. .625 N MAX. .630 48 Ordering Information ICS9248yF-77 Example: ICS XXXX y F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 14 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.