ICS ICS9248YF-72

ICS9248-72
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Frequency Timing Generator for PENTIUM II Systems
General Description
Features
The ICS9248-72 is a main clock synthesizer chip for Pentium
II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used
with a Direct Rambus Clock Generator(DRCG) chip such as
the ICS9211-01.
•
•
•
Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI by
8dB to 10dB. This simplifies EMI qualification without resorting
to board design iterations or costly shielding. The ICS924872 employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
The CPU/2 clocks are inputs to the DRCG.
Block Diagram
•
•
Up to 200MHz frequency support.
Power Down feature.
Spread Spectrum for EMI control
(0 to –0.5% down spread , + 0.25% center spread)
I2C interface.
VDDL=2.5V,VDD=3.3V
Key Specification
•
•
•
•
•
•
•
•
•
•
•
•
CPU Output Jitter: <250ps
CPU/2 Output Jitter. <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
Ref Output Jitter. <1000ps
CPU Output Skew: <175ps
IOAPIC Output Skew <250ps
PCI Output Skew: <500ps
3V66 Output Skew <250ps
CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads)
3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads)
CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)
Pin Configuration
48-pin SSOP
* 250K ohm pull-up to VDD on indicated inputs.
1.These pins will have 2X drive strength
9248-72 Rev B 7/28/99
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
ICS9248-72
Preliminary Product Preview
Power Groups:
VDDREF, GNDREF = REF, X1, X2
GNDPCI, VDDPCI = PCICLK
VDD66, GND66 = 3V66
VDD48, GND48 = 48MHz
VDDCOR, GNDCOR = PLL Core
VDDLCPU/2 , GNDLCPU/2 = CPU/2
VDDLIOAPIC, GNDIOAPIC = IOAPIC
Pin Descriptions
Pin number
Pin name
Type
1, 45, 46
2
3, 24, 29, 33
4
5
6, 14, 20, 26, 32
IOAPIC[2:0]
REF0
VDD
X1
X2
GND
FS [2:1]
PCICLK [1:0]
VDDPCI
Output
Output
Power
Input
Output
Power
IN
Output
Power
2.5V IOAPIC clock outputs
3.3V, 14.318 MHz reference clock output.
3.3 V power
14.318 MHz crystal input
14.318 MHz crystal output
Ground
Frequency select pins. Latched Inputs determins the CPU & PCI frequencies.
3.3 V PCI clock outputs, generating timing requirements for
3.3 V power for the PCI clock outputs
PCICLK [9:2]
Output
3.3 V PCI clock outputs
3V66
Output
3.3 V 66 MHz clock output, fixed frequency clock typically used with AGP
SEL 133/100#
Input
FS0
IN
48 MHz
Output
8, 7
9,17
19, 18, 16, 15, 13,
12, 11, 10
23, 22, 21
25
27
SEL24/48
28
24_48MHz#
IN
Output
IN
30
SCLK
31
PD#
Input
34
36, 35
37, 40
41
42
43
47
48
SDATA
CPUCLK [1:0]
VDDLCPU
GNDLCPU/2
CPU/2
VDDLCPU/2
GNDLIOAPIC
GNDREF
IN
0utput
Power
Power
Output
Power
Power
Power
Description
control for the frequency of clocks at the CPU output pins. If logic "0" is used the
100 MHz frequency is selected. If Logic "1" is used, the 133 MHz frequency is
selected. The PCI clock is multiplexed to run at 33.3 MHz for both selected cases.
Frequency select pin. Latched Inputs determins the CPU & PCI frequencies.
3.3 V 48 MHz clock output, fixed frequency clock typically used with USB
devices
48/24 MHz select option. Active low = 48 MHz output. Active High = 24
MHz
3.3V 48 or 24 MHz clock output, fixed frequency clock typically used with
USB devices.
Clock input of I2C input
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped.
Data input for I2C serial input.
2.5 V CPU and Host clock outputs
2.5 V power for the CPU and Host clock outputs
Ground for the CPU and Host clock outputs
output running at 1/2 CPU clock frequency.Synchronous to the CPU outputs.
2.5 V power for the CPU/2 clock outputs
Ground for IOAPIC clocks
Ground for 14.318 MHz reference clock outputs
2
ICS9248-72
Preliminary Product Preview
Functionality
VDD = 3.3V±5%, VDDL = 2.5V ±5% TA= 0 to 70°C
Crystal (X1, X2) = 14.31818MHz
FS2
(MHz)
1
SEL133/100#
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
FS1
(MHz)
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
FS0
(MHz)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
CPU
(MHz)
133.30
138.01
142.91
147.95
152.49
156.99
162.02
180.00
100.23
105.00
113.99
120.00
128.51
200.01
170.03
66.82
CPU/2
(MHz)
66.65
69.01
71.45
73.98
76.24
78.49
81.01
89.99
50.11
52.49
56.99
59.99
64.25
100.00
85.01
33.40
PCI
(MHz)
33.325
34.505
35.725
36.99
38.12
39.245
40.505
30.00
33.405
35
37.83
40.00
32.125
33.33
28.33
33.40
3V66
(MHz)
66.65
69.01
71.45
73.98
76.24
78.49
81.01
60.00
66.81
70.00
75.66
80.00
64.25
66.66
56.66
66.80
IOAPIC
(MHz)
16.66
17.25
17.86
18.49
19.06
19.62
20.25
15.00
16.70
17.50
18.91
20.00
16.06
16.66
14.16
16.7
ICS9248-72 Power Management Features:
PD#
CPUCLK CPU/2 IOAPIC
3V66
PCI
PCI_F
REF.
48MHz
Osc
VCOs
0
LOW
LOW
LOW
LOW
LOW
LOW
LOW
OFF
OFF
1
ON
ON
ON
ON
ON
ON
ON
ON
ON
Note:
1. LOW means outputs held static LOW as per latency requirement next page.
2. On means active.
3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
Power Management Requirements:
Latency
Singal
PD#
Singal State
1 (normal operation)
0 (power down)
No. of rising edges
of PCICLK
3mS
2max.
Note:
1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/
high to the first valid clock comes out of the device.
2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.
3
ICS9248-72
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
Dummy Command Code
ACK
ACK
Byte Count
Dummy Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
ICS (Slave/Receiver)
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
4
ICS9248-72
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
Bit
Bit
(7:4)
Bit3
Bit2
Bit1
Bit0
CPUCLK
CPU/2
3V66
7
6
5
4
1
1
1
1
133.30
66.65
66.65
1
1
1
0
138.01
69.01
69.01
1
1
0
1
142.91
71.45
71.45
1
1
0
0
147.95
73.98
73.98
1
0
1
1
152.49
76.24
76.24
1
0
1
0
156.99
78.49
78.49
1
0
0
1
162.02
81.01
81.01
1
0
0
0
180.00
89.99
60.00
0
1
1
1
100.23
50.11
66.81
0
1
1
0
105.00
52.49
70.00
0
1
0
1
113.99
56.99
75.66
0
1
0
0
120.00
59.99
80.00
0
0
1
1
128.51
64.25
64.25
0
0
1
0
200.01
100.00
66.66
0
0
0
1
170.03
85.01
56.66
0
0
0
0
66.82
33.40
66.80
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 7:4
0- Spread spectrum center spread type ±0.25%
1- Spread spectrum down spread type 0 to - 0.5%
0- Normal
1- Spread spectrum enable
0= Running
1= Tristate all outputs
PCICLK
IOAPIC
33.325
34.505
35.725
36.99
38.12
39.245
40.505
30.00
33.405
35
37.83
40.00
32.125
33.33
28.33
33.40
16.66
17.25
17.86
18.49
19.06
19.62
20.25
15.00
16.70
17.50
18.91
20.00
16.06
16.66
14.16
16.7
Note1: Default at power-up will be for latched logic inputs to define frequency.
5
0
XXXX
Note1
0
1
1
0
ICS9248-72
Preliminary Product Preview
Byte 1: CPU, CPU/2, 48MHz Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
27
28
42
39
36
35
PWD
1
1
1
1
1
1
Byte 2: PCICLK Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
48MHz
24_48 MHz
(Reserved)
CPU/2
(Reserved)
CPUCLK 2
CPUCLK 1
CPUCLK 0
Pin #
16
15
13
12
11
10
8
7
PWD
1
1
1
1
1
1
1
1
Description
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: 3V66, REF Register Active/Inactive
(1 = enable, 0 = disable)
Byte 4: IOAPIC, REF Register Active/Inactive
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
23
22
21
19
18
PWD
0
1
1
1
X
X
1
1
Description
(Reserved)
3V66_2
3V66_1
3V66_0
FS2#
(SEL24 48#)#
PCICLK9
PCICLK8
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 5: CPU, IOAPIC Register Active/Inactive
(1 = enable, 0 = disable)
Pin #
-
PWD
0
0
0
0
0
0
0
0
1
45
46
2
PWD
0
1
1
1
0
X
X
1
Description
(Reserved)
IOAPIC2
IOAPIC1
IOAPIC0
(Reserved)
FS0#
FS1#
REF (X2)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
6
ICS9248-72
Preliminary Product Preview
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP#
are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in
the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the
LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
7
ICS9248-72
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Group Offset
Group
CPU to 3V66
3V66 to PCI
CPU to IOAPIC
Offset
0.0-1.5ns CPU leads
1.5-4.0ns 3V66 leads
1.5-4.0ns CPU leads
Measurement Loads
CPU @ 20pF, 3V66 @ 30pF
3V66 @ 30pF, PCI @ 30pF
CPU @ 20pF, IOAPIC @ 20pF
Measure Points
CPU @1.25V, 3V66 @ 1.5V
3V66 @ 1.5V, PCI @ 1.5V
CPU @1.25V, IOAPIC @ 1.5V
No te: 1 . All o ffsets are to be meas u red at ris in g edg es.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
Supply Current
Power Down
Supply Current
Input frequency
Pin Inductance
Input Capacitance1
Transition Time
Settling Time
1
1
Clk Stabilization
Delay
1
1
SYMBOL
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP
IDD3.3PD
CONDITIONS
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select
MIN
2
VSS-0.3
-5
TYP
MAX UNITS
VDD+0.3
V
0.8
V
µA
5
µA
µA
mA
µA
CL = 0 pF; With input address to Vdd or GND
Fi
Lpin
VDD = 3.3 V;
CIN
Cout
CINX
Logic Inputs
Out put pin capacitance
X1 & X2 pins
Ttrans
To 1st crossing of target Freq.
27
Ts
From 1st crossing to 1% target Freq.
TSTAB
tPZH,tPZH
tPLZ,tPZH
From VDD = 3.3 V to 1% target Freq.
output enable delay (all outputs)
output disable delay (all outputs)
Guarenteed by design, not 100% tested in production.
8
14.318
7
MHz
nH
5
6
45
pF
pF
pF
3
mS
mS
1
1
3
10
10
mS
nS
nS
ICS9248-72
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSP2B1
Rise Time
Fall Time
Duty Cycle
Skew
Jitter
1
CONDITIONS
MIN
-27
27
0.4
-27
30
VOL = 0.4 V, VOH = 2.0 V
0.4
1.6
ns
VOH = 0.4 V, VOL = 2.0 V
0.4
1.6
ns
VT = 1.25 V
45
55
ns
175
250
ps
ps
13.5
2
tr2B1
tf2B1
dt2B1
tsk2B1
tjcyc-cyc1
MAX UNITS
Ω
V
V
mA
mA
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @MIN= 1.0V , [email protected] MAX= 2.375V
VOL @MIN= 1.2V , [email protected] MAX= 0.3V
VOH2B
VOL2B
IOH2B
IOL2B
TYP
45
VT = 1.25 V
VT = 1.25 V
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - CPU/2
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSP2B1
Rise Time
Fall Time
Duty Cycle
Jitter
1
CONDITIONS
MIN
-27
27
0.4
-27
30
VOL = 0.4 V, VOH = 2.0 V
0.4
1.6
ns
VOH = 0.4 V, VOL = 2.0 V
0.4
1.6
ns
VT = 1.25 V
VT = 1.25 V
45
55
250
ns
ps
13.5
2
tr2B1
tf2B1
dt2B1
tjcyc-cyc1
MAX UNITS
Ω
V
V
mA
mA
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @MIN= 1.0V , [email protected] MAX= 2.375V
VOL @MIN= 1.2V , [email protected] MAX= 0.3V
VOH2B
VOL2B
IOH2B
IOL2B
TYP
Guarenteed by design, not 100% tested in production.
9
45
ICS9248-72
Preliminary Product Preview
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP1
1
VO = VDD*(0.5)
12
55
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN1
VOH1
VOL1
IOH1
IOL1
1
VO = VDD*(0.5)
12
IOH = -1 mA
2.4
IOL = 1 mA
[email protected] MIN = 1.0 V, [email protected] MAX = 3.135 V -33
[email protected] MIN = 1.95 V, [email protected] MAX= 0.4
30
55
0.55
-33
38
Ω
V
V
mA
mA
Rise Time
tr11
VOL = 0.4 V, VOH = 2.4 V
0.5
2.0
ns
Fall Time
1
VOH = 2.4 V, VOL = 0.4 V
0.5
2.0
ns
1
VT = 1.5 V
45
55
%
1
VT = 1.5 V
VT = 1.5 V
250
500
ps
ps
Output Impedance
Duty Cycle
Skew
Jitter
1
tf1
dt1
tsk1
tjcyc-cyc
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP1
1
VO = VDD*(0.5)
12
55
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN1
VOH1
VOL1
IOH1
IOL1
1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
[email protected] MIN = 1.0 V, [email protected] MAX = 3.135 V
[email protected] MIN = 1.95 V, [email protected] MAX= 0.4
12
2.4
55
-29
29
0.55
-23
27
Ω
V
V
mA
mA
Rise Time
tr11
VOL = 0.4 V, VOH = 2.4 V
0.5
2
ns
Fall Time
1
VOH = 2.4 V, VOL = 0.4 V
0.5
2
ns
1
VT = 1.5 V
45
55
%
1
VT = 1.5 V
VT = 1.5 V
500
500
ps
ps
Output Impedance
Duty Cycle
Skew
Jitter
1
tf1
dt1
tsk1
tjcyc-cyc
Guarenteed by design, not 100% tested in production.
10
ICS9248-72
Preliminary Product Preview
Electrical Characteristics - 48M, REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP5
1
VO = VDD*(0.5)
20
60
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN5
VOH5
VOL5
IOH5
IOL5
1
VO = VDD*(0.5)
IOH = 1 mA
IOL = -1 mA
VOH @MIN=1 V, [email protected]= 3.135 V
[email protected]=1.95 V, [email protected]=0.4 V
20
2.4
60
-29
29
0.4
-23
27
Ω
V
V
mA
mA
Duty Cycle
dt51
VT = 1.5 V
45
55
%
Jitter
tjcyc-cyc1
tjcyc-cyc1
VT = 1.5 V; Fixed Clocks
500
ps
VT = 1.5 V; Ref Clocks
VT = 1.5 V,Fixed Clocks
1000
N/A
ps
ps
Output Impedance
Skew
1
Tsk
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 40 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
RDSP2B1
VOH2B
VOL2B
IOH2B
IOL2B
Rise Time
tr2B1
VOL = 0.4 V, VOH = 2.0 V
0.4
1.6
ns
Fall Time
VOH = 0.4 V, VOL = 2.0 V
0.4
1.6
ns
VT = 1.25 V
45
55
ns
Skew
tf2B1
dt2B1
tsk2B1
Jitter
tjcyc-cyc1
Duty Cycle
1
CONDITIONS
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @MIN= 1.0V , [email protected] MAX= 2.375V
VOL @MIN= 1.2V , [email protected] MAX= 0.3V
VT = 1.25 V
VT = 1.25 V
Guarenteed by design, not 100% tested in production.
11
MIN
13.5
2
-27
27
TYP
MAX UNITS
45
Ω
V
0.4
V
-27
mA
30
mA
250
ps
500
ps
ICS9248-72
Preliminary Product Preview
SYMBOL
A
A1
A2
B
C
D
E
e
H
h
L
N
∝
X
COMMON DIMENSIONS
MIN.
NOM.
MAX.
.095
.101
.110
.008
.012
.016
.088
.090
.092
.008
.010
.0135
.005
.010
See Variations
.292
.296
.299
0.025 BSC
.400
.406
.410
.010
.013
.016
.024
.032
.040
See Variations
0°
5°
8°
.085
.093
.100
VARIATIONS
MIN.
.620
AC
D
NOM.
.625
N
MAX.
.630
48
48 Pin SSOP Package
Ordering Information
ICS9248yF-72
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
12
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.