ICS ICS9250-29

Integrated
Circuit
Systems, Inc.
ICS9250-29
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Pin Configuration
Output Features:
•
2 CPU (2.5V) (up to 133MHz achievable through I2C)
•
13 SDRAM (3.3V) (up to 133MHz achievable
through I2C)
•
5 PCI (3.3 V) @33.3MHz
•
1 IOAPIC (2.5V) @ 33.3 MHz
•
3 Hublink clocks (3.3 V) @ 66.6 MHz
•
2 (3.3V) @ 48 MHz (Non spread spectrum)
•
1 REF (3.3V) @ 14.318 MHz
Features:
•
Supports spread spectrum modulation,
0 to -0.5% down spread.
•
I2C support for power management
•
Efficient power management scheme through PD#
•
Uses external 14.138 MHz crystal
•
Alternate frequency selections available through I2C
control.
IOAPIC
VDDL
GNDL
*FS1/REF
VDDR
X1
X2
GNDR
VDD3
3V66-0
3V66-1
3V66-2
GND3
PCICLK0
PCICLK1
PCICLK2
VDD2
GND2
PCICLK3
PCICLK4
FS0
GNDA
VDDA
SCLK
SDATA
GNDF
VDDF
48MHz_0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ICS9250-29
Recommended Application:
Solano type chipset.
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GNDL
VDDL
CPUCLK0
CPUCLK1
GND1
SDRAM0
SDRAM1
VDD1
GND1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDD1
GND1
SDRAM6
SDRAM7
SDRAM8
SDRAM9
VDD1
GND1
SDRAM10
SDRAM11
VDD1
GND1
SDRAM12
TRISTATE#/PD#**
48MHz_1
56-Pin 300mil SSOP
* This input has a 50KW pull-down to GND.
** This input has a 50KW pull-up to VDD
Functionality
Block Diagram
X1
X2
XTAL
OSC
REF
PLL1
Spread
Spectrum
/2
/3
VDDL
2
FS(1:0)
PD#
3
Control
Logic
TRISTATE#
Config
Reg
SDATA
13
/2
5
PLL2
3V66 [2:0]
2
FS0
FS1
0
0
1
1
1
1
0
1
0
1
0
1
X
X
0
0
1
1
CPU
MHz
Tristate
Test
66MHz
100MHz
133MHz
133MHz
SDRAM
MHz
Tristate
Test
100MHz
100MHz
133MHz
100MHz
SDRAM [12:0]
PCICLK [4:0]
IOAPIC
VDDL
/2
SCLK
CPU66/100/133 [1:0]
Tristate#
48MHz [1:0]
9250-29 Rev A 02/01/01
Third party brands and names are the property of their respective owners.
Power Groups
VDDA, GNDA = CPU, PLL (analog)
VDDF, GNDF = Fixed PLL, 48M (analog/digital)
VDDR, GNDR = REF, X1, X2 (analog/digital)
VDD3, GND3 = 3V66 (digital)
VDD2, GND2 = PCI (digital)
VDD1, GND1 = SDRAM (digital)
VDDL, GNDL = IOAPIC, CPU (digital)
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
ICS9250-29
General Description
The ICS9250-29 is a single chip clock solution for Solano type chipset. It provides all necessary clock signals for such
a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-29
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Pin Configuration
PIN NUMBER
P I N NA M E
TYPE
DESCRIPTION
1
IOAPIC
OUT
2.5V clock output running at 33.3MHz.
2, 55
VDDL
PWR
2.5V power supply for CPU & IOAPIC
3, 56
GNDL
PWR
Ground for 2.5V power supply for CPU & IOAPIC
4
5, 9, 17, 23, 27,
33, 37, 43, 49
FS1
IN
REF
OUT
3.3V, 14.318MHz reference clock output.
VDDx
PWR
3.3V power supply
6
X1
IN
7
X2
OUT
8, 13, 18, 22, 26,
GNDx
32, 36, 42, 48, 52
12, 11, 10
21
3V66 (2:0)
FS0
20, 19, 16, 15, 14 PCICLK (4:0)
Function Select pin. Determines CPU frequency, all output functionality
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
PWR
Ground pins for 3.3V supply
OUT
3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B
IN
OUT
Function Select pin. Determines CPU frequency, all output functionality.
3.3V PCI clock outputs
At power up the TRISTATE#/PD# pin defaults to the TRISTATE#
input function to enable the TRISTATE# and TEST modes. (see Shared
Pin Operation for full description).
Asynchronous active low input pin used to power down the device into
a low power state. The internal clocks are disabled and the VCO and
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
TRISTATE#
IN
PD#
IN
24
SCLK
IN
Clock input of I2C input
25
SDATA
IN
Data input for I2C serial input.
30
29, 28
48MHz (1:0)
31, 34, 35, 38,
SDRAM
39, 40, 41, 44, [12:0]
45, 46, 47, 50, 51
53, 54
CPUCLK (1:0)
OUT
3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t s .
OUT
3.3V output running 100MHz and 133MHz. All SDRAM outputs can
be turned off through I2C
OUT
2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending
on FS pins.
2
ICS9250-29
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the
output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Maximum Allowed Current
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 2.625V
All static inputs = Vddq3 or GND
Solano
Condition
Max 3.3V supply consumption
Max discrete cap loads,
Vddq3 = 3.465V
All static inputs = Vddq3 or GND
Powerdown Mode
(PWRDWN# = 0)
2mA
2mA
Full Active 66MHz
FS(1:0) = 00
35mA
440mA
Full Active 100MHz
FS(1:0) = 01
50mA
430mA
Full Active 133MHz
FS(1:0) = 11
60mA
440mA
Full Active 133MHz
FS(1:0) = 10
60mA
500mA
Clock Enable Configuration
PD#
CPUCLK
SDRAM
IOAPIC
3V66
PCICLK
REF,
48MHz
Osc
VCOs
0
LOW
LOW
LOW
LOW
LOW
LOW
OFF
OFF
1
ON
ON
ON
ON
ON
ON
ON
ON
3
ICS9250-29
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0) through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
Note: This clock does not support Read Back. Doing a
read back will lock up the PIIX-4 system.
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I2C (SMB) component. It is only a "write" mode SMB device, no readback on
this part. Read-Back will lock up the PIIX-4 due to the Byte count of 00H.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The
data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
4
ICS9250-29
Truth Table
Tristate
FS0
FS1
CPU
SDRAM
3V66
PCI
48MHz
REF
IOAPIC
0
0
X
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
0
1
X
TCLK/2
TCLK/2
TCLK/3
TCLK/6
TCLK/2
TCLK
TCLK/6
1
0
0
66.6 MHz
100 MHz
66.6 MHz
33.3 MHz
48 MHz
14.318 MHz
33.3 MHz
1
1
0
100 MHz
100 MHz
66.6 MHz
33.3 MHz
48 MHz
14.318 MHz
33.3 MHz
1
0
1
133 MHz
133 MHz
66.6 MHz
33.3 MHz
48 MHz
14.318 MHz
33.3 MHz
1
1
1
133 MHz
100 MHz
66.6 MHz
33.3 MHz
48 MHz
14.318 MHz
33.3 MHz
Byte 0: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
29
28
-
Name
(Reserved ID)
(Reserved ID)
(Reserved ID)
(Reserved ID)
Spread Spectrum
48MHz_1
48MHz_0
(Reserved ID)
PWD
0
0
0
1
0
1
1
0
Description
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(1=On / 0=Off )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
PWD
1
1
1
1
1
1
1
1
Description
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
Note:
Reserved ID bits must be written with "0"
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
40
41
44
45
46
47
50
51
Name
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
5
ICS9250-29
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
12
31
34
35
38
39
15
-
Name
3V66_2 (AGP)
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
PCICLK1
Undefined bit
PWD
1
1
1
1
1
1
1
0
Description
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
3. Undefined bits can be written with either "1" or "0"
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Bit
Description
PWD
Bit 7
ICS Reserved bit (Note 2)
0
Bit 6
ICS Reserved bit (Note 2)
0
Bit 5
ICS Reserved bit (Note 2)
0
Bit 4
ICS Reserved bit (Note 2)
0
Bit 3
5% overclock mode (1 = 5% / 0= normal )
0
Bit 2
Undefined bit (note 3)
1
Bit 1
Tristate#/PWRDN# ( 1 = PWRDN# / 0 = Tristate# ) see pin description
1
Bit 0
CPUCLK SDRAM
MHz
MHz
3V66
MHz
PCICLK IOAPIC
MHz
MHz
Bit 0
FS1
FS0
0
0
0
66.66
100.0
66.66
33.33
33.33
0
0
1
100.0
100.0
66.66
33.33
33.33
0
1
0
133.32
133.32
66.66
33.33
33.33
0
1
1
133.32
100.0
66.66
33.33
33.33
1
0
0
66.66
100.0
66.66
33.33
33.33
1
0
1
100.0
100.0
66.66
33.33
33.33
1
1
0
133.32
133.32
66.66
33.33
33.33
1
1
1
133.32
133.32
66.66
33.33
33.33
0
Note 1
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS1 for the appropriate CPU speed, always with
SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the default 0 to 1
to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the CPU is at the
133MHz FSB speed as shown in this table. The CPU, 3V66, PCI and IOAPIC clocks will be glitch free during this
transition, and only SDRAM will change.
Note 2: Must be written with "0"
Note 3: Undefined bits can be written with either "1" or "0"
6
ICS9250-29
Byte 4: Reserved Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
20
19
16
Name
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
PCICLK4
PCICLK3
PCICLK2
PWD
0
0
0
0
0
1
1
1
Description
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
PWD
0
0
0
0
0
0
0
0
Description
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
Byte 5: Reserved Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
Name
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
7
ICS9250-29
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Group Timing Relationship Table1
Group
CPU 66MHz
SDRAM 100MHz
CPU 100MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 133MHz
Offset
Tolerance
Offset
Tolerance
Offset
Tolerance
Offset
Tolerance
CPU to SDRAM
CPU to 3V66
-2.5ns
7.5ns
500ps
500ps
5.0ns
5.0ns
500ps
500ps
0.0ns
0.0ns
500ps
500ps
3.75ns
0.0ns
500ps
500ps
SDRAM to 3V66
0.0ns
500ps
0.0ns
500ps
0.0ns
500ps
-3.75ns
500ps
3V66 to PCI
1.5-3.5ns
500ps
1.5-3.5ns
500ps
1.5-3.5ns
500ps
1.5 -3.5ns
500ps
PCI to IOAPIC
USB & DOT
0.0ns
Asynch
1ns
N/A
0.0ns
Asynch
1ns
N/A
0.0ns
Asynch
1ns
N/A
0.0ns
Asynch
1ns
N/A
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
Supply Current
Power Down
Supply Current
Input frequency
Pin Inductance1
Input Capacitance1
Transition Time
Settling Time
1
1
Clk Stabilization 1
Delay 1
1
SYMBOL
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP
IDD3.3PD
Fi
CONDITIONS
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66M
MIN
2
VSS-0.3
-5
-5
-200
TYP
CL = 0 pF; With input address to Vdd or GND
VDD = 3.3 V;
Lpin
CIN
Cout
CINX
Logic Inputs
Out put pin capacitance
X1 & X2 pins
Ttrans
MAX UNITS
VDD+0.3
V
0.8
V
5
µA
µA
µA
100
mA
600
µA
14.318
MHz
7
5
6
22.5
nH
pF
pF
pF
To 1st crossing of target Freq.
3
ms
Ts
From 1st crossing to 1% target Freq.
3
ms
TSTAB
t PZH,t PZH
t PLZ,t PZH
From VDD = 3.3 V to 1% target Freq.
output enable delay (all outputs)
output disable delay (all outputs)
3
10
10
ms
ms
ms
13.5
Guarenteed by design, not 100% tested in production.
8
1
1
ICS9250-29
Electrical Characteristics - CPU
TA = 0 - 70C, VDD=3,3V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Impedance
RDSP2B1
RDSN2B1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
1
VOH2B
VOL2B
IOH2B
IOL2B
CONDITIONS
MIN
TYP
MAX UNITS
VO = VDD*(0.5)
13.5
45
Ω
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @MIN= 1.0V , [email protected] MAX= 2.375V
VOL @MIN= 1.2V , [email protected] MAX= 0.3V
13.5
2
45
0.4
-27
30
Ω
V
V
mA
mA
-27
27
Rise Time
tr2B1
VOL = 0.4 V, VOH = 2.0 V
0.4
1.10
1.6
ns
Fall Time
tf2B1
VOH = 2.0 V, VOL = 0.4 V
0.4
1.26
1.6
ns
Duty Cycle
VT = 1.25 V
45
53.6
55
%
Skew
dt2B1
tsk2B1
175
ps
Jitter
tjcyc-cyc1
250
ps
VT = 1.25 V
VT = 1.25 V
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%;CL = 10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP1
1
VO = VDD*(0.5)
12
55
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN1
VOH1
VOL1
IOH1
IOL1
1
VO = VDD*(0.5)
12
IOH = -1 mA
2.4
IOL = 1 mA
[email protected] MIN = 1.0 V, [email protected] MAX = 3.135 V -33
[email protected] MIN = 1.95 V, [email protected] MAX= 0.4V
30
55
0.4
-33
38
Ω
V
V
mA
mA
Rise Time
tr11
VOL = 0.4 V, VOH = 2.4 V
0.5
1.46
2
ns
Fall Time
1
VOH = 2.4 V, VOL = 0.4 V
0.5
1.47
2
ns
1
VT = 1.5 V
45
50.2
55
%
1
VT = 1.5 V
VT = 1.5 V
175
ps
500
ps
Output Impedance
Duty Cycle
1
tf1
dt1
Skew
tsk1
Jitter
tjcyc-cyc1
Guarenteed by design, not 100% tested in production.
9
ICS9250-29
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Impedance
RDSP4B1
RDSN4B1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
1
VOH4B
VOL4B
IOH4B
IOL4B
CONDITIONS
MIN
TYP
MAX UNITS
VO = VDD*(0.5)
9
30
Ω
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
[email protected] min = 1.0 V, [email protected] MAX = 2.375 V
[email protected] MIN = 1.2 V, [email protected] MAX= 0.3V
9
2
30
-27
27
0.4
-27
30
Ω
V
V
mA
mA
Rise Time
tr4B1
VOL = 0.4 V, VOH = 2.0 V
0.4
1.09
1.6
ns
Fall Time
VOH = 2.0 V, VOL = 0.4 V
0.4
1.22
1.6
ns
Duty Cycle
tf4B1
dt4B1
50.2
55
%
Jitter
VT = 1.25 V
VT = 1.25 V
45
tjcyc-cyc1
500
ps
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%, CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP3
1
VO = VDD*(0.5)
10
24
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN3
VOH3
VOL3
IOH3
IOL3
1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @MIN= 2.0 V, [email protected] MAX=3.135 V
[email protected] MIN= 1.0 V, [email protected] MAX=0.4 V
10
2.4
24
-54
49
0.4
-46
53
Ω
V
V
mA
mA
Rise Time
tr31
VOL = 0.4 V, VOH = 2.4 V
0.4
1.19
1.6
ns
Fall Time
tf3
1
VOH = 2.4 V, VOL = 0.4 V
0.4
1.43
1.6
ns
Duty Cycle
dt31
VT = 1.5 V
45
54.9
55
%
250
ps
250
ps
Output Impedance
Skew
Jitter
1
VT = 1.5 V
tsk31
1
tj cyc-cyc VT = 1.5 V
Guarenteed by design, not 100% tested in production.
10
ICS9250-29
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP1
1
VO = VDD*(0.5)
12
55
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN1
VOH1
VOL1
IOH1
IOL1
1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
[email protected] MIN = 1.0 V, [email protected] MAX = 3.135 V
[email protected] MIN = 1.95 V, [email protected] MAX= 0.4
12
2.4
55
-33
30
0.4
-33
38
Ω
V
V
mA
mA
Rise Time
tr11
VOL = 0.4 V, VOH = 2.4 V
0.5
1.43
2
ns
Fall Time
1
VOH = 2.4 V, VOL = 0.4 V
0.5
1.63
2
ns
1
VT = 1.5 V
45
51.9
55
%
1
VT = 1.5 V
VT = 1.5 V
500
ps
500
ps
Output Impedance
Duty Cycle
1
tf1
dt1
Skew
tsk1
Jitter
tjcyc-cyc1
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%, CL = 10 -20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP5
1
VO = VDD*(0.5)
20
60
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN5
VOH5
VOL5
IOH5
IOL5
1
VO = VDD*(0.5)
IOH = 1 mA
IOL = -1 mA
VOH @MIN=1 V, [email protected]= 3.135 V
[email protected]=1.95 V, [email protected]=0.4 V
20
2.4
60
0.4
-23
27
Ω
V
V
mA
mA
Rise Time
tr51
VOL = 0.4 V, VOH = 2.4 V
1
1.53
4
ns
Fall Time
1
VOH = 2.4 V, VOL = 0.4 V
1
1.76
4
ns
1
VT = 1.5 V
45
53.6
55
%
500
ps
1000
ps
Output Impedance
1
tf5
Duty Cycle
dt5
Jitter
tjcyc-cyc1
tjcyc-cyc1
VT = 1.5 V; Fixed Clocks
VT = 1.5 V; Ref Clocks
Guarenteed by design, not 100% tested in production.
11
-29
29
ICS9250-29
Electrical Characteristics - 48MHz_1
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 15 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP3
1
VO = VDD*(0.5)
10
24
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN3
VOH3
VOL3
IOH3
IOL3
1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @MIN= 2.0 V, [email protected] MAX=3.135 V
[email protected] MIN= 1.0 V, [email protected] MAX=0.4 V
10
2.4
24
-33
30
0.4
-33
38
Ω
V
V
mA
mA
Rise Time
tr31
VOL = 0.4 V, VOH = 2.4 V
0.5
0.81
2.0
ns
Fall Time
1
VOH = 2.4 V, VOL = 0.4 V
0.5
0.95
2.0
ns
45
53.1
55
%
500
ps
Output Impedance
Duty Cycle
Jitter
1
tf3
dt31
VT = 1.5 V
tjcyc-cyc1 VT = 1.5 V
Guarenteed by design, not 100% tested in production.
12
ICS9250-29
0ns
10ns
20ns
30ns
Cycle Repeats
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 100MHz
SDRAM 133MHz
3.3V 66MHz
PCI 33MHz
IOAPIC 33MHz
REF 14.318MHz
USB 48MHz
Group Offset Waveforms
13
40ns
ICS9250-29
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS9250-29
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage) that
is present on these pins at this time is read and stored into a 5bit internal data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In this
mode the pins produce the specified buffered clocks to external
loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K Via to Gnd
Device
Pad
8.2K Clock trace to load
Series Term. Res.
Fig. 1
TRISTATE#/PD# pin description:
The TRISTATE#/PD# pin provides the capability of invoking
Tristate mode during board level testing.
At power up the TRISTATE#/PD# pin defaults to the
TRISTATE# input function to enable the TRESTATE# and
TEST modes.
Approximately 1.5ms to 3ms after power on, the TRISTATE#/
PD# changes to the PD# input function and the TRISTATE#
functionality is disabled (if TRISTATE# is not active).
14
ICS9250-29
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
2.413
2.794
.095
.110
A1
0.203
0.406
.008
.016
b
0.203
0.343
.008
.0135
c
D
0.127
0.254
SEE VARIATIONS
.005
.010
SEE VARIATIONS
E
10.033
10.668
.395
.420
E1
7.391
7.595
.291
.299
e
0.635 BASIC
h
0.381
L
0.508
1.016
SEE VARIATIONS
N
α
0.635
0°
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
8°
0°
8°
MIN
MAX
MIN
MAX
18.288
18.542
.720
.730
JEDEC MO-118
DOC# 10-0034
6/1/00
REV B
VARIATIONS
D mm.
N
56
D (inch)
Ordering Information
ICS9250yF-29-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
15
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.