Integrated Circuit Systems, Inc. ICS9250-28 Frequency Generator & Integrated Buffers for Celeron & PII/III™ Pin Configuration IOAPIC VDDL GND *FS1/REF0 VDDREF X1 X2 GND VDD3V66 3V66_0 3V66_1 3V66_2 GND VDDPCI PCICLK0 PCICLK1 GND FS0 GND VDDA PD# SCLK SDATA GND VDD48 48MHz_0 48MHz_1 FS2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ICS9250-28 Recommended Application: 810/810E and 815 type chipset. Output Features: • 2 CPU (2.5V) (up to 133MHz achievable through I2C) • 13 SDRAM (3.3V) (up to 133MHz achievable through I2C) • 2 PCI (3.3 V) @33.3MHz • 1 IOAPIC (2.5V) @ 33.3 MHz • 3 Hublink clocks (3.3 V) @ 66.6 MHz • 2 (3.3V) @ 48 MHz (Non spread spectrum) • 1 REF (3.3V) @ 14.318 MHz Features: • Supports spread spectrum modulation, 0 to -0.5% down spread. • I2C support for power management • Efficient power management scheme through PD# • Uses external 14.138 MHz crystal • Alternate frequency selections available through I2C control. 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDL GND CPUCLK0 CPUCLK1 GND SDRAM0 SDRAM1 VDDSDR GND SDRAM2 SDRAM3 SDRAM4 VDDSDR GND SDRAM5 SDRAM6 VDDSDR GND SDRAM7 SDRAM8 SDRAM9 VDDSDR GND SDRAM10 SDRAM11 VDDSDR GND SDRAM12 56-Pin 300mil SSOP * This input has a 50KW pull-down to GND. Functionality Block Diagram X1 X2 XTAL OSC /2 FS1 0 0 0 1 X X 1 0 0 1 1 0 1 0 1 1 1 1 /3 2 PD# FS0 REF0 PLL1 Spread Spectrum FS(2:0) FS2 3 Control Logic Config Reg SDATA 13 /2 2 /2 SCLK PLL2 CPU66/100/133 [1:0] 3V66 (2:0) SDRAM (12:0) Function Tristate Test Active CPU = 66MHz SDRAM = 100MHz Active CPU = 100MHz SDRAM = 100MHz Active CPU = 133MHz SDRAM = 133MHz Active CPU = 133MHz SDRAM = 100MHz PCICLK (1:0) IOAPIC 48MHz (1:0) 2 9250-28 Rev B 10/26/00 Third party brands and names are the property of their respective owners. Power Groups Analog VDDREF = X1, X2 VDDA = PLL1 VDD48 = PLL2 Digital VDD3V66, VDDPCI VDDSDR, VDDL ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9250-28 General Description The ICS9250-28 is part of a two chip clock solution for 810/810E and 815 type chipset. Combined with the ICS9112-17, the ICS9250-28 provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-28 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Pin Configuration PIN NUMBER P I N NA M E TYPE DESCRIPTION 1 IOAPIC OUT 2.5V clock output running at 33.3MHz. 2, 56 VDDL PWR 2.5V power supply for CPU & IOAPIC 4 FS1 REF0 5, 9, 14, 20, 25, VDD 31, 35, 40, 44, 49 IN Function Select pin. Determines CPU frequency, all output functionality OUT 3.3V, 14.318MHz reference clock output. PWR 3.3V power supply Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) 6 X1 IN 7 X2 OUT GND PWR Ground pins for 3.3V supply 3V66 (2:0) OUT 3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B 3, 8, 13, 17, 19, 24, 30, 34, 39, 43, 48, 52, 55 12, 11, 10 28, 18 FS (2, 0) 16, 15 PCICLK[1:0] IN OUT Function Select pins. Determines CPU frequency, all output functionality. Please refer to Functionality table on page 3. 3.3V PCI clock outputs 21 PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 22 SCLK IN Clock pin of I2C circuitry 5V tolerant 23 SDATA I/O Data pin for I2C circuitry 5V tolerant 26, 27 48MHz_0 29, 32, 33, 36, AM 37, 38, 41, 42, (S1D2R :0) 45, 46, 47, 50, 51 54, 53 CPUCLK (1:0) OUT 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t s . OUT 3.3V output running 100MHz. All SDRAM outputs can be turned off t h r o u g h I 2C OUT 2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending on FS (2:0) pins. 2 ICS9250-28 Power Down Waveform Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz Maximum Allowed Current Max 2.5V supply consumption Max discrete cap loads, Vddq2 = 2.625V All static inputs = Vddq3 or GND 815 Condition Max 2.5V supply consumption Max discrete cap loads, Vddq2 = 3.465V All static inputs = Vddq3 or GND Powerdown Mode (PWRDWN# = 0 10mA 10mA Full Active 66MHz FS[2:0] = 010 70mA 400mA Full Active 100MHz FS[2:0] = 011 100mA 400mA Full Active 133MHz FS[2:0] = 111 130mA 450mA Clock Enable Configuration PD# CPUCLK SDRAM IOAPIC 66MHz PCICLK REF, 48MHz Osc VCOs 0 LOW LOW LOW LOW LOW LOW OFF OFF 1 ON ON ON ON ON ON ON ON 3 ICS9250-28 Truth Table FS2 FS0 FS1 CPU SDRAM 3V66 PCI 48MHz REF IOAPIC 0 0 X Tristate Tristate Tristate Tristate Tristate Tristate Tristate 0 1 X TCLK/2 TCLK/2 TCLK/3 TCLK/6 TCLK/2 TCLK TCLK/6 1 0 0 66.6 MHz 100 MHz 66.6 MHz 33.3 MHz 48 MHz 14.318 MHz 33.3 MHz 1 1 0 100 MHz 100 MHz 66.6 MHz 33.3 MHz 48 MHz 14.318 MHz 33.3 MHz 1 0 1 133 MHz 133 MHz 66.6 MHz 33.3 MHz 48 MHz 14.318 MHz 33.3 MHz 1 1 1 133 MHz 100 MHz 66.6 MHz 33.3 MHz 48 MHz 14.318 MHz 33.3 MHz Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD) Bit Desctiption PWD Bit7 ICS Reserved bit (Note 2) 0 Bit6 ICS Reserved bit (Note 2) 0 Bit5 ICS Reserved bit (Note 2) 0 Bit4 ICS Reserved bit (Note 2) 0 Bit3 ICS Reserved bit (Note 2) 0 Bit2 Undefined bit (Note 3) X Bit1 Undefined bit (Note 3) Bit 0 Bit 0 FS0 X FS1 CPUCLK SDRAM MHz MHz 3V66 MHz PCICLK IOAPIC MHz MHz 0 0 0 66.66 100.0 66.66 33.33 33.33 0 1 0 100.0 100.0 66.66 33.33 33.33 0 0 1 133.32 133.32 66.66 33.33 33.33 0 1 1 133.32 100.0 66.66 33.33 33.33 1 0 0 66.66 100.0 66.66 33.33 33.33 1 1 0 100.0 100.0 66.66 33.33 33.33 1 0 1 133.32 133.32 66.66 33.33 33.33 1 1 1 133.32 133.32 66.66 33.33 33.33 0 Note 1 Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always with SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the default 0 to 1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the CPU is at the 133MHz FSB speed as shown in this table. The CPU, 3V66, PCI, and IOAPIC clocks will be glitch free during this transition, and only SDRAM will change. Note 2: "ICS RESERVED BITS" must be writtern as "0". Note3: Undefined bits can be written either as "1 or 0" 4 ICS9250-28 Byte 0: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Pin# - Name PWD Reserved ID 0 Reserved ID 0 Reserved ID 0 Reserved ID 1 SpreadSpectrum Bit 3 1 (1=On/0=Off) Bit 2 27 48MHz 1 1 Bit 1 26 48MHz 0 1 Bit 0 Reserved ID 0 Note: Reserved ID bits must be written as "0" Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Byte 1: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 38 41 42 45 46 47 50 51 Name SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 PWD 1 1 1 1 1 1 1 1 Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) PWD 1 1 1 1 1 1 1 0 Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Byte 2: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 12 29 32 33 36 37 16 - Name 3V66-2 (AGP) SDRAM12 SDRAM11 SDRAM10 SDRAM9 SDRAM8 PCICLK1 Reserved Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default 3. Undefined bit can be wirtten with either a "1" or "0". 5 ICS9250-28 Byte 4: Reserved Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# - Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PWD 0 0 0 0 0 0 0 0 Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default Group Timing Relationship Table1 Group CPU 66MHz SDRAM 100MHz CPU 100MHz SDRAM 100MHz CPU 133MHz SDRAM 100MHz CPU 133MHz SDRAM 133MHz Offset Tolerance Offset Tolerance Offset Tolerance Offset Tolerance CPU to SDRAM -2.5ns 500ps 5.0ns 500ps 0.0ns 500ps 3.75ns 500ps CPU to 3V66 7.5ns 500ps 5.0ns 500ps 0.0ns 500ps 0.0ns 500ps SDRAM to 3V66 0.0ns 500ps 0.0ns 500ps 0.0ns 500ps -3.75ns 500ps 3V66 to PCI 1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5 -3.5ns 500ps PCI to PCI USB & DOT 0.0ns Asynch 500ps N/A 0.0ns Asynch 500ps N/A 500ps Asynch 1.0ns N/A 0.0ns Asynch 500ps N/A 6 ICS9250-28 Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V DD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C Maximum Case Operating Temperature . . . . . . +135°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP Input High Voltage VIH 2 VSS-0.3 Input Low Voltage VIL VIN = VDD -5 Input High Current IIH IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 Input Low Current VIN = 0 V; Inputs with pull-up resistors IIL2 -200 138 CL = 0 pF; @ 66/100 MHz CL = 0 pF; @ 100/100 MHz 126 172 CL = 0 pF; @ 133/133 MHz 141 CL = 0 pF; @ 133/100 MHz IDD3.3OP 339 CL = Max loads; @ 66/100 MHz 328 CL = Max loads; @ 100/100 MHz 383 CL = Max loads; @ 133/133 MHz Transition time 1 1 Settling time Clk Stabilization1 Delay1 1 µA 200 200 200 200 400 400 450 mA mA 340 9 11 13 13 13 23 400 15 18 20 20 35 60 CL = Max loads; @ 133/133 MHz 29 60 IDD3.3PD IDD.25PD Fi CL = Max loads; @ 133/100 MHz CL = Max loads Input address VDD or GND VDD = 3.3 V 30 251 <1 14.318 60 400 10 16 MHz Ttrans To 1st crossing of target frequency 3 ms From 1st crossing to 1% target frequency 3 ms TSTAB From VDD = 3.3 V to 1% target frequency tPZH,tPZL Output enable delay (all outputs) tPHZ,tPLZ Output disable delay (all outputs) 3 10 10 ms ns ns IDD2.5OP Input Frequency UNITS V V µA CL = Max loads; @ 133/100 MHz CL = 0 pF; @ 66/100 MHz CL = 0 pF; @ 100/100 MHz CL = 0 pF; @ 133/133 MHz CL = 0 pF; @ 133/100 MHz CL = Max loads; @ 66/100 MHz CL = Max loads; @ 100/100 MHz Operating Supply Current Powerdown Current MAX VDD+0.3 0.8 5 Ts Guaranteed by design, not 100% tested in production. 7 12 1 1 mA mA µA ICS9250-28 Electrical Characteristics - CPU TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP2B VO = VDD*(0.5) VO = VDD*(0.5) Output Impedance RDSN2B1 IOH = -1 mA Output High Voltage VOH2B IOL = 1 mA Output Low Voltage VOL2B VOH @ MIN = 1.0 V IOH2B Output High Current VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V IOL2B Output Low Current VOL @ MAX = 0.3 V Rise Time1 Fall Time 1 1 Duty Cycle Skew window1 Jitter, Cycle-to-cycle1 1 MIN 13.5 13.5 2 TYP 16 21 -27 -68 -9 54 11 27 MAX UNITS 45 Ω 45 Ω V 0.4 V -27 30 mA mA tr2B VOL = 0.4 V, VOH = 2.0 V 0.4 1.1 1.6 ns tf2B dt2B VOH = 2.0 V, VOL = 0.4 V 0.4 1.1 1.6 ns VT = 1.25 V 45 49 55 % tsk2B VT = 1.25 V 45 175 ps tjcyc-cyc2B VT = 1.25 V 135 250 ps Guaranteed by design, not 100% tested in production. Electrical Characteristics - 3V66 TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance RDSP1B1 VO = VDD*(0.5) VO = VDD*(0.5) Output Impedance RDSN1B1 IOH = -1 mA Output High Voltage VOH1 IOL = 1 mA Output Low Voltage VOL1 VOH @ MIN = 1.0 V IOH1 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL1 Output Low Current VOL @ MAX = 0.4 V TYP 14 14.5 -33 -108 -9 95 29 30 MAX UNITS 55 Ω 55 Ω V 0.55 V -33 38 mA mA Rise Time1 tr1 VOL = 0.4 V, VOH = 2.4 V 0.4 1.2 1.6 ns Fall Time1 tf1 dt1 VOH = 2.4 V, VOL = 0.4 V 0.4 1.2 1.6 ns VT = 1.5 V 45 49 55 % tsk1 VT = 1.5 V 135 175 ps tjcyc-cyc1 VT = 1.5 V 175 500 ps Duty Cycle1 Skew window1 Jitter, Cycle-to-cycle1 1 MIN 12 12 2.4 Guaranteed by design, not 100% tested in production. 8 ICS9250-28 Electrical Characteristics - IOAPIC TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP4B VO = VDD*(0.5) Output Impedance RDSN4B1 VO = VDD*(0.5) IOH = -1 mA Output High Voltage VOH4B IOL = 1 mA Output Low Voltage VOL4B VOH @ MIN = 1.0 V IOH4B Output High Current VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V IOL4B Output Low Current VOL @ MAX = 0.3 V Rise Time1 Fall Time 1 1 Duty Cycle Jitter, Cycle-to-cycle1 1 MIN 9 9 2 TYP 16 20 -27 -68 -9 54 11 27 MAX UNITS 30 Ω 30 Ω V 0.4 V -27 30 mA mA tr4B VOL = 0.4 V, VOH = 2.0 V 0.4 1.1 1.6 ns tf4B dt4B VOH = 2.0 V, VOL = 0.4 V 0.4 1.1 1.6 ns VT = 1.25 V 45 49 55 % 180 500 ps tjcyc-cyc4B VT = 1.25 V Guaranteed by design, not 100% tested in production. Electrical Characteristics - SDRAM TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance RDSP3B1 VO = VDD*(0.5) VO = VDD*(0.5) Output Impedance RDSN3B1 IOH = -1 mA Output High Voltage VOH3 IOL = 1 mA Output Low Voltage VOL3 VOH @ MIN = 2.0 V IOH3 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.0 V IOL3 Output Low Current VOL @ MAX = 0.4 V TYP 12 15 -54 -92 -16 68 29 54 MAX UNITS 24 Ω 24 Ω V 0.4 V -46 53 mA mA Rise Time1 tr3 VOL = 0.4 V, VOH = 2.4 V 0.4 1 1.6 ns Fall Time1 tf3 dt3 VOH = 2.4 V, VOL = 0.4 V 0.4 1.5 1.6 ns VT = 1.5 V 45 52 55 % tsk3 VT = 1.5 V 120 250 ps tjcyc-cyc3 VT = 1.5 V 135 250 ps Duty Cycle1 Skew window1 Jitter, Cycle-to-cycle 1 MIN 10 10 2.4 1 Guaranteed by design, not 100% tested in production. 9 ICS9250-28 Electrical Characteristics - PCI TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP1B VO = VDD*(0.5) VO = VDD*(0.5) Output Impedance RDSN1B1 IOH = -1 mA Output High Voltage VOH1 IOL = 1 mA Output Low Voltage VOL1 VOH @ MIN = 1.0 V IOH1 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL1 Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time 1 1 Duty Cycle Skew window1 Jitter, Cycle-to-cycle1 1 MIN 12 12 2.4 TYP 15 15 -33 -106 -14 94 29 30 MAX UNITS 55 Ω 55 Ω V 0.55 V -33 38 mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 0.4 1.3 2 ns tf1 dt1 VOH = 2.4 V, VOL = 0.4 V 0.4 1.4 2 ns VT = 1.5 V 45 51 55 % tsk1 VT = 1.5 V 20 500 ps tjcyc-cyc1 VT = 1.5 V 175 500 ps Guaranteed by design, not 100% tested in production. Electrical Characteristics - REF, 48MHz_0 (Pin 26) TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance RDSP5B1 VO = VDD*(0.5) Output Impedance RDSN5B1 VO = VDD*(0.5) Output High Voltage VOH15 IOH = -1 mA Output Low Voltage VOL5 IOL = 1 mA VOH @ MIN = 1.0 V IOH5 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL5 Output Low Current VOL @ MAX = 0.4 V TYP 29 27 -29 -54 -11 54 16 29 Rise Time1 tr5 VOL = 0.4 V, VOH = 2.4 V 0.4 1.3 Fall Time1 tf5 dt5 VOH = 2.4 V, VOL = 0.4 V 0.4 VT = 1.5 V 45 tjcyc-cyc5 tjcyc-cyc5 Duty Cycle1 Jitter, Cycle-to-cycle1 Jitter, Cycle-to-cycle1 1 MIN 20 20 2.4 MAX UNITS 60 Ω 60 Ω V 0.55 V -23 27 mA mA 4 ns 1.6 4 ns 53 55 % VT = 1.5 V, Fixed clocks 160 500 ps VT = 1.5 V, Ref clocks 420 1000 ps Guaranteed by design, not 100% tested in production. 10 ICS9250-28 Electrical Characteristics - 48MHz_1 (Pin 27) TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-15 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP3B VO = VDD*(0.5) Output Impedance RDSN3B1 VO = VDD*(0.5) IOH = -1 mA Output High Voltage VOH3 IOL = 1 mA Output Low Voltage VOL3 VOH @ MIN = 2.0 V IOH3 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.0 V IOL3 Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time 1 1 Duty Cycle Jitter, Cycle-to-cycle1 1 MIN 10 10 2.4 TYP 15 15 -54 -82 -20 95 28 54 MAX UNITS 24 Ω 24 Ω V 0.55 V -46 53 mA mA tr3 VOL = 0.4 V, VOH = 2.4 V 0.4 1.1 1.6 ns tf3 dt3 VOH = 2.4 V, VOL = 0.4 V 0.4 1.3 1.6 ns VT = 1.5 V 45 53 55 % 145 500 ps tjcyc-cyc3B VT = 1.5 V Guaranteed by design, not 100% tested in production. 11 ICS9250-28 Group Skews (CPU 66 MHz, SDRAM 100MHz) TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF Refer to Group Offset Waveforms diagram for definition of transition edges. PARAMETER SYMBOL CONDITIONS MIN 1 T -3 CPU to SDRAM Skew sk1 CPU-SDRAM CPU @ 1.25 V, SDRAM @ 1.5 V 1 0 Skew Window Tw1 CPU-SDRAM 1 T 7 CPU to 3V66 Skew sk1 CPU-3V66 CPU @ 1.25 V, 3V66 @ 1.5 V 1 Tw1 CPU-3V66 0 Skew Window -500 SDRAM to 3V66 Skew1 Tsk1 SDRAM-3V66 SDRAM, 3V66 @ 1.5 V 0 Skew Window1 Tw1 SDRAM-3V66 Tsk1 3V66-PCI 1.5 3V66 to PCI Skew1 3V66, PCI @ 1.5 V Tw1 3V66-PCI 0 Skew Window1 -1 IOAPIC to PCI Skew1 Tsk1 IOAPIC-PCI IOAPIC @ 1.25 V, PCI @ 1.5 V 0 Skew Window1 Tw1 IOAPIC-PCI 1 Guaranteed by design, not 100% tested in production. TYP -2.7 165 7.6 105 180 210 2.1 90 -0.1 0 MAX UNITS -2 ns 500 ps 8 ns 500 ps 500 ps 500 ps 3.5 ns 500 ps 1 ns 1 ns TYP 4.9 180 5 100 175 200 2.1 90 -0.1 0 MAX UNITS 5.5 ns 500 ps 5.5 ns 500 ps 500 ps 500 ps 3.5 ns 500 ps 1 ns 1 ns Group Skews (CPU 100 MHz, SDRAM 100MHz) TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF Refer to Group Offset Waveforms diagram for definition of transition edges. PARAMETER SYMBOL CONDITIONS MIN 4.5 CPU to SDRAM Skew1 Tsk2 CPU-SDRAM CPU @ 1.25 V, SDRAM @ 1.5 V 1 T 0 Skew Window w2 CPU-SDRAM Tsk2 CPU-3V66 4.5 CPU to 3V66 Skew1 CPU @ 1.25 V, 3V66 @ 1.5 V Tw2 CPU-3V66 0 Skew Window1 1 -500 SDRAM to 3V66 Skew Tsk2 SDRAM-3V66 SDRAM, 3V66 @ 1.5 V 1 T 0 Skew Window w2 SDRAM-3V66 1 Tsk2 3V66-PCI 1.5 3V66 to PCI Skew 3V66, PCI @ 1.5 V 1 T 0 Skew Window w2 3V66-PCI 1 Tsk2 IOAPIC-PCI -1 IOAPIC to PCI Skew IOAPIC @ 1.25 V, PCI @ 1.5 V 1 T 0 Skew Window w2 IOAPIC-PCI 1 Guaranteed by design, not 100% tested in production. 12 ICS9250-28 Group Skews (CPU 133 MHz, SDRAM 133MHz) TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF Refer to Group Offset Waveforms diagram for definition of transition edges. PARAMETER SYMBOL CONDITIONS MIN 1 Tsk3 CPU-SDRAM 3.25 CPU to SDRAM Skew CPU @ 1.25 V, SDRAM @ 1.5 V 0 Skew Window1 Tw3 CPU-SDRAM 1 T -500 CPU to 3V66 Skew sk3 CPU-3V66 CPU @ 1.25 V, 3V66 @ 1.5 V Tw3 CPU-3V66 0 Skew Window1 1 T -3.25 SDRAM to 3V66 Skew sk3 SDRAM-3V66 SDRAM, 3V66 @ 1.5 V 0 Skew Window1 Tw3 SDRAM-3V66 1 T 1.5 3V66 to PCI Skew sk3 3V66-PCI 3V66, PCI @ 1.5 V Tw3 3V66-PCI 0 Skew Window1 1 T -1 IOAPIC to PCI Skew sk3 IOAPIC-PCI IOAPIC @ 1.25 V, PCI @ 1.5 V 0 Skew Window1 Tw3 IOAPIC-PCI 1 Guaranteed by design, not 100% tested in production. TYP 3.45 155 120 120 -3.08 175 2.2 80 -0.1 0 MAX UNITS 4.25 ns 500 ps 500 ps 500 ps -4.25 ps 500 ps 3.5 ns 500 ps 1 ns 1 ns TYP -15 165 165 105 185 185 2.2 60 -0.1 0 MAX UNITS 500 ps 500 ps 500 ps 500 ps 500 ps 500 ps 3.5 ns 500 ps 1 ns 1 ns Group Skews (CPU133 MHz, SDRAM 100MHz) TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF Refer to Group Offset Waveforms diagram for definition of transition edges. PARAMETER SYMBOL CONDITIONS MIN 1 T CPU @ 1.25 V, SDRAM @ 1.5 V -500 CPU to SDRAM Skew sk3 CPU-SDRAM 1 0 Skew Window Tw3 CPU-SDRAM 1 T CPU @ 1.25 V, 3V66 @ 1.5 V -500 CPU to 3V66 Skew sk3 CPU-3V66 Tw3 CPU-3V66 0 Skew Window1 SDRAM, 3V66 @ 1.5 V -500 SDRAM to 3V66 Skew1 Tsk3 SDRAM-3V66 0 Skew Window1 Tw3 SDRAM-3V66 Tsk3 3V66-PCI 3V66, PCI @ 1.5 V 1.5 3V66 to PCI Skew1 Tw3 3V66-PCI 0 Skew Window1 1 Tsk3 IOAPIC-PCI IOAPIC @ 1.25 V, PCI @ 1.5 V -1 IOAPIC to PCI Skew 0 Skew Window1 Tw3 IOAPIC-PCI 1 Guaranteed by design, not 100% tested in production. 13 ICS9250-28 0ns 10ns 20ns 30ns Cycle Repeats CPU 66MHz CPU 100MHz CPU 133MHz SDRAM 100MHz SDRAM 133MHz 3V66MHz PCI 33MHz APIC 33MHz REF 14.318MHz USB 48MHz Group Offset Waveforms 14 40ns ICS9250-28 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ICS (Slave/Receiver) ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 15 ICS9250-28 General Layout Precautions: 1) Use a ground plane on the top routing layer of the PCB in all areas not used by traces. Ferrite Bead VDD 2) Make all power traces and ground traces as wide as the via pad for lower inductance. Notes: 1 All clock outputs should have provisions for a 15pf capacitor between the clock output and series terminating resistor. Not shown in all places to improve readability of diagram. 2 C1 C1 2 Optional crystal load capacitors are recommended. They should be included in the layout but not inserted unless needed. Component Values: C1 : Crystal load values determined by user C2 : 22µF/20V/D case/Tantalum AVX TAJD226M020R C3 : 15pF capacitor FB = Fair-Rite products 2512066017X1 All unmarked capacitors are 0.01µF ceramic Connections to VDD: 16 Ferrite Bead C2 22µF/20V Tantalum C2 22µF/20V Tantalum 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 VDD 2.5V Power Route 1 C3 Clock Load Ground 3.3V Power Route ICS9250-28 SYMBOL In Millimeters COMMON DIMENSIONS MIN MAX In Inches COMMON DIMENSIONS MIN MAX A 2.413 2.794 .095 .110 A1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c D 0.127 0.254 SEE VARIATIONS .005 .010 SEE VARIATIONS E 10.033 10.668 .395 .420 E1 7.391 7.595 .291 .299 e 0.635 BASIC h 0.381 L 0.508 1.016 SEE VARIATIONS N α 0.025 BASIC 0.635 0° .015 .025 .020 .040 SEE VARIATIONS 8° 0° 8° MAX MIN MAX VARIATIONS N D mm. MIN D (inch) 28 9.398 9.652 .370 .380 34 11.303 11.557 .445 .455 48 15.748 16.002 .620 .630 56 18.288 18.542 .720 .730 20.828 21.082 .820 .830 64 Ordering Information ICS9250yF-28-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 17 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.