ETC PCM1601Y/1K

®
PCM
1601
PCM
160
0
PCM1600
PCM1601
For most current data sheet and other product
information, visit www.burr-brown.com
24-Bit, 96kHz Sampling, 6-Channel,
Enhanced Multi-Level, Delta-Sigma
DIGITAL-TO-ANALOG CONVERTER
TM
FEATURES
APPLICATIONS
● 24-BIT RESOLUTION
● INTEGRATED A/V RECEIVERS
● ANALOG PERFORMANCE:
Dynamic Range: 105dB typ
SNR: 104dB typ
THD+N: 0.0018% typ
Full-Scale Output: 3.1Vp-p typ
● DVD MOVIE AND AUDIO PLAYERS
● HDTV RECEIVERS
● CAR AUDIO SYSTEMS
● DVD ADD-ON CARDS FOR HIGH-END PCs
● DIGITAL AUDIO WORKSTATIONS
● 8x OVERSAMPLING INTERPOLATION FILTER:
Stopband Attenuation: –82dB
Passband Ripple: ±0.002dB
● OTHER MULTI-CHANNEL AUDIO SYSTEMS
● SAMPLING FREQUENCY: 10kHz to 100kHz
● ACCEPTS 16, 18, 20, AND 24-BIT AUDIO DATA
● DATA FORMATS: Standard, I2S, and Left-Justified
● SYSTEM CLOCK: 256fS, 384fS, 512fS, or 768fS
● USER-PROGRAMMABLE FUNCTIONS:
Digital Attenuation: 0dB to –63dB, 0.5dB/Step
Soft Mute
Zero Detect Mute
Zero Flags for Each Output Channel
Digital De-Emphasis
Digital Filter Roll-Off: Sharp or Slow
● DUAL SUPPLY OPERATION:
+5V Analog, +3.3V Digital
● 5V TOLERANT DIGITAL LOGIC INPUTS
● PACKAGES(1): LQFP-48 (PCM1600)
and MQFP-48 (PCM1601)
DESCRIPTION
The PCM1600(1) and PCM1601(1) are CMOS monolithic integrated circuits which feature six 24-bit audio
digital-to-analog converters and support circuitry in
either a LQFP-48 or MQFP-48 package. The digitalto-analog converters utilize Burr-Brown’s enhanced
multi-level, delta-sigma architecture, which employ
4th-order noise shaping and 8-level amplitude quantization to achieve excellent signal-to-noise performance
and a high tolerance to clock jitter.
The PCM1600 and PCM1601 accept industry-standard audio data formats with 16- to 24-bit audio data.
Sampling rates up to 100kHz are supported. A full set
of user-programmable functions are accessible through
a 4-wire serial control port which supports register
write and readback functions.
NOTE: (1) The PCM1600 and PCM1601 utilize the same die and are
electrically the same. All references to the PCM1600 apply equally
to the PCM1601.
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
SBAS116
PDS-1523C
Printed in U.S.A. March, 2000
SPECIFICATIONS
All specifications at +25°C, +VCC = +5V, +VDD = +3.3V, system clock = 384fS (fS = 44.1kHz) and 24-bit data, unless otherwise noted.
PCM1600Y, PCM1601Y
PARAMETER
CONDITIONS
MIN
RESOLUTION
TYP
MAX
24
DATA FORMAT
Audio Data Interface Formats
Data Bit Length
Audio Data Format
Sampling Frequency (fS)
System Clock Frequency
User Selectable
User Selectable
DIGITAL INPUT/OUTPUT
Logic Family
Input Logic Level
VIH
VIL
Input Logic Current
IIH(1)
IIL(1)
IIH(2)
IIL(2)
Output Logic Level
VOH(3)
VOL(3)
VOH(4)
VOL(4)
DYNAMIC PERFORMANCE(5)
THD+N, VOUT = 0dB
VOUT = –60dB
Dynamic Range
Signal-to-Noise Ratio(6)
Channel Separation
Level Linearity Error
UNITS
Bits
Standard, I2S, Left-Justified
16, 18, 20, 24-Bit
MSB-First, Binary Two’s Complement
10
100
256, 384, 512, 768fS
kHz
TTL-Compatible
2.0
VIN = VDD
VIN = 0V
VIN = VDD
VIN = 0V
65
IOH = –2mA
IOL = +2mA
IOH = –4mA
IOL = +4mA
ANALOG OUTPUT
Output Voltage
Center Voltage
Load Impedance
DIGITAL FILTER PERFORMANCE
Filter Characteristics 1, Sharp Roll-Off
Passband
Stopband
Passband Ripple
Stopband Attenuation
Filter Characteristics 2, Slow Roll-Off
Passband
Stopband
Passband Ripple
Stopband Attenuation
Delay Time
De-Emphasis Error
ANALOG FILTER PERFORMANCE
Frequency Response
0.1
–0.1
100
–0.1
µA
µA
µA
µA
1.0
2.4
1.0
100
98
96
VO = 0.5VCC at Bipolar Zero
Full Scale (0dB)
AC Load
0.0018
0.0035
0.65
0.75
105
104
104
103
102
101
±0.5
0.0045
62% of VCC
50% VCC
Vp-p
V
kΩ
0.454fS
0.490fS
0.546fS
±0.002
–75
–82
±0.002dB
–3dB
0.274fS
0.454fS
f = 20kHz
f = 44kHz
2
Hz
Hz
Hz
dB
dB
dB
34/fS
±0.1
Hz
Hz
Hz
dB
dB
sec
dB
–0.03
–0.20
dB
dB
0.732fS
Stopband = 0.732fS
%
%
%
%
dB
dB
dB
dB
dB
dB
dB
% of FSR
% of FSR
mV
±0.002dB
–3dB
Stopband = 0.546fS
Stopband = 0.567fS
V
V
V
V
±1.0
±1.0
±30
5
®
PCM1600, PCM1601
V
V
2.4
fS = 44.1kHz
fS = 96kHz
fS = 44.1kHz
fS = 96kHz
EIAJ, A-Weighted, fS =44.1kHz
A-Weighted, fS = 96kHz
EIAJ, A-Weighted, fS =44.1kHz
A-Weighted, fS = 96kHz
fS = 44.1kHz
fS = 96kHz
VOUT = –90dB
DC ACCURACY
Gain Error
Gain Mismatch, Channel-to-Channel
Bipolar Zero Error
0.8
±0.002
–82
SPECIFICATIONS (Cont.)
All specifications at +25°C, +VCC = +5V, +VDD = +3.3V, system clock = 384fS (fS = 44.1kHz) and 24-bit data, unless otherwise noted.
PCM1600Y, PCM1601Y
PARAMETER
CONDITIONS
POWER SUPPLY REQUIREMENTS
Voltage Range, VDD
VCC
Supply Current, IDD (7)
MIN
TYP
MAX
UNITS
+3.0
+4.5
+3.3
+5.0
20
42
40
42
266
349
+3.6
+5.5
28
V
V
mA
mA
mA
mA
mW
mW
fS = 44.1kHz
fS = 96kHz
fS = 44.1kHz
fS = 96kHz
fS = 44.1kHz
fS = 96kHz
ICC
Power Dissipation
TEMPERATURE RANGE
Operation
Storage
Thermal Resistance, θJA
0
–55
56
409
+70
+125
100
°C
°C
°C/W
NOTES: (1) Pins 38, 40, 41, 45-47 (SCLKI, BCK, LRCK, DATA1, DATA2, DATA3). (2) Pins 34-37 (MDI, MC, ML, RST). (3) Pins 1-6, 48 (ZERO1-6, ZEROA).
(4) Pin 39 (SCLKO). (5) Analog performance specifications are tested with Shibasoku #725 THD Meter 400Hz HPF, 30kHz LPF on, average mode with 20kHz
bandwidth limiting. The load connected to the analog output is 5kΩ or larger, AC-coupled. (6) SNR is tested with Infinite Zero Detection off. (7) CLKO is disabled.
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Power Supply Voltage, VDD .............................................................. +4.0V
VCC .............................................................. +6.5V
+VCC to +VDD Difference ................................................................... ±0.1V
Digital Input Voltage ........................................................... –0.2V to +5.5V
Digital Output Voltage(1) ........................................... –0.2V to (VDD + 0.2V)
Input Current (except power supply) ............................................... ±10mA
Power Dissipation .......................................................................... 650mW
Operating Temperature Range ............................................. 0°C to +70°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s) ................................................ +260°C
Package Temperature (IR reflow, 10s) .......................................... +235°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Pin 33 (MDO) when output is disabled.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
PCM1600Y
48-Lead LQFP
340
0°C to +70°C
PCM1600Y
"
"
"
"
48-Lead MQFP
359
0°C to +70°C
PCM1601Y
"
"
"
"
"
PCM1601Y
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PCM1600Y
PCM1600Y/2K
PCM1601Y
PCM1601Y/1K
250-Piece Tray
Tape and Reel
84-Piece Tray
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “PCM1600Y/2K” will get a single 2000-piece Tape and Reel.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
PCM1600, PCM1601
BLOCK DIAGRAM
DAC
Output Amp and
Low-Pass Filter
DAC
Output Amp and
Low-Pass Filter
DAC
Output Amp and
Low-Pass Filter
BCK
VOUT1
LRCK
DATA1
DATA2
Audio
Serial
I/F
8x
Oversampling
Digital Filter
with
Function
Controller
DATA3
TEST
Enhanced
Multi-level
Delta-Sigma
Modulator
VOUT2
VOUT3
VCOM1
VCOM2
Output Amp and
Low-Pass Filter
DAC
VOUT4
RST
ML
MC
Serial
Control
I/F
Output Amp and
Low-Pass Filter
DAC
VOUT5
MDI
MDO
Output Amp and
Low-Pass Filter
DAC
VOUT6
System Clock
VCC1-6
AGND1-6
VCC0
AGND0
VDD
DGND
ZERO6
ZERO5
ZERO4
ZERO3
ZERO2
ZEROA
SCLKO
VCC
Power Supply
Zero Detect
AGND
System Clock
Manager
ZERO1
SCLKI
PIN CONFIGURATION
DATA3
DATA2
DATA1
DGND
VDD
TEST
LRCK
BCK
SCLKO
SCLKI
RST
LQFP, MQFP
ZEROA
Top View
48
47
46
45
44
43
42
41
40
39
38
37
ZERO1
1
36 ML
ZERO2
2
35 MC
ZERO3
3
34 MDI
ZERO4
4
33 MDO
ZERO5
5
32 NC
ZERO6
6
AGND
7
VCC
8
29 AGND0
VOUT6
9
28 VCC1
31 NC
PCM1600
PCM1601
30 VCC0
19
20
21
22
23
24
VCC3
18
AGND3
17
VCC4
16
AGND4
15
VCC5
14
AGND5
13
VCC6
25 AGND2
AGND6
VOUT3 12
VCOM1
26 VCC2
VCOM2
VOUT4 11
VOUT1
27 AGND1
VOUT2
VOUT5 10
®
PCM1600, PCM1601
4
PIN ASSIGNMENTS
PIN
NAME
I/O
1
ZERO1
O
Zero Data Flag for VOUT1.
DESCRIPTION
2
ZERO2
O
Zero Data Flag for VOUT2.
3
ZERO3
O
Zero Data Flag for VOUT3.
4
ZERO4
O
Zero Data Flag for VOUT4.
5
ZERO5
O
Zero Data Flag for VOUT5.
6
ZERO6
O
Zero Data Flag for VOUT6.
7
AGND
—
Analog Ground
8
VCC
—
Analog Power Supply, +5V
9
VOUT6
O
Voltage Output of Audio Signal Corresponding to Rch on DATA3.
10
VOUT5
O
Voltage Output of Audio Signal Corresponding to Lch on DATA3.
11
VOUT4
O
Voltage Output of Audio Signal Corresponding to Rch on DATA2.
12
VOUT3
O
Voltage Output of Audio Signal Corresponding to Lch on DATA2.
13
VOUT2
O
Voltage Output of Audio Signal Corresponding to Rch on DATA1.
14
VOUT1
O
Voltage Output of Audio Signal Corresponding to Lch on DATA1.
15
VCOM2
O
Common Voltage Output. This pin should be bypassed with a 10µF capacitor to AGND.
16
VCOM1
O
Common Voltage Output. This pin should be bypassed with a 10µF capacitor to AGND.
17
AGND6
—
Analog Ground
Analog Power Supply, +5V
18
VCC6
—
19
AGND5
—
Analog Ground
20
VCC5
—
Analog Power Supply, +5V
21
AGND4
—
Analog Ground
22
VCC4
—
Analog Power Supply, +5V
23
AGND3
—
Analog Ground
24
VCC3
—
Analog Power Supply, +5V
25
AGND2
—
Analog Ground
26
VCC2
—
Analog Power Supply, +5V
27
AGND1
—
Analog Ground
28
VCC1
—
Analog Power Supply, +5V
29
AGND0
—
Analog Ground
30
VCC0
—
Analog Power Supply, +5V
31
NC
—
No Connection. Must be open.
32
NC
—
No Connection. Must be open.
33
MDO
O
Serial Data Output for Function Register Control Port (3)
34
MDI
I
Serial Data Input for Function Register Control Port(1)
35
MC
I
Shift Clock for Function Register Control Port(1)
36
ML
I
Latch Enable for Function Register Control Port(1)
37
RST
I
System Reset, Active LOW(1)
38
SCLKI
I
System Clock In. Input frequency is 256, 384, 512 or 768f S.(2)
39
SCLKO
O
Buffered Clock Output. Output frequency is 256, 384, 512, or 768fS and one-half of 256, 384, 512, or 768fS.
40
BCK
I
Shift Clock Input for Serial Audio Data(2)
41
LRCK
I
42
TEST
—
Left and Right Clock Input. This clock is equal to the sampling rate, fS. (2)
Test Pin. This pin should be connected to DGND.(1)
43
VDD
—
Digital Power Supply, +3.3V
44
DGND
—
Digital Ground for +3.3V
45
DATA1
I
Serial Audio Data Input for VOUT1 and VOUT2(2)
46
DATA2
I
Serial Audio Data Input for VOUT3 and VOUT4(2)
47
DATA3
I
Serial Audio Data Input for VOUT5 and VOUT6(2)
48
ZEROA
I
Zero Data Flag. Logical “AND” of ZERO1 through ZERO6.
NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant. (2) Schmitt-Trigger input, 5V tolerant. (3) Tri-state output.
®
5
PCM1600, PCM1601
TYPICAL PERFORMANCE CURVES
All specifications at +25°C, VCC = 5V, VDD = 3.3V, SYSCLK = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted.
DIGITAL FILTER
Digital Filter (De-Emphasis Off, fS = 44.1kHz)
FREQUENCY RESPONSE
(Sharp Roll-Off)
PASSBAND RIPPLE
(Sharp Roll-Off)
0.003
0
–20
0.002
Amplitude (dB)
Amplitude (dB)
–40
–60
–80
–100
0.001
0
–0.001
–120
–0.002
–140
–160
–0.003
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.1
0.2
0.3
0.4
0.5
Frequency (x fS)
Frequency (x fS)
FREQUENCY RESPONSE
(Slow Roll-Off)
TRANSITION CHARACTERISTICS
(Slow Roll-Off)
0
0
–2
–20
–4
Amplitude (dB)
Amplitude (dB)
–40
–60
–80
–100
–6
–8
–10
–12
–14
–16
–120
–18
–140
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
–20
4.0
0
0.1
0.2
Frequency (x fS)
DE-EMPHASIS FREQUENCY RESPONSE (fS = 32kHz)
Level (dB)
Level (dB)
De-Emphasis Error
0
–2
–4
–6
–8
–10
0
2
4
6
8
10
12
0
14
Level (dB)
Level (dB)
2
4
6
8
10
12
2
4
14
16
18
0
20
Level (dB)
Level (dB)
2
4
6
8
10
12
14
6
8
10
12
14
2
4
6
8
10
12
14
16
18
20
20
22
Frequency (kHz)
DE-EMPHASIS FREQUENCY RESPONSE (fS = 48kHz)
0
0.6
DE-EMPHASIS ERROR (fS = 44.1kHz)
0.5
0.3
0.1
–0.1
–0.3
–0.5
Frequency (kHz)
0
–2
–4
–6
–8
–10
0.5
Frequency (kHz)
DE-EMPHASIS FREQUENCY RESPONSE (fS = 44.1kHz)
0
0.4
DE-EMPHASIS ERROR (fS = 32kHz)
0.5
0.3
0.1
–0.1
–0.3
–0.5
Frequency (kHz)
0
–2
–4
–6
–8
–10
0.3
Frequency (x fS)
16
18
20
0
22
2
4
6
8
10
12
14
Frequency (kHz)
Frequency (kHz)
®
PCM1600, PCM1601
DE-EMPHASIS ERR0R (fS = 48kHz)
0.5
0.3
0.1
–0.1
–0.3
–0.5
6
16
18
TYPICAL PERFORMANCE CURVES (Cont.)
All specifications at +25°C, VCC = 5V, VDD = 3.3V, SYSCLK = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted.
ANALOG DYNAMIC PERFORMANCE
Supply Voltage Characteristics
TOTAL HARMONIC DISTORTION + NOISE vs VCC
(VDD = 3.3V)
10
110
108
THD+N (%)
1
Dynamic Range (dB)
96kHz, 384fS
–60dB
44.1kHz, 384fS
0.1
96kHz, 384fS
0.01
DYNAMIC RANGE vs VCC
(VDD = 3.3V)
44.1kHz, 384fS
106
104
96kHz, 384fS
102
100
98
0dB
44.1kHz, 384fS
0.001
4.0
110
4.5
96
5.0
5.5
4.0
6.0
5.0
5.5
VCC (V)
SIGNAL-TO-NOISE RATIO vs VCC
(VDD = 3.3V)
CHANNEL SEPARATION vs VCC
(VDD = 3.3V)
110
6.0
108
106
Channel Separation (dB)
108
SNR (dB)
4.5
VCC (V)
44.1kHz, 384fS
104
102
96kHz, 384fS
100
106
104
44.1kHz, 384fS
102
100
96kHz, 384fS
98
98
96
96
4.0
4.5
5.0
5.5
4.0
6.0
4.5
5.0
5.5
6.0
VCC (V)
VCC (V)
®
7
PCM1600, PCM1601
TYPICAL PERFORMANCE CURVES (Cont.)
All specifications at +25°C, VCC = 5V, VDD = 3.3V, SYSCLK = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted.
ANALOG DYNAMIC PERFORMANCE (con.t)
Temperature Characteristics
TOTAL HARMONIC DISTORTION + NOISE
vs TEMPERATURE
(VDD = 3.3V)
110
10
108
THD+N (%)
Dynamic Range (dB)
96kHz, 384fS
1
–60dB
44.1kHz, 384fS
0.1
96kHz, 384fS
0.01
44.1kHz, 384fS
44.1kHz, 384fS
106
104
102
96kHz, 384fS
100
98
0dB
96
0.001
–25
0
25
50
75
–25
100
0
25
50
75
Temperature (°C)
Temperature (°C)
SIGNAL-TO-NOISE RATIO vs TEMPERATURE
(VDD = 3.3V)
CHANNEL SEPARATION vs TEMPERATURE
(VDD = 3.3V)
110
108
108
Channel Separation (dB)
110
106
SNR (dB)
DYNAMIC RANGE vs TEMPERATURE
(VDD = 3.3V)
44.1kHz, 384fS
104
102
96kHz, 384fS
100
100
106
104
44.1kHz, 384fS
102
100
96kHz, 384fS
98
98
96
96
–25
0
25
50
75
–25
100
®
PCM1600, PCM1601
0
25
50
Temperature (°C)
Temperature (°C)
8
75
100
SYSTEM CLOCK OUTPUT
SYSTEM CLOCK AND RESET
FUNCTIONS
A buffered version of the system clock input is available at
the SCLKO output (pin 39). SCLKO can operate at either
full (fSCLKI) or half (fSCLKI/2) rate. The SCLKO output
frequency may be programmed using the CLKD bit of
Control Register 9. The SCLKO output pin can also be
enabled or disabled using the CLKE bit of Control Register
9. The default is SCLKO enabled.
SYSTEM CLOCK INPUT
The PCM1600 and PCM1601 require a system clock for
operating the digital interpolation filters and multi-level
delta-sigma modulators. The system clock is applied at the
SCLKI input (pin 38). For sampling rates from 10kHz
through 64kHz, the system clock frequency may be 256,
384, 512, or 768 times the sampling frequency, fS. For
sampling rates above 64kHz, the system clock frequency
may be 256, 384, or 512 times the sampling frequency.
Table I shows examples of system clock frequencies for
common audio sampling rates.
POWER-ON AND EXTERNAL RESET FUNCTIONS
The PCM1600 includes a power-on reset function. Figure 2
shows the operation of this function.
The system clock input at SCLKI should be active for at
least one clock period prior to VDD = 2.0V. With the system
clock active and VDD > 2.0V, the power-on reset function
will be enabled. The initialization sequence requires 1024
system clocks from the time VDD > 2.0V. After the initialization period, the PCM1600 will be set to its reset default
state, as described in the Mode Control Register section of
this data sheet.
Figure 1 shows the timing requirements for the system clock
input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. Burr-Brown’s
PLL1700 multi-clock generator is an excellent choice for
providing the PCM1600 system clock source.
The PCM1600 also includes an external reset capability
using the RST input (pin 37). This allows an external
controller or master reset circuit to force the PCM1600 to
initialize to its reset default state. For normal operation, RST
should be set to a logic ‘1’.
SYSTEM CLOCK FREQUENCY (MHz)
SCLKI (Pin 38)
SAMPLING
FREQUENCY (fS)
256fS
384fS
512fS
768fS
22.05kHz
5.6448
8.4670
11.2896
16.9340
24kHz
6.1440
9.2160
12.2880
18.4320
32kHz
8.1920
12.2880
16.3840
24.5760
44.1kHz
11.2896
16.9340
22.5792
33.8688
48kHz
12.2880
18.4320
24.5760
36.8640
64kHz
16.3840
24.5760
32.7680
49.1520
88.2kHz
22.5792
33.8688
45.1584
See Note 1
96kHz
24.5760
36.8640
49.1520
See Note 1
Figure 3 shows the external reset operation and timing. The
RST pin is set to logic ‘0’ for a minimum of 20ns. The RST
pin is then set to a logic ‘1’ state, which starts the initialization sequence, which lasts for 1024 system clock periods.
After the initialization sequence is completed, the PCM1600
will be set to its reset default state, as described in the Mode
Control Registers section of this data sheet.
NOTE: (1) The 768fS system clock rate is not supported for fS > 64kHz.
TABLE I. System Clock Rates for Common Audio Sampling
Frequencies.
tSCLKIH
2.0V
“H”
SCLKI
0.8V
“L”
fSCLKI
tSCLKIH
System Clock Pulse Width High tSCLKIH
System Clock Pulse Width Low tSCLKIL
: 7ns min
: 7ns min
FIGURE 1. System Clock Input Timing.
®
9
PCM1600, PCM1601
2.4V
2.0V
1.6V
VCC = VDD
Reset
Reset Removal
Internal Reset
1024 system clocks
System Clock
(SCLKI)
FIGURE 2. Power-On Reset Timing.
RST
tRST(1)
Reset
Reset Removal
Internal Reset
1024 system clocks
System Clock
(SCLKI)
NOTE: (1) tRST = 20ns min.
FIGURE 3. External Reset Timing.
default data format is 24-bit Standard. All formats require
Binary Two’s Complement, MSB-first audio data. Figure 5
shows a detailed timing diagram for the serial audio interface.
The external reset is especially useful in applications
where there is a delay between PCM1600 power up and
system clock activation. In this case, the RST pin should
be held at a logic ‘0’ level until the system clock has been
activated.
DATA1, DATA2 and DATA3 each carry two audio channels,
designated as the Left and Right channels. The Left channel
data always precedes the Right channel data in the serial data
stream for all data formats. Table II shows the mapping of the
digital input data to the analog output pins.
AUDIO SERIAL INTERFACE
The audio serial interface for the PCM1600 is comprised
of a 5-wire synchronous serial port. It includes LRCK (pin
41), BCK (pin 40), DATA1 (pin 45), DATA2 (pin 46) and
DATA3 (pin 47). BCK is the serial audio bit clock, and is
used to clock the serial data present on DATA1, DATA2
and DATA3 into the audio interface’s serial shift registers.
Serial data is clocked into the PCM1600 on the rising edge
of BCK. LRCK is the serial audio left/right word clock. It
is used to latch serial data into the serial audio interface’s
internal registers.
CHANNEL
DATA1
Left
ANALOG OUTPUT
VOUT1
DATA1
Right
VOUT2
DATA2
Left
VOUT3
DATA2
Right
VOUT4
DATA3
Left
VOUT5
DATA3
Right
VOUT6
TABLE II. Audio Input Data to Analog Output Mapping.
Both LRCK and BCK must be synchronous to the system
clock. Ideally, it is recommended that LRCK and BCK be
derived from the system clock input or output, SCLKI or
SCLKO. The left/right clock, LRCK, is operated at the
sampling frequency (fS). The bit clock, BCK, may be
operated at 48 or 64 times the sampling frequency.
SERIAL CONTROL INTERFACE
The serial control interface is a 4-wire synchronous serial port
which operates asynchronously to the serial audio interface.
The serial control interface is utilized to program and read the
on-chip mode registers. The control interface includes MDO
(pin 33), MDI (pin 34), MC (pin 35), and ML (pin 36). MDO
is the serial data output, used to read back the values of the
mode registers; MDI is the serial data input, used to program
the mode registers; MC is the serial bit clock, used to shift
data in and out of the control port and ML is the control port
latch clock.
AUDIO DATA FORMATS AND TIMING
The PCM1600 supports industry-standard audio data formats, including Standard, I2S, and Left-Justified. The data
formats are shown in Figure 4. Data formats are selected
using the format bits, FMT[2:0], in Control Register 9. The
®
PCM1600, PCM1601
DATA INPUT
10
11
PCM1600, PCM1601
®
16 17 18
18 19 20
22 23 24
18-Bit Right-Justified
DATA1-DATA3
20-Bit Right-Justified
DATA1-DATA3
24-Bit Right-Justified
DATA1-DATA3
MSB
1
2
3
4
5
MSB
1
2
3
MSB
1
2
Lch
3
MSB
1
1
2
3
FIGURE 4. Audio Data Input Formats.
DATA1-DATA3
BCK
(= 48fS or 64fS)
LRCK
MSB
1
2
3
Lch
(3) 24-Bit I2S Data Format; Lch = LOW, Rch = HIGH
DATA1-DATA3
BCK
(= 48fS or 64fS)
LRCK
22
22
Lch
LSB
23 24
23 24
(2) 24-Bit Left-Justified Data Format; Lch = HIGH, Rch = LOW
14 15 16
16-Bit Right-Justified
DATA1-DATA3
BCK
(= 48fS or 64fS)
LRCK
(1) Standard Data Format; Lch = HIGH, Rch = LOW
2
3
1/fS
2
MSB
1
2
MSB
1
1/fS
3
3
LSB
22 23 24
LSB
18 19 20
LSB
16 17 18
LSB
14 15 16
MSB
1
1/fS
Rch
2
3
22
22
Rch
4
LSB
23 24
2
LSB
23 24
5
MSB
1
3
MSB
1
2
Rch
3
MSB
1
1
2
2
3
LSB
22 23 24
LSB
18 19 20
LSB
16 17 18
LSB
14 15 16
LRCK
50% of VDD
tBCH
tBCL
tLB
BCK
50% of VDD
tBCY
tBL
50% of VDD
DATA1-DATA3
tDH
tDS
SYMBOL
tBCY
tBCH
tBCL
tBL
tLB
tDS
tDH
PARAMETER
MIN
BCK Pulse Cycle Time
BCK High Level Time
BCK Low Level Time
BCK Rising Edge to LRCK Edge
LRCK Falling Edge to BCK Rising Edge
DIN Set Up Time
DIN Hold Time
MAX
UNITS
48 or 64fS
(1)
50
50
30
30
30
20
ns
ns
ns
ns
ns
ns
NOTE: (1) fS is the sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.)
FIGURE 5. Audio Interface Timing.
MSB
R/W
LSB
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
D7
D6
D5
D4
Register Index (or Address)
D3
D2
D5
D4
D3
D2
D1
D0
Register Data
Read/Write Operation
0 = Write Operation
1 = Read Operation (register index is ignored)
FIGURE 6. Control Data Word Format for MDI.
ML
MC
MDI
X
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7
D6
D5
D4
D3
D2
D1
D0
X
X
D15 D14
FIGURE 7. Write Operation Timing.
REGISTER WRITE OPERATION
SINGLE REGISTER READ OPERATION
All Write operations for the serial control port use 16-bit
data words. Figure 6 shows the control data word format.
The most significant bit is the Read/Write (R/W) bit. When
set to ‘0’, this bit indicates a Write operation. There are
seven bits, labeled IDX[6:0], that set the register index (or
address) for the Write operation. The least significant eight
bits, D[7:0], contain the data to be written to the register
specified by IDX[6:0].
Read operations utilize the 16-bit control word format shown
in Figure 6. For Read operations, the Read/Write (R/W) bit
is set to ‘1’. Read operations ignore the index bits, IDX[6:0],
of the control data word. Instead, the REG[6:0] bits in
Control Register 11 are used to set the index of the register
that is to be read during the Read operation. Bits IDX[6:0]
should be set to 00H for Read operations.
Figure 8 details the Read operation. First, Control Register
11 must be written with the index of the register to be read
back. Additionally, the INC bit must be set to logic ‘0’ in
order to disable the Auto-Increment Read function. The
Read cycle is then initiated by setting ML to logic ‘0’ and
setting the R/W bit of the control data word to logic ‘1’,
indicating a Read operation. MDO remains at a high-impedance state until the last 8 bits of the 16-bit read cycle, which
Figure 7 shows the functional timing diagram for writing the
serial control port. ML is held at a logic ‘1’ state until a
register needs to be written. To start the register write cycle,
ML is set to logic ‘0’. Sixteen clocks are then provided on
MC, corresponding to the 16-bits of the control data word on
MDI. After the sixteenth clock cycle has completed, ML is
set to logic ‘1’ to latch the data into the indexed mode
control register.
®
PCM1600, PCM1601
12
13
PCM1600, PCM1601
®
I
O
I
O
I
O
I
O
Write
0
0
X = Don't care
0
0
0
1
1
0
1
0
0
0
0
High Impedance
0
0
0
D7
X
D6
X
D5
X
D3
X
INDEX “1”
D4
X
D2
X
FIGURE 9. Read Operation Timing with INC = 1 (Auto-Increment Read).
MDO
MDI
MC
ML
D1
X
High Impedance
Read Register Index
D0
X
X
X
D7
REG6 REG5 REG4 REG3 REG2 REG1 REG0
Writing Register 11 with INC and REG[6:0] Data
1
FIGURE 8. Read Operation Timing with INC = 0 (Single Register Read).
MDO
MDI
MC
ML
D6
X
X
D4
X
D3
X
Read
0
0
X
0
D2
INDEX “N – 1”
D5
X
1
D1
X
0
D0
X
0
0
X
D7
X
D6
X
D7
D5
X
X
X
X
X
X
X
D6
D3
X
INDEX “N”
D4
X
D5
D2
X
D4
D1
X
D3
D0
X
D2
D0
High Impedance
X
D1
Data from Register Indexed by REG[6:0]
X
Register Read Cycle
0
corresponds to the 8 data bits of the register indexed by the
REG[6:0] bits of Control Register 11. The Read cycle is
completed when ML is set to ‘1’, immediately after the MC
clock cycle for the least significant bit of indexed control
register has completed.
pin. The Read cycle starts by setting the R/W bit of the
control word to ‘1’, and setting all of the IDX[6:0] bits to
‘0.’. All subsequent bits input on the MDI are ignored while
ML is set to ‘0.’ For the first 8 clocks of the Read cycle,
MDO is set to a high-impedance state. This is followed by
a sequence of 8-bit words, each corresponding the data
contained in Control Registers 1 through N, where N is
defined by the REG[6:0] bits in Control Register 11. The
Read cycle is completed when ML is set to ‘1’, immediately
after the MC clock cycle for the least significant bit of
Control Register N has completed.
AUTO-INCREMENT READ OPERATION
The Auto-Increment Read function allows for multiple registers to be read sequentially. The Auto-Increment Read
function is enabled by setting the INC bit of Control Register
11 to ‘1’. The sequence always starts with Register 1, and
ends with the register indexed by the REG[6:0] bits in
Control Register 11.
CONTROL INTERFACE TIMING REQUIREMENTS
Figure 10 shows a detailed timing diagram for the Serial
Control interface. Pay special attention to the setup and hold
times, as well as tMLS and tMLH, which define minimum delays
between edges of the ML and MC clocks. These timing
parameters are critical for proper control port operation.
Figure 9 shows the timing for the Auto-Increment Read
operation. The operation begins by writing Control Register
11, setting INC to ‘1’ and setting REG[6:0] to the last
register to be read in the sequence. The actual Read operation starts on the next HIGH to LOW transition of the ML
tMHH
50% of VDD
ML
tMLS
tMCH
tMCL
tMLH
50% of VDD
MC
tMCY
LSB
MDI
50% of VDD
tMOS
tMDS
tMCH
LSB
50% of VDD
MDO
SYMBOL
tMCY
tMCL
tMCH
tMHH
tMLS
tMLH
tMDI
tMDS
tMOS
PARAMETER
MIN
MC Pulse Cycle Time
MC Low Level Time
MC High Level Time
ML High Level Time
ML Falling Edge to MC Rising Edge
ML Hold Time(1)
Hold Time
MDL Set Up Time
MC Falling Edge to MDSO Stable
100
50
50
300
20
20
15
20
NOTE: (1) MC rising edge for LSB to ML rising edge.
FIGURE 10. Control Interface Timing.
®
PCM1600, PCM1601
14
MAX
UNITS
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
MODE CONTROL REGISTERS
Register Map
User-Programmable Mode Controls
The PCM1600 includes a number of user-programmable
functions which are accessed via control registers. The
registers are programmed using the Serial Control Interface
which was previously discussed in this data sheet. Table III
lists the available mode control functions, along with their
reset default conditions and associated register index.
The mode control register map is shown in Table IV. Each
register includes a R/W bit, which determines whether a
register read (R/W =1) or write (R/W = 0) operation is
performed. Each register also includes an index (or address)
indicated by the IDX[6:0] bits.
FUNCTION
Reserved Registers
Registers 0 and 12 are reserved for factory use. To ensure
proper operation, the user should not write or read these
registers.
RESET DEFAULT
CONTROL REGISTER
INDEX, IDX[6:0]
Digital Attenuation Control, 0dB to –63dB in 0.5dB Steps
0dB, No Attenuation
1 through 6
01H - 07H
Digital Attenuation Load Control
Data Load Disabled
7
07H
Digital Attenuation Rate Select
2/fS
7
07H
Soft Mute Control
DAC 1-6 Operation Control
Mute Disabled
7
07H
DAC 1-6 Enabled
8
08H
Infinite Zero Detect Mute
Disabled
8
08H
24-Bit Standard Format
9
09H
Digital Filter Roll-Off Control
Sharp Roll-Off
9
09H
SCLKO Frequency Selection
Full Rate (= fSCLKI)
9
09H
Audio Data Format Control
SCLKO Output Enable
De-Emphasis Function Control
SCLKO Enabled
9
09H
De-Emphasis Disabled
10
0AH
De-Emphasis Sample Rate Selection
44.1kHz
10
0AH
Read Register Index Control
REG[6:0] = 01H
11
0BH
Read Auto-Increment Control
Auto-Increment Disabled
11
0BH
TABLE III. User-Programmable Mode Controls.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 0
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Register 1
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT17
AT16
AT15
AT14
AT13
AT12
AT11
AT10
Register 2
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT27
AT26
AT25
AT24
AT23
AT22
AT21
AT20
Register 3
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT37
AT36
AT35
AT34
AT33
AT32
AT31
AT30
Register 4
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT47
AT46
AT45
AT44
AT43
AT42
AT41
AT40
Register 5
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT57
AT56
AT55
AT54
AT53
AT52
AT51
AT50
Register 6
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT67
AT66
AT65
AT64
AT63
AT62
AT61
AT60
Register 7
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
ATLD
ATTS
MUT6
MUT5
MUT4
MUT3
MUT2 MUT1
Register 8
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
res
INZD
DAC6
DAC5
DAC4
DAC3
DAC2 DAC1
Register 9
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
res
res
FLT0
CLKD
CLKE
FMT2
FMT1 FMT0
Register 10
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
res
res
res
DMF1
DMF0
DM56
DM34 DM12
Register 11
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
INC
REG6
REG5
REG4
REG3
REG2
REG1 REG0
Register 12
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
TABLE IV. Mode Control Register Map.
®
15
PCM1600, PCM1601
REGISTER DEFINITIONS
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 1
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT17
AT16
AT15
AT14
AT13
AT12
AT11
AT10
Register 2
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT27
AT26
AT25
AT24
AT23
AT22
AT21
AT20
Register 3
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT37
AT36
AT35
AT34
AT33
AT32
AT31
AT30
Register 4
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT47
AT46
AT45
AT44
AT43
AT42
AT41
AT40
Register 5
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT57
AT56
AT55
AT54
AT53
AT52
AT51
AT50
Register 6
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT67
AT66
AT65
AT64
AT63
AT62
AT61
AT60
R/W
Read/Write Mode Select
When R/W = 0, a Write operation is performed.
When R/W = 1, a Read operation is performed.
Default Value: 0
ATx[7:0]
Digital Attenuation Level Setting
where x = 1-6, corresponding to the DAC output VOUTx.
These bits are Read/Write.
Default Value: 1111 1111B
Each DAC output, VOUT1 through VOUT6, has a digital attenuator associated with it. The attenuator may be
set from 0dB to –63dB, in 0.5dB steps. Alternatively, the attenuator may be set to infinite attenuation (or
mute).
The attenuation data for each channel can be set individually. However, the data load control (ATLD bit of
Control Register 7) is common to all six attenuators. ATLD must be set to ‘1’ in order to change an
attenuator’s setting. The attenuation level may be set using the formula below.
Attenuation Level (dB) = 0.5 (AT x [7:0]DEC – 255)
where: AT x [7:0]DEC = 0 through 255
for: AT x [7:0]DEC = 0 through 128, the attenuator is set to infinite attenuation.
The following table shows attenuator levels for various settings.
ATx[7:0]
Decimal Value
Attenuator Level Setting
1111 1111B
1111 1110B
1111 1101B
•
•
•
1000 0010B
1000 0001B
1000 0000B
•
•
•
0000 0000B
255
254
253
•
•
•
130
129
128
•
•
•
0
0dB, No Attenuation (default)
–0.5dB
–1.0dB
•
•
•
–62.5dB
–63.0dB
Mute
•
•
•
Mute
®
PCM1600, PCM1601
16
Register 7
R/W
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
ATLD
ATTS
MUT6
MUT5
MUT4
MUT3
MUT2
MUT1
Read/Write Mode Select
When R/W = 0, a Write operation is performed.
When R/W = 1, a Read operation is performed.
Default Value: 0
ATLD
Attenuation Control
This bit is Read/Write.
Default Value: 0
ATLD = 0
ATLD = 1
Attenuation Control Disabled (default)
Attenuation Control Enabled
The ATLD bit must be set to logic “1” in order for the attenuators to function. Setting ATLD to logic “0” will
disable the attenuator function and cause the current attenuator data to be lost.
Set ATLD = 1 immediately after reset.
ATTS
Attenuation Rate Select
This bit is Read/Write.
Default Value: 0
ATTS = 0
ATTS = 1
Attenuation rate is 2/fS (default)
Attenuation rate is 4/fS
Changes in attenuator levels are made by incrementing or decrementing the attenuator by one step (0.5dB) for
every 2/fS or 4/fS time interval until the programmed attenuator setting is reached. This helps to minimize
audible ‘clicking’, or zipper noise, while the attenuator is changing levels. The ATTS bit allows you to select
the rate at which the attenuator is decremented/incremented during level transitions.
MUTx
Soft Mute Control
where x = 1-6, corresponding to the DAC output VOUTx.
These bits are Read/Write.
Default Value: 0
MUTx = 0
MUTx = 1
Mute Disabled (default)
Mute Enabled
The mute bits, MUT1 through MUT6, are used to enable or disable the Soft Mute function for the
corresponding DAC outputs, VOUT1 through VOUT6. The Soft Mute function is incorporated into the digital
attenuators. When Mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When Mute
is enabled by setting MUTx = 1, the digital attenuator for the corresponding output will be decremented
from the current setting to the infinite attenuation setting one attenuator step (0.5dB) at a time, with the rate
of change programmed by the ATTS bit. This provides a quiet, ‘pop’ free muting of the DAC output. Upon
returning from Soft Mute, by setting MUTx = 0, the attenuator will be incremented one step at a time to
the previously programmed attenuator level.
®
17
PCM1600, PCM1601
REGISTER 8
R/W
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
res
INZD
DAC6
DAC5
DAC4
DAC3
B1
B0
DAC2 DAC1
Read/Write Mode Select
When R/W = 0, a Write operation is performed.
When R/W = 1, a Read operation is performed.
Default Value: 0
INZD
Infinite Zero Detect Mute Control
This bit is Read/Write.
Default Value: 0
INZD = 0
INZD = 1
Infinite Zero Detect Mute Disabled (default)
Infinite Zero Detect Mute Enabled
The INZD bit is used to enable or disable the Zero Detect Mute function described in the Zero Flag and Infinite
Zero Detect Mute section in this data sheet. The Zero Detect Mute function is independent of the Zero Flag
output operation, so enabling or disabling the INZD bit has no effect on the Zero Flag outputs (ZERO1-ZERO6,
ZEROA).
DACx
DAC Operation Control
where x = 1-6, corresponding to the DAC output VOUTx.
These bits are Read/Write.
Default Value: 0
DACx = 0
DACx = 1
DAC Operation Enabled (default)
DAC Operation Disabled
The DAC operation controls are used to enable and disable the DAC outputs, VOUT1 through VOUT6. When
DACx = 0, the output amplifier input is connected to the DAC output. When DACx = 1, the output amplifier
input is switched to the DC common-mode voltage (VCOM1 or VCOM2), equal to VCC/2.
®
PCM1600, PCM1601
18
REGISTER 9
R/W
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
res
res
FLT0
CLKD
CLKE
FMT2
FMT1
FMT0
Read/Write Mode Select
When R/W = 0, a Write operation is performed.
When R/W = 1, a Read operation is performed.
Default Value: 0
FLT0
Digital Filter Roll-Off Control
These bits are Read/Write.
Default Value: 000B
FLT0 = 0
FLT0 = 1
Sharp Roll-Off (default)
Slow Roll-Off
Bit FLT0 allows the user to select the digital filter roll-off that is best suited to their application. Two filter rolloff sections are available: Sharp or Slow. The filter responses for these selections are shown in the Typical
Performance Curves section of this data sheet.
CLKD
SCLKO Frequency Selection
This bit is Read/Write.
Default Value: 0
CLKD = 0
CLKD = 1
Full Rate, fSCLKO = fSCLKI (default)
Half Rate, fSCLKO = fSCLKL/2
The CLKD bit is used to determine the clock frequency at the system clock output pin, SCLKO.
CLKE
SCLKO Output Enable
This bit is Read/Write.
Default Value: 0
CLKE = 0
CLKE = 1
SCLKO Enabled (default)
SCLKO Disabled
The CLKE bit is used to enable or disable the system clock output pin, SCLKO. When SCLKO is enabled, it
will output either a full or half rate clock, based upon the setting of the CLKD bit. When SCLKO is disabled,
it is set to a high impedance state.
FMT[2:0]
Audio Interface Data Format
These bits are Read/Write.
Default Value: 000B
FMT[2:0]
000
001
010
011
100
101
110
111
Audio Data Format Selection
24-Bit Standard Format, Right-Justified
20-Bit Standard Format, Right-Justified
18-Bit Standard Format, Right-Justified
16-Bit Standard Format, Right-Justified
I2S Format, 16- to 24-bits
Left-Justified Format, 16- to 24-Bits
Reserved
Reserved
Data (default)
Data
Data
Data
The FMT[2:0] bits are used to select the data format for the serial audio interface.
®
19
PCM1600, PCM1601
REGISTER 10
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
res
res
res
DMF1
DMF0
DM56
DM34
DM12
R/W
Read/Write Mode Select
When R/W = 0, a Write operation is performed.
When R/W = 1, a Read operation is performed.
Default Value: 0
DMF[1:0]
Sampling Frequency Selection for the De-Emphasis Function
These bits are Read/Write.
Default Value: 00B
DMF[1:0]
00
01
10
11
De-Emphasis Same Rate Selection
44.1 kHz (default)
48 kHz
32 kHz
Reserved
The DMF[1:0] bits are used to select the sampling frequency used for the Digital De-Emphasis function when
it is enabled. The de-emphasis curves are shown in the Typical Performance Curves section of this data sheet.
The table below shows the available sampling frequencies.
DM12
Digital De-Emphasis Control for Channels 1 and 2
This bit is Read/Write.
Default Value: 0
DM12 = 0
DM12 = 1
De-Emphasis Disabled for Channels 1 and 2 (default)
De-Emphasis Enabled for Channels 1 and 2
The DM12 bit is used to enable or disable the De-emphasis function for VOUT1 and VOUT2, which correspond
to the Left and Right channels of the DATA1 input.
DM34
Digital De-Emphasis Control for Channels 3 and 4
This bit is Read/Write.
Default Value: 0
DM34 = 0
DM34 = 1
De-Emphasis Disabled for Channels 3 and 4 (default)
De-Emphasis Enabled for Channels 3 and 4
The DM34 bit is used to enable or disable the De-Emphasis function for VOUT3 and VOUT4, which correspond
to the Left and Right channels of the DATA2 input.
DM56
Digital De-Emphasis Control for Channels 5 and 6
This bit is Read/Write.
Default Value: 0
DM56 = 0
DM56 = 1
De-Emphasis Disabled for Channels 5 and 6 (default)
De-Emphasis Enabled for Channels 5 and 6
The DM56 bit is used to enable or disable the de-emphasis function for VOUT5 and VOUT6, which correspond
to the Left and Right channels of the DATA3 input.
®
PCM1600, PCM1601
20
REGISTER 11
R/W
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
INC
REG6
REG5
REG4
REG3
REG2
REG1
REG0
Read/Write Mode Select
When R/W = 0, a Write operation is performed.
When R/W = 1, a Read operation is performed.
Default Value: 0
INC
Auto-Increment Read Control
This bit is Read/Write.
Default Value: 0
INC = 0
INC = 1
Auto-Increment Read Disabled (default)
Auto-Increment Read Enabled
The INC bit is used to enable or disable the Auto-Increment Read feature of the Serial Control Interface. Refer
to the Serial Control Interface section of this data sheet for details regarding Auto-Increment Read operation.
REG[6:0]
Read Register Index
These bits are Read/Write.
Default Value: 01H
Bits REG[6:0] are used to set the index of the register to be read when performing a Single Register Read
operation. In the case of an Auto-Increment Read operation, bits REG[6:0] indicate the index of the last register
to be read in the in the Auto-Increment Read sequence. For example, if Registers 1 through 6 are to be read
during an Auto-Increment Read operation, bits REG[6:0] would be set to 06H.
Refer to the Serial Control Interface section of this data sheet for details regarding the Single Register and AutoIncrement Read operations.
®
21
PCM1600, PCM1601
ANALOG OUTPUTS
ZERO FLAG AND INFINITE ZERO DETECT MUTE
FUNCTIONS
The PCM1600 includes six independent output channels,
VOUT1 through VOUT6. These are unbalanced outputs, each
capable of driving 3.1Vp-p typical into a 5kΩ AC load with
VCC = +5V. The internal output amplifiers for VOUT1 through
VOUT6 are DC biased to the common-mode (or bipolar zero)
voltage, equal to VCC/2.
The PCM1600 includes circuitry for detecting an all ‘0’ data
condition for the data input pins, DATA1 through DATA3.
This includes two independent functions: Zero Output Flags
and Zero Detect Mute.
Although the flag and mute functions are independent of one
another, the zero detection mechanism is common to both
functions.
The output amplifiers include a RC continuous-time filter,
which helps to reduce the out-of-band noise energy present
at the DAC outputs due to the noise shaping characteristics
of the PCM1600’s delta-sigma D/A converters. The frequency response of this filter is shown in Figure 11. By
itself, this filter is not enough to attenuate the out-of-band
noise to an acceptable level for most applications. An
external low-pass filter is required to provide sufficient outof-band noise rejection. Further discussion of DAC postfilter circuits is provided in the Applications Information
section of this data sheet.
Zero Detect Condition
Zero Detection for each output channel is independent from
the others. If the data for a given channel remains at a ‘0’
level for 1024 sample periods (or LRCK clock periods), a
Zero Detect condition exists for the that channel.
Zero Output Flags
Given that a Zero Detect condition exists for one or more
channels, the Zero flag pins for those channels will be set to
a logic ‘1’state. There are Zero Flag pins for each channel,
ZERO1 through ZERO6 (pins 1 through 6). In addition, all
six Zero Flags are logically ANDed together and the result
provided at the ZEROA pin (pin 48), which is set to a logic
‘1’ state when all channels indicate a zero detect condition.
The Zero Flag pins can be used to operate external mute
circuits, or used as status indicators for a microcontroller,
audio signal processor, or other digitally controlled functions.
20
Level (dB)
0
–20
–40
Infinite Zero Detect Mute
–60
Infinite Zero Detect Mute is an internal logic function. The
Zero Detect Mute can be enabled or disabled using the INZD
bit of Control Register 8. The reset default is Zero Detect
Mute disabled, INZD = 0. Given that a Zero Detect Condition exists for one or more channels, the zero mute circuitry
will immediately force the corresponding DAC output(s) to
the bipolar zero level, or VCC/2. This is accomplished by
switching the input of the DAC output amplifier from the
delta-sigma modulator output to the DC common-mode
reference voltage.
–80
–100
1
10
100
1k
10k
100k
1M
10M
Log Frequency (Hz)
FIGURE 11. Output Filter Frequency Response.
VCOM1 AND VCOM2 OUTPUTS
Two unbuffered common-mode voltage output pins, VCOM1
(pin 16) and VCOM2 (pin 15), are brought out for decoupling
purposes. These pins are nominally biased to a DC voltage
level equal to VCC/2. If these pins are to be used to bias
external circuitry, a voltage follower is required for buffering purposes. Figure 12 shows an example of using the
VCOM1 and VCOM2 pins for external biasing applications.
PCM1600
PCM1601
APPLICATIONS INFORMATION
CONNECTION DIAGRAMS
A basic connection diagram is shown in Figure 13, with the
necessary power supply bypassing and decoupling components. Burr-Brown recommends using the component values
shown in Figure 13 for all designs.
A typical application diagram is shown in Figure 14. BurrBrown’s REG1117-3.3 is used to generate +3.3V for VDD
from the +5V analog power supply. Burr-Brown’s PLL1700E
is used to generate the system clock input at SCLKI, as well
as generating the clock for the audio signal processor.
4
1
3 OPA337
16
VCOM1
VBIAS ≈
VCC
2
15
VCOM2
+
10µF
The use of series resistors (22Ω to 100Ω) are recommended
for SCLKI, LRCK, BCK, DATA1, DATA2, and DATA3.
The series resistor combines with the stray PCB and device
input capacitance to form a low-pass filter which removes
high frequency noise from the digital signal, thus reducing
high frequency emission.
FIGURE 12. Biasing External Circuits Using the VCOM1
and VCOM2 Pins.
®
PCM1600, PCM1601
22
+3.3V
Analog
+3.3V
Regulator
To/From
Decoder
or
Microcontroller
C12
26
25
37
VCC3
RST
38
AGND3
SCLKI
39
To/From
Decoder
VCC4
SCLKO
40
AGND4
BCK
41
VCC5
LRCK
42
PCM1600
PCM1601
TEST
+3.3V
Analog
43
C11
+
C10
AGND5
VCC6
VDD
44
DGND
AGND6
DATA1
VCOM1
DATA2
VCOM2
DATA3
VOUT1
ZEROA
VOUT2
45
46
To/From
Decoder
47
2
3
4
5
6
7
8
9
10
11
24
23
22
21
20
19
18
17
+
C1
14
+
C2
13
+
C3
+
C4
+
C4
+
C6
+
C7
16
15
VOUT3
VOUT4
VOUT5
VOUT6
VCC
AGND
ZERO6
ZERO5
ZERO4
ZERO3
ZERO2
ZERO1
48
1
+5V Analog
AGND2
VCC0
27
VCC2
28
AGND1
29
VCC1
30
AGND0
31
NC
32
NC
MDI
33
MDO
34
MC
35
ML
36
+
C13
12
Zero
Output
Flags
Output
Low-Pass
Filters
+5V Analog
C9
C8
+
NOTE: C1 - C7, C8, C11, C13 = 10µF tantalum or aluminum electrolytic
C9, C10, C12 = 0.1µF ceramic
FIGURE 13. Basic Connection Diagram.
®
23
PCM1600, PCM1601
24
RS
RS
RS
RS
RS
RS(3)
+3.3V
Analog
FIGURE 14. Typical Application Diagram.
NOTES: (1) Serial Control and Reset functions may be provided
by DSP/Decoder GPIO pins. (2) Actual clock output used is determined
by the application. (3) RS = 22Ω to 100Ω. (4) See Applications Information
section of this data sheet for more information.
Audio DSP
or
Decoder
27MHz
Master Clock
XT1
SCKO3(2)
Buffer
C11
+
48
47
46
45
44
43
Zero Flag Outputs
for Mute Circuits,
microcontroller, or
DSP/Decoder.
C10
42
41
40
39
38
37
1
ZEROA
DATA3
DATA2
DATA1
DGND
VDD
TEST
LRCK
BCK
SCLKO
SCLKI
RST
2
3
34
4
33
5
32
31
30
6
7
0.1µF
8
AGND0
9
28
VCC
MDO
ZERO4
MDI
ZERO3
MC
ZERO2
ML
ZERO1
29
PCM1600
PCM1601
NC
ZERO5
PLL1700
35
NC
ZERO6
36
27
VCC1
10µF
10
VOUT6
µC/µP(1)
AGND1
26
+
11
VOUT5
ANALOG SECTION
25
VCC2
AGND2
VOUT2
VOUT1
VCOM2
VCOM1
AGND6
VCC6
AGND5
VCC5
AGND4
VCC4
AGND3
VCC3
0.1µF
+5V Analog
12
VOUT4
DIGITAL SECTION
VCC0
AGND
PCM1600, PCM1601
VOUT3
®
13
14
15
16
17
18
19
20
21
22
23
24
10µF
10µF
10µF
10µF
+
+
10µF
10µF
10µF
+
+
+
+
+
+
+5V Analog
Output
Low-Pass
Filters(4)
REG1117
+3.3V
+3.3V
Analog
SUB
CTR
RS
LS
RF
LF
POWER SUPPLIES AND GROUNDING
Multiple Feedback (MFB) circuit arrangement, which reduces sensitivity to passive component variations over frequency and temperature. For more information regarding
MFB active filter design, please refer to Burr-Brown Applications Bulletin AB-034, available from our web site
(www.burr-brown.com) or your local Burr-Brown sales
office.
The PCM1600 requires a +5V analog supply and a +3.3V
digital supply. The +5V supply is used to power the DAC
analog and output filter circuitry, while the +3.3V supply is
used to power the digital filter and serial interface circuitry.
For best performance, the +3.3V supply should be derived
from the +5V supply using a linear regulator, as shown in
Figure 14.
Since the overall system performance is defined by the
quality of the D/A converters and their associated analog
output circuitry, high quality audio op amps are recommended for the active filters. Burr-Brown’s OPA2134 and
OPA2353 dual op amps are shown in Figures 15 and 16, and
are recommended for use with the PCM1600 and PCM1601.
Six capacitors are required for supply bypassing, as shown
in Figure 13. These capacitors should be located as close as
possible to the PCM1600 or PCM1601 package. The 10µF
capacitors should be tantalum or aluminum electrolytic,
while the 0.1µF capacitors are ceramic (X7R type is recommended for surface-mount applications).
D/A OUTPUT FILTER CIRCUITS
Delta-sigma D/A converters utilize noise shaping techniques
to improve in-band Signal-to-Noise Ratio (SNR) performance at the expense of generating increased out-of-band
noise above the Nyquist Frequency, or fS/2. The out-of-band
noise must be low-pass filtered in order to provide the
optimal converter performance. This is accomplished by a
combination of on-chip and external low-pass filtering.
R2
R1
1
AV ≈ –
VOUT
R2
R1
R2
R1
R3
2
1
C2
3
VCOM1
C2
10µF
R4
C1
R1
+
3
OPA2134
FIGURE 15. Dual Supply Filter Circuit.
VIN
PCM1600
PCM1601
2
C2
R2
VCOM2
R3
VIN
Figures 15 and 16 show the recommended external low-pass
active filter circuits for dual and single-supply applications.
These circuits are 2nd-order Butterworth filters using the
AV ≈ –
C1
OPA337
R4
OPA2134
VOUT
To Additional
Low-Pass Filter
Circuits
FIGURE 16. Single-Supply Filter Circuit.
®
25
PCM1600, PCM1601
PCB LAYOUT GUIDELINES
Separate power supplies are recommended for the digital
and analog sections of the board. This prevents the switching
noise present on the digital supply from contaminating the
analog power supply and degrading the dynamic performance of the D/A converters. In cases where a common +5V
supply must be used for the analog and digital sections, an
inductance (RF choke, ferrite bead) should be placed between the analog and digital +5V supply connections to
avoid coupling of the digital switching noise into the analog
circuitry. Figure 18 shows the recommended approach for
single-supply applications.
A typical PCB floor plan for the PCM1600 and PCM1601 is
shown in Figure 17. A ground plane is recommended, with
the analog and digital sections being isolated from one
another using a split or cut in the circuit board. The PCM1600
or PCM1601 should be oriented with the digital I/O pins
facing the ground plane split/cut to allow for short, direct
connections to the digital audio interface and control signals
originating from the digital section of the board.
Digital Power
+VD
Analog Power
DGND
AGND +5VA
+VS –VS
REG
VCC
VDD
Digital Logic
and
Audio
Processor
DGND
PCM1600
PCM1601
Output
Circuits
Digital
Ground
AGND
DIGITAL SECTION
Analog
Ground
ANALOG SECTION
Return Path for Digital Signals
FIGURE 17. Recommended PCB Layout.
Power Supplies
RF Choke or Ferrite Bead
+5V
AGND
+VS –VS
REG
VCC
VDD
VDD
DGND
Output
Circuits
PCM1600
PCM1601
AGND
Common
Ground
DIGITAL SECTION
ANALOG SECTION
FIGURE 18. Single-Supply PCB Layout.
®
PCM1600, PCM1601
26
THEORY OF OPERATION
KEY PERFORMANCE PARAMETERS AND MEASUREMENT
The delta-sigma section of PCM1600 is based on a 8-level
amplitude quantizer and a 4th-order noise shaper. This
section converts the oversampled input data to 8-level deltasigma format.
This section provides information on how to measure key
dynamic performance parameters for the PCM1600 and
PCM1601. In all cases, an Audio Precision System Two
Cascade or equivalent audio measurement system is utilized
to perform the testing.
A block diagram of the 8-level delta-sigma modulator is
shown in Figure 19. This 8-level delta-sigma modulator has
the advantage of stability and clock jitter sensitivity over the
typical one-bit (2 level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the internal 8x interpolation filter is 64fS for all
system clock combinations (256/384/512/768fS).
TOTAL HARMONIC DISTORTION + NOISE
Total Harmonic Distortion + Noise (THD+N) is a significant
figure of merit for audio D/A converters, since it takes into
account both harmonic distortion and all noise sources
within a specified measurement bandwidth. The true rms
value of the distortion and noise is referred to as THD+N.
The theoretical quantization noise performance of the
8-level delta-sigma modulator is shown in Figure 20. The
enhanced multi-level delta-sigma architecture also has advantages for input clock jitter sensitivity due to the multilevel quantizer, with the simulated jitter sensitivity shown in
Figure 21.
For the PCM1600 and PCM1601 D/A converters, THD+N is
measured with a full scale, 1kHz digital sine wave as the test
stimulus at the input of the DAC. The digital generator is set
–
+
8fS
Z–1
+
Z–1
+
Z–1
+
Z–1
+
+
8-Level Quantizer
64fS
FIGURE 19. Eight-Level Delta-Sigma Modulator.
125
–20
120
–40
115
Dynamic Range (dB)
Amplitude (dB)
CLOCK JITTER
0
–60
–80
–100
–120
110
105
100
95
–140
90
–160
85
80
–180
0
1
2
3
4
5
6
7
0
8
100
200
300
400
500
600
Jitter (ps)
Frequency (fS)
FIGURE 20. Quantization Noise Spectrum.
FIGURE 21. Jitter Sensitivity.
®
27
PCM1600, PCM1601
The measurement setup for the dynamic range measurement
is shown in Figure 23, and is similar to the THD+N test
setup discussed previously. The differences include the band
limit filter selection, the additional A-Weighting filter, and
the –60dBFS input level.
to 24-bit audio word length and a sampling frequency of
44.1kHz, or 96kHz. The digital generator output is taken
from the unbalanced S/PDIF connector of the measurement
system. The S/PDIF data is transmitted via coaxial cable to
the digital audio receiver on the DEM-DAI1600 demo board.
The receiver is then configured to output 24-bit data in either
I2S or left-justified data format. The DAC audio interface
format is programmed to match the receiver output format.
The analog output is then taken from the DAC post filter and
connected to the analog analyzer input of the measurment
system. The analog input is band limited using filters resident in the analyzer. The resulting THD+N is measured by
the analyzer and displayed by the measurement system.
IDLE CHANNEL SIGNAL-TO-NOISE RATIO
The SNR test provides a measure of the noise floor of the
D/A converter. The input to the D/A is all 0’s data, and the
D/A converter’s Infinite Zero Detect Mute function must
be disabled (default condition at power up for the PCM1600,
PCM1601). This ensures that the delta-sigma modulator
output is connected to the output amplifier circuit so that
idle tones (if present) can be observed and effect the SNR
measurement. The dither function of the digital generator
must also be disabled to ensure an all ‘0’s data stream at the
input of the D/A converter.
DYNAMIC RANGE
Dynamic range is specified as A-Weighted, THD+N measured with a –60dBFS, 1kHz digital sine wave stimulus at
the input of the D/A converter. This measurment is designed
to give a good indicator of how the DAC will perform given
a low-level input signal.
The measurement setup for SNR is identical to that used for
dynamic range, with the exception of the input signal level.
(see the notes provided in Figure 23).
Evaluation Board
DEM-DAI1600
S/PDIF
Receiver
PCM1600
PCM1601
2nd-Order
Low-Pass
Filter
f–3dB = 54kHz
Analyzer
and
Display
Digital
Generator
S/PDIF
Output
100% Full Scale
24-Bit, 1kHz
Sine Wave
NOTES: (1) There is little difference
in measured THD+N when using the
various settings for these filters.
(2) Required for THD+N test.
RMS Mode
Band Limit
Notch Filter
22Hz(1)
HPF =
fC = 1kHz
LPF = 30kHz(1)
Option = 20kHz Apogee Filter(2)
FIGURE 22. Test Setup for THD+N Measurements.
Evaluation Board
DEM-DAI1600
S/PDIF
Receiver
PCM1600(1)
PCM1601
2nd-Order
Low-Pass
Filter
f–3dB = 54kHz
S/PDIF
Output
NOTES: (1) Infinite Zero Detect Mute disabled.
(2) Results without A-Weighting will be
approximately 3dB worse.
Digital
Generator
0% Full Scale,
Dither Off (SNR)
–60dBFS,
1kHz Sine Wave
(Dynamic Range)
Analyzer
and
Display
A-Weight
Filter(1)
RMS Mode
FIGURE 23. Test Set-Up for Dynamic Range and SNR Meeasurements.
®
PCM1600, PCM1601
28
Band Limit
HPF = 22Hz
LPF = 22kHz
Option = A-Weighting(2)
Notch Filter
fC = 1kHz
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  2000, Texas Instruments Incorporated