PCM1738 PC M1 738 www.ti.com 24-Bit, 192kHz Sampling, Advanced Segment, Audio-Stereo DIGITAL-TO-ANALOG CONVERTER APPLICATIONS FEATURES 24-BIT RESOLUTION ANALOG PERFORMANCE (VCC = +5V): Dynamic Range: 117dB typ SNR: 117dB typ THD+N: 0.0004% typ Full-Scale Output: 2.2Vrms (at post amp) DIFFERENTIAL CURRENT OUTPUT: 2.48mA SAMPLING FREQUENCY: 10kHz to 200kHz SYSTEM CLOCK: 128, 192, 256, 384, 512, or 768fS with Auto Detect ACCEPTS 16-, 20-, AND 24-BIT AUDIO DATA DATA FORMATS: Standard, I2S, and LeftJustified 8x OVERSAMPLING DIGITAL FILTER: Stopband Attenuation: –82dB Passband Ripple: 0.002dB OPTIONAL INTERFACE TO EXTERNAL DIGITAL FILTER AVAILABLE OPTIONAL INTERFACE TO DSD DECODER FOR SACD PLAYBACK USER-PROGRAMMABLE MODE CONTROLS: Digital Attenuation: 0dB to –120dB, 0.5dB/Step Digital De-Emphasis Digital Filter Roll-Off: Sharp or Slow Soft Mute Zero Detect Mute Zero Flags for Each Output DUAL-SUPPLY OPERATION: +5V Analog, +3.3V Digital AV RECEIVERS DVD MOVIE PLAYERS SACD PLAYERS HDTV RECEIVERS CAR AUDIO SYSTEMS DIGITAL MULTI-TRACK RECORDERS OTHER MULTICHANNEL AUDIO SYSTEMS DESCRIPTION The PCM1738 is a CMOS, monolithic, Integrated Circuit (IC) that includes stereo Digital-to-Analog Converters (DACs) and support circuitry in a small SSOP-28 package. The data converters utilize a newly developed advanced segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1738 provides balanced current outputs, allowing the user to optimize analog performance externally, and accepts industry standard audio data formats with 16- to 24-bit data, providing easy interfacing to audio DSP and decoder chips. Sampling rates up to 200kHz are supported. The PCM1738 also has two optional modes of operation: an external digitalfilter mode (for use with the DF1704, DF1706, and PMD200), and a DSD decoder interface for SACD playback applications. A full set of user-programmable functions are accessible through a 4-wire serial control port that supports register write and read functions. 5V TOLERANT DIGITAL INPUTS SMALL SSOP-28 PACKAGE Copyright © 2000, Texas Instruments Incorporated SBAS174B Printed in U.S.A. February, 2002 SPECIFICATIONS All specifications at TA = +25 C, VDD = +3.3V, VCC = +5V, SCKI = 256fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted. PCM1738E PARAMETER CONDITIONS MIN RESOLUTION DYNAMIC PERFORMANCE(2) THD+N at VOUT = 0dB Dynamic Range Signal-to-Noise Ratio Channel Separation Level Linearity Error DC ACCURACY VCOM2 Voltage VCOM2 Output Current Gain Error Gain Mismatch, Channel-to-Channel Bipolar Zero Error DSD MODE DYNAMIC PERFORMANCE(1) THD+N at Full Scale Dynamic Range Signal-to-Noise Ratio ANALOG OUTPUT Output Current DSD Mode Output Current Center Current DIGITAL-FILTER PERFORMANCE Filter Characteristics 1, Sharp Roll-Off Passband Passband Stopband Passband Ripple Stopband Attenuation Stopband Attenuation Filter Characteristics 2, Slow Roll-Off Passband Passband Stopband Passband Ripple Stopband Attenuation Delay Time De-Emphasis Error 2 MAX 24 DATA FORMAT Audio Data Interface Formats Audio Data Bit Length Audio Data Format Sampling Frequency (fS) System Clock Frequency DIGITAL INPUT/OUTPUT Logic Family Input Logic Level VIH VIL Input Logic Current IIH IIL Output Logic Level VOH VOL High Impedance Output Logic Current(1) IOHZ IOLZ TYP UNITS Bits Standard, I2S, Left-Justified 16-, 20-, 24-Bits Selectable MSB-First, Binary Two’s Complement 10 200 128, 192, 256, 384, 512, 768fS kHz TTL-Compatible 2.0 0.8 VIN = VDD VIN = 0V IOH = –2mA IOL = +2mA 10 –10 2.4 1.0 VOUT = VDD VOUT = VDD fS = 44.1kHz fS = 96kHz fS = 192kHz EIAJ, A-Weighted, fS = 44.1kHz A-Weighted, fS = 96kHz A-Weighted, fS = 192kHz EIAJ, A-Weighted, fS = 44.1kHz A-Weighted, fS = 96kHz A-Weighted, fS = 192kHz fS = 44.1kHz fS = 96kHz fS = 192kHz VOUT = –110dB 5 5 114 114 110 0.0004 0.0006 0.0012 117 117 117 117 117 117 115 113 111 1.0 0.0008 VDC VDC A A VDC VDC A A % % % dB dB dB dB dB dB dB dB dB dB at Bipolar Zero 2.45 100 2.0 0.5 0.5 V A % of FSR % of FSR % of FSR 44.1kHz, 64fS 2.48mAp-p –60dB, EIAJ, A-Weighted EIAJ, A-Weighted 0.0004 117 117 % dB dB Full Scale (0dB) 100% OUTPUT Bipolar Zero Input 2.48 2.48 0 mAp-p mAp-p mAp-p Delta VCOM2 < 5% 0.002dB –3dB 0.454fS 0.487fS 0.546fS 0.002 Stopband = 0.546fS Stopband = 0.567fS –75 –82 0.04dB –3dB 0.274fS 0.454fS 0.732fS 0.002 Stopband = 0.732fS –82 29/fS 0.1 Hz Hz Hz dB dB dB Hz Hz Hz dB dB sec dB PCM1738 SBAS174B SPECIFICATIONS (Cont.) All specifications at TA = +25 C, VDD = +3.3V, VCC = +5V, SCKI = 256fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted. PCM1738E PARAMETER CONDITIONS POWER SUPPLY REQUIREMENTS Voltage Range, VDD VCC Supply Current, IDD(4) TYP MAX UNITS +3.0 +4.75 +3.3 +5.0 7.0 15.0 30.0 33.0 34.5 36.5 188 222 282 +3.6 +5.25 9.8 VDC VDC mA mA mA mA mA mA mW mW mW VDD = 3.3V, fS = 44.1kHz VDD = 3.3V, fS = 96kHz VDD = 3.3V, fS = 192kHz VCC = 5.0V, fS = 44.1kHz VCC = 5.0V, fS = 96kHz VCC = 5.0V, fS = 192kHz VDD = 3.3V, VCC = 5.0V, fS = 44.1kHz VDD = 3.3V, VCC = 5.0V, fS = 96kHz VDD = 3.3V, VCC = 5.0V, fS = 192kHz ICC Power Dissipation TEMPERATURE RANGE Operation Temperature Thermal Resistance MIN 46.2 –25 +85 SSOP-28 JA 263 115 C C/W NOTES: (1) Pin 11 (MDO). (2) Analog performance specifications are measured by an Audio Precision System II, using an averaging mode. At 44.1kHz operation, bandwidth measurement is limited with 20kHz. At 96kHz and 192kHz, bandwidth measurement is limited with 40kHz. (3) Theoretical performance in DSD modulation index of 100%. It's performance is equivalent to the PCM mode. (4) SCKO is disabled. Input is Bipolar Zero Data. ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Power Supply Voltage, VCC1, VCC2, and VCC3 .............................................. +6.5V VDD ............................................................................. +4.0V Supply Voltage Differences Among VCC1, VCC2, and VCC3 .......................... 0.1V Ground Voltage Differences Among AGND1, AGND2, and AGND3 ................................................................................................. 0.1V Digital Input Voltage, LRCK, DATA, BCK, SCKI, MDI, MC, and MUTE ............................................................................... –0.3V to 6.5V Digital Input Voltage, ZEROL, ZEROR, SCKO, and MDO ........................................................................... –3.0V to (VDD + 0.3V) Analog Input Voltage, IOUTR–, IOUTR+, VCOM1, VCOM2, VCOM3, IREF, IOUTL+, and IOUTL– ................ –0.3V to (VCC, VCC2 + 0.3V) Input Current (except power supply) ............................................................ 10mA Ambient Temperature Under Bias ................................................ –40 C to +125 C Storage Temperature .................................................................... –55 C to +150 C Junction Temperature .................................................................................. +150 C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER PCM1738E SSOP-28 324 –25 C to +85 C PCM1738E " " " " " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA PCM1738E PCM1738E/2K Rails Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “PCM1738E/2K” will yield a single 2000-piece Tape and Reel. PCM1738 SBAS174B 3 BLOCK DIAGRAM LRCK Current Segment DAC Input DATA I/F IOUTL+ IOUTL– BCK 8x Oversampling Digital Filter and Function Control RST MUTE CS Function MC Control VCOM2 Advanced Segment DAC Modulator Bias IV and Filter IREF and VREF VCOM1 VCOM3 IV and Filter MDI Current Segment DAC I/F IOUTR– IOUTR+ MDO System Clock AGND2 AGND1 VCC3 VCC2 VCC1 DGND VDD ZEROR SCKO Power Supply ZERO Detect ZEROL System Clock Manager SCKI PIN ASSIGNMENTS PIN CONFIGURATION TOP VIEW SSOP RST 1 28 VCC3 ZEROL 2 27 AGND2 ZEROR 3 26 IOUTL– LRCK 4 25 IOUTL+ DATA 5 24 VCC2 BCK 6 23 VCC1 SCKI 7 22 VCOM3 PCM1738 DGND 8 21 IREF VDD 9 20 VCOM2 SCKO 10 19 VCOM1 MDO 11 18 AGND1 MDI 12 17 IOUTR+ MC 13 16 IOUTR– CS 14 15 MUTE PIN NAME TYPE FUNCTION 1 2 3 4 RST ZEROL ZEROR LRCK IN OUT OUT IN 5 DATA IN 6 7 BCK SCKI IN IN 8 9 10 11 12 13 14 15 DGND VDD SCKO MDO MDI MC CS MUTE – – OUT OUT IN IN IN IN 16 17 18 19 20 21 IOUTR– IOUTR+ AGND1 VCOM1 VCOM2 IREF OUT OUT – – – – 22 23 24 25 26 27 28 VCOM3 VCC1 VCC2 IOUTL+ IOUTL– AGND2 VCC3 – – – OUT OUT – – Reset(1) Zero Flag for L-Channel. Zero Flag for R-Channel. Left/Right clock (fS) input for normal operation.(1) WDCK clock input in external DF mode. Connected to GND in DSD mode. Serial Audio data input for normal operation.(1) L-channel audio data input for external DF and DSD modes. Bit Clock. Input. Connected to GND for DSD mode.(1) System Clock Input for normal operation.(1) BCK (64fS) clock input for DSD mode. Digital Ground Digital Supply, +3.3V System Clock Output Serial data output for function control register.(2) Serial data input for function control register.(1) Shift Clock for function control register.(1) Mode Control chip select and latch signal.(1) Analog output mute control for normal operation.(1) R-channel audio data input for external DF and DSD modes. R-Channel Analog Current Output – R-Channel Analog Current Output + Analog Ground Internal Bias Decoupling Pin Common Voltage for I/V Output current reference bias pin. Connect 16k resistor to GND. Internal Bias Decoupling Pin Analog Supply, +5.0V Analog Supply, +5.0V L-Channel Analog Current Output + L-Channel Analog Current Output – Analog Ground Analog Power Supply, +5.0V NOTES: (1) Schmitt-trigger input, 5V tolerant. (2) Tristate output. 4 PCM1738 SBAS174B TYPICAL PERFORMANCE CURVES All specifications at TA = +25 C, VDD = +3.3V, VCC = +5V, SCKI = 256fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted. DIGITAL FILTER Digital Filter (De-Emphasis Off, fS = 44.1kHz) FREQUENCY RESPONSE (Sharp Roll-Off) PASSBAND RIPPLE (Sharp Roll-Off) 0 0.003 –20 0.002 –60 0.001 Amplitude (dB) Amplitude (dB) –40 –80 –100 –120 0 –0.001 –0.002 –140 –160 –0.003 0 1 2 3 4 0 0.1 0.2 Frequency (x fS) 0.3 0.4 0.5 Frequency (x fS) TRANSITION CHARACTERISTICS (Slow Roll-Off) FREQUENCY RESPONSE (Slow Roll-Off) 0 0 –2 –20 –4 –6 Amplitude (dB) Amplitude (dB) –40 –60 –80 –100 –8 –10 –12 –14 –16 –120 –18 –140 –20 0 1 2 3 0 4 0.1 0.2 0.3 0.4 0.5 0.6 Frequency (x fS) Frequency (x fS) De-Emphasis Error DE-EMPHASIS ERROR (fS = 32kHz) 0.5 –1.0 0.4 –2.0 0.3 –3.0 0.2 –4.0 0.1 Error (dB) Level (dB) DE-EMPHASIS (fS = 32kHz) 0.0 –5.0 –6.0 0.0 –0.1 –7.0 –0.2 –8.0 –0.3 –9.0 –0.4 –10.0 –0.5 0 2 4 6 8 Frequency (kHz) PCM1738 SBAS174B 10 12 14 0 2 4 6 8 10 12 14 Frequency (kHz) 5 TYPICAL PERFORMANCE CURVES (Cont.) All specifications at TA = +25 C, VDD = +3.3V, VCC = +5V, SCKI = 256fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted. De-Emphasis Error (Cont.) DE-EMPHASIS ERROR (fS = 44.1kHz) 0.5 –1.0 0.4 –2.0 0.3 –3.0 0.2 –4.0 0.1 Error (dB) Level (dB) DE-EMPHASIS (fS = 44.1kHz) 0.0 –5.0 –6.0 0.0 –0.1 –7.0 –0.2 –8.0 –0.3 –9.0 –0.4 –10.0 –0.5 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 Frequency (kHz) DE-EMPHASIS (fS = 48kHz) 10 12 14 16 18 20 18 22 DE-EMPHASIS ERROR (fS = 48kHz) 0.0 0.5 –1.0 0.4 –2.0 0.3 –3.0 0.2 –4.0 0.1 Error (dB) Level (dB) 8 Frequency (kHz) –5.0 –6.0 0.0 –0.1 –7.0 –0.2 –8.0 –0.3 –9.0 –0.4 –10.0 –0.5 0 2 4 6 8 10 12 14 16 18 22 0 2 4 6 Frequency (kHz) 8 10 12 14 16 Frequency (kHz) ANALOG DYNAMIC PERFORMANCE All specifications at TA = +25 C, VDD = +3.3V, VCC = +5V, SCKI = 256fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted. Analog Dynamic Performance THD+N/fS vs TEMPERATURE THD+N/fS vs VCC 0.0020 0.0020 44.1 kHz 96kHz 44.1 kHz 96kHz 0.0015 THD+N/fS (%) THD+N/fS (%) 0.0015 0.0010 0.0005 0.0005 0 4.50 0 4.75 5.00 VCC (V) 6 0.0010 5.25 5.50 –40 –20 0 20 40 60 80 100 Temperature ( C) PCM1738 SBAS174B TYPICAL PERFORMANCE CURVES (Cont.) All specifications at TA = +25 C, VDD = +3.3V, VCC = +5V, SCKI = 256fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted. Analog Dynamic Performance (Cont.) DYNAMIC RANGE vs TEMPERATURE 120 119 119 118 118 Dynamic Range (dB) Dynamic Range (dB) DYNAMIC RANGE vs VCC 120 117 116 115 44.1 kHz 96kHz 114 113 112 4.50 117 116 115 44.1 kHz 96kHz 114 113 112 4.75 5.00 5.25 5.50 –40 –20 0 VCC (V) 119 119 118 118 117 117 116 115 44.1 kHz 96kHz 115 44.1 kHz 96kHz 112 4.75 5.00 5.25 5.50 –40 –20 0 40 60 80 100 CHANNEL SEPARATION vs TEMPERATURE 118 44.1 kHz 96kHz 44.1 kHz 96kHz 117 Channel Separation (dB) 117 Channel Separation (dB) 20 Temperature ( C) CHANNEL SEPARATION vs VCC 116 115 114 113 112 111 116 115 114 113 112 111 110 4.75 5.00 VCC (V) SBAS174B 100 113 118 PCM1738 80 116 VCC (V) 110 4.50 60 114 113 112 4.50 40 SIGNAL-TO-NOISE RATIO vs TEMPERATURE 120 SNR (dB) SNR (dB) SIGNAL-TO-NOISE RATIO vs VCC 120 114 20 Temperature ( C) 5.25 5.50 –40 –20 0 20 40 60 80 100 Temperature ( C) 7 TYPICAL PERFORMANCE CURVES (Cont.) All specifications at TA = +25 C, VDD = +3.3V, VCC = +5V, SCKI = 256fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted. Analog Dynamic Performance (Cont.) –60dB OUTPUT SPECTRUM (BW = 100kHz) 0 –20 –20 –40 –40 Output Level (dB) Output Level (dB) –60dB OUTPUT SPECTRUM (BW = 20kHz) 0 –60 –80 –100 –120 –60 –80 –100 –120 –140 –140 –160 –160 0 5k 10k 15k 0 20k 20k 40k THD+N vs LEVEL (PCM MODE) 100k –20 0 100 44.1 kHz 96kHz 10 10 1 THD+N (%) 1 THD+N (%) 80k THD+N vs LEVEL (DSD MODE) 100 0.1 0.01 0.001 0.0001 –100 60k Frequency (Hz) Frequency (Hz) 0.1 0.01 0.001 –80 –60 Level ( –40 –20 0.0001 –100 0 –80 –60 ?) Level ( –40 ?) –60dB OUTPUT SPECTRUM ON DSD MODE 0 –20 Output Level (dB) –40 –60 –80 –100 –120 –140 –160 0 5k 10k 15k 20k Frequency (Hz) 8 PCM1738 SBAS174B ANALOG FIR FILTER PERFORMANCE FOR DSD MODE All specifications at TA = +25 C, VDD = +3.3V, VCC = +5V, SCKI = 11.2896MHz (44.1kHz • 256fS), and 50% modulation DSD data input, unless otherwise noted. DSD FILTER 1 DSD FILTER 1 0 0 –1 –20 Gain (dB) Gain (dB) –2 –3 –40 –60 –4 –80 –5 –6 –100 0 50 100 150 200 0 Frequency (kHz) 500 1000 1500 Frequency (kHz) DSD FILTER 2 DSD FILTER 2 0 0 –1 –20 Gain (dB) Gain (dB) –2 –3 –40 –60 –4 –80 –5 –6 –100 0 50 100 150 200 0 Frequency (kHz) 500 1000 1500 Frequency (kHz) DSD FILTER 3 DSD FILTER 3 0 0 –1 –20 Gain (dB) Gain (dB) –2 –3 –40 –60 –4 –80 –5 –6 –100 0 50 100 Frequency (kHz) PCM1738 SBAS174B 150 200 0 500 1000 1500 Frequency (kHz) 9 ANALOG FIR FILTER PERFORMANCE FOR DSD MODE (Cont.) All specifications at TA = +25 C, VDD = +3.3V, VCC = +5V, SCKI = 11.2896MHz (44.1kHz • 256fS), and 50% modulation DSD data input, unless otherwise noted. DSD FILTER 4 DSD FILTER 4 0 0 –1 –20 Gain (dB) Gain (dB) –2 –3 –40 –60 –4 –80 –5 –6 –100 0 50 100 Frequency (kHz) 10 150 200 0 500 1000 1500 Frequency (kHz) PCM1738 SBAS174B SYSTEM CLOCK AND RESET FUNCTIONS POWER-ON AND EXTERNAL RESET FUNCTIONS The PCM1738 includes a power-on reset function (see Figure 2). The system clock input at SCKI should be active for at least one clock period prior to VDD = 2.0V. With the system clock active, and VDD > 2.0V, the power-on reset function will be enabled. The initialization sequence requires 1024 system clocks from the time VDD > 2.0V. After the initialization period, the PCM1738 will be set to its reset default state, as described in the Mode Control Register section of this data sheet. The PCM1738 also includes an external reset capability using the RST input (pin 1). This allows an external controller or master reset circuit to force the PCM1738 to initialize to its reset default state. See Figure 3 for external reset operation and timing. The RST pin is set to a logic “0” for a minimum of 20ns. The RST pin is then set to a logic “1” state that starts the initialization sequence that requires 1024 system clock periods. After the initialization sequence is complete, the PCM1738 will be set to its reset default state, as described in the Mode Control Register section of this data sheet. The external reset is especially useful in applications where there is a delay between the PCM1738 power-up and system clock activation. In this case, the RST pin should be held at a logic “0” level until the system clock has been activated. The RST pin may then be set to a logic “1” state to start the initialization sequence. SYSTEM CLOCK INPUT The PCM1738 requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCKI input (pin 7). The PCM1738 has a system-clock detection circuit that automatically senses if the system clock is operating at 128fS to 768fS. Table I shows examples of system-clock frequencies for common audio sampling rates. Figure 1 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. The PLL1700 multiclock generator is an excellent choice for providing the PCM1738 system clock. SYSTEM CLOCK OUTPUT A buffered version of the system clock input is available at the SCKO output (pin 10). SCKO can operate at either full (fSCKI) or half (fSCKI/2) rate. The SCKO output frequency may be programmed using the CLKD bit of Control Register 19. The SCKO output pin can also be enabled or disabled using the CLKE bit of Control Register 19. The default is SCKO enabled. SYSTEM CLOCK FREQUENCY (fSCLK) (MHz) SAMPLING FREQUENCY 128fS 192fS 256fS 384fS 512fS 768fS 32kHz 44.1kHz 48kHz 96kHz 192kHz 4.0960 5.6488 6.1440 12.2880 24.5760 6.1440 8.4672 9.2160 18.4320 36.8640 8.1920 11.2896 12.2880 24.5760 49.1520 12.2880 16.9344 18.4320 36.8640 73.7280 16.3840 22.5792 24.5760 49.1520 See Note (1) 24.5760 33.8688 36.8640 73.7280 See Note (1) NOTE: (1) This system clock is not supported for the given sampling frequency. TABLE I. System Clock Rates for Common Audio Sampling Frequencies. tSCKH “H” 2.0V “L” 0.8V System Clock tSCKL System clock pulse cycle time(1) System Clock Pulse Width HIGH tSCKH: 5ns (min) System Clock Pulse Width LOW tSCKL: 5ns (min) FIGURE 1. System Clock Input Timing. PCM1738 SBAS174B 11 2.4V/max VDD 2.0V/typ 1.6V/min Reset Reset Removal Internal Reset 1024 System Clock Periods System Clock FIGURE 2. Power-On Reset Timing. RST (pin 1) 50% of VDD tRST Reset Removal Reset Internal Reset 1024 System Clocks System Clock Reset Pulse Width LOW tRST 20ns (min) FIGURE 3. Audio Data Input Formats. AUDIO DATA INTERFACE AUDIO SERIAL INTERFACE The audio serial interface for the PCM1738 is comprised of a 3-wire synchronous serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit clock, used to clock the serial data present on DATA into the audio interface’s serial shift register. Serial data is clocked into the PCM1738 on the rising edge of BCK. LRCK is the serial audio left/right word clock, used to latch serial data into the serial audio interface’s internal registers. LRCK should be synchronous to the system clock. In the event these clocks are not synchronized, the PCM1738 can compensate for the phase difference internally. If the phase difference between LRCK and SCKI is greater than six bit clocks (BCK), the synchronization is performed internally. While the synchronization is processing, the analog output is 12 forced to the bipolar zero level. The synchronization typically occurs in less than one cycle of LRCK. Ideally, it is recommended that LRCK and BCK be derived from the system clock input or output, SCKI or SCKO. The left/right clock (LRCK) is operated at the sampling frequency, fS. AUDIO DATA FORMATS AND TIMING The PCM1738 supports industry-standard audio data formats, including Standard Right-Justified, I2S, and Left-Justified. The data formats are shown in Figure 4. Data formats are selected using the format bits, FMT [2:0], in Control Register 18. The default data format is 16-bit Standard. All formats require Binary Two’s Complement, MSB-first audio data. Figure 5 shows a detailed timing diagram for the serial audio interface. PCM1738 SBAS174B (1) Standard Data Format (Right Justified): L-Channel = HIGH, R-Channel = LOW 1/fS LRCK R-Channel L-Channel BCK Audio Data Word = 16 Bit DATA 14 15 16 1 MSB Audio Data Word = 20 Bit DATA 2 18 19 20 1 15 16 1 2 15 16 LSB 2 1 19 20 MSB 2 19 20 LSB Audio Data Word = 24 Bit DATA 22 23 24 1 2 1 23 24 MSB 2 23 24 LSB (2) Left-Justified Data Format: L-Channel = HIGH, R-Channel = LOW 1/fS L-Channel LRCK R-Channel BCK Audio Data Word = 24 Bit DATA 1 24 2 MSB LSB 1 24 2 MSB 1 2 LSB (3) I2S Data Format: L-Channel = LOW, R-Channel = HIGH 1/fS LRCK L-Channel R-Channel BCK Audio Data Word = 16 Bit DATA 1 2 MSB 16 1 2 1 2 16 1 2 1 2 LSB Audio Data Word = 24 Bit DATA 1 2 MSB 24 24 LSB FIGURE 4. Audio Data Input Formats. PCM1738 SBAS174B 13 LRCK 50% of VDD tBCH tBCL tLB BCK 50% of VDD tBCY tBL 50% of VDD DATA tDH tDS SYMBOL tBCY tBCL tBCH tBL tLB tDS tDH --- PARAMETER MIN BCK Pulse Cycle Time BCK High Level Time BCK Low Level Time BCK Rising Edge to LRCK Edge LRCK Falling Edge to BCK Rising Edge DATA Set Up Time DATA Hold Time LRCK Clock Duty 70 30 30 10 10 10 10 50% UNITS ns ns ns ns ns ns ns 2-Bit Clock FIGURE 5. Audio Interface Timing. CS MC MDI W/R MDO A6 A5 A4 A3 A2 A1 high impedance A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 When Read mode is instructed NOTE: B15 is used for the selection of Write or Read. Setting W/R = 0 indicates a Write, while W/R = 1 indicates a Read. B14 to B8 are used for register address. B7 to B0 are used for register data. FIGURE 6. Serial Control Format. EXTERNAL DIGITAL FILTER INTERFACE AND TIMING The PCM1738 supports an external digital-filter interface comprised of a 4-wire synchronous serial port that allows the use of an external digital filter. External filters include the DF1704 and DF1706 from Texas Instruments, the Pacific Microsonics PMD200, or a programmable digital signal processor. The 4-wire interface includes WCK as the word clock, BCK as the bit clock, DATAL as the L-channel data, and DATAR as the R-channel data. The external digital-filter interface is selected using the DFTH bit of Control Register 20, which functions to bypass the internal digital-filter portion of the PCM1738. The 4-wire serial port is assigned to WDCK (pin 4), BCK (pin 6), DATAL (pin 5), and DATAR (pin 15). 14 DSD (DIRECT STREAM DIGITAL) FORMAT INTERFACE AND TIMING The PCM1738 supports a DSD format interface operation that includes out-of-band noise filtering using an internal Analog FIR filter. For DSD operation, pin 7 is redefined as BCK, which operates at 64 x 44.1kHz; pin 5 is redefined as DATAL (left-channel audio data), and pin 15 becomes DATAR (right-channel audio data). Pins 4 and 6 must be forced LOW in DSD mode. This configuration allows for direct interface to a DSD decoder for SACD applications. Detailed information for the DSD mode is provided in the DSD Mode Operation section of this data sheet. PCM1738 SBAS174B FUNCTIONAL DESCRIPTIONS ZERO DETECT When the PCM1738 detects that the audio input data in the L-channel or R-channel is continuously zero for 1024fS, the PCM1738 sets ZEROL (pin 2) or ZEROR (pin 3) to HIGH. Setting the INZD bit of mode register 19 can set both analog outputs to the bipolar zero level when the input data of both channels are zero. SOFT MUTE The PCM1738 supports mute operation by both hardware and software control. When MUTE (pin 15) is set to HIGH, both analog outputs are turned to the bipolar zero level. When the MUTE bit in mode register 18 is set to “1”, both analog outputs are also turned to the bipolar zero level. The speed to turn to the bipolar zero level is set by the ATS0 and ATS1 bits in mode register 19. SERIAL CONTROL INTERFACE The serial control interface is a 4-wire synchronous serial port that operates asynchronously to the serial audio interface and the system clock (SCKI). The serial control interface is utilized to program the on-chip mode registers. The control interface includes MDO (pin 11), MDI (pin 12), MC (pin 13), and CS (pin 14). MDO is the serial data output, used to read back the values of the mode registers; MDI is the serial data input, used to program the mode registers; MC is the serial bit clock, used to shift data in and out of the control port; and CS is the mode control enable, used to enable the internal mode register access. Figures 6 and 7 show the format and timing for the serial control interface. tMHH 50% of VDD ML tMCH tMLS tMCL tMLH 50% of VDD MC tMCY LSB MD 50% of VDD tMOS SYMBOL tMCY tMCL tMCH tMHH tMLS tMLH tMDH tMDS tMOS tMDS tMDH PARAMETER MIN MC Pulse Cycle Time MC Low Level Time MC High Level Time CS High Level Time CS Falling Edge to MC Rising Edge CS Hold Time(1) MDI Hold Time MDI Set-Up Time MC Falling Edge to MDO Stable 100 40 40 80 15 15 15 15 MAX UNITS 30 ns ns ns ns ns ns ns ns ns NOTE: (1) MC rising edge for LSB to CS rising edge. FIGURE 7. Control Interface Timing. PCM1738 SBAS174B 15 MODE CONTROL REGISTERS User-Programmable Mode Controls The PCM1738 includes a number of user-programmable functions that are accessed via mode control registers. The registers are programmed using the Serial Control Interface that was previously discussed in this data sheet. Table II lists the available mode control functions, along with their reset default conditions and associated register index. FUNCTION Register Map The mode control register map is shown in Table III. Each register includes a W/R bit that indicates whether a register read (W/R = 1) or write (W/R = 0) operation is performed. DEFAULT REGISTER BIT 0dB Attenuation Disabled Register 16 for L-Channel Register 17 for R-Channel 18 ATL[7:0] ATR[7:0] ATLD x1fS 19 ATS[1:0] Mute Disabled 18 MUTE Disabled 19 INZD 16-Bit Standard Format 18 FMT[2:0] De-Emphasis Disabled 18 DME De-Emphasis Disabled 18 DMF[1:0] Sharp Roll-Off 19 FLT Normal 19 REV DAC Operation Enabled 19 OPE Output Enabled 19 CLKE SCKI 19 CLKD Normal Operation 20 SRST Normal Operation 20 MRST DF Enabled 20 DFTH x64fS 20 OS[1:0] Third Order 20 DSOS Stereo 20 MONO L-Channel 20 CHSL Not Zero = 0 Zero Detected = 1 21 21 ZFGL for L-Channel ZFGR for R-Channel FUNCTIONS AVAILABLE FOR BOTH WRITE AND READ Digital Attenuation Control 0dB to –120dB in 0.5dB Steps Attenuation Load Control Disable, Enable Attenuation Speed Selection x1fS, x1/2fS, x1/4fS, x1/8fS Soft Mute Control Mute Disable, Enable Infinite Zero Mute Control Disable, Enable Input Audio Data Format Selection 16-, 20-, 24-Bit Standard (Right Justified) Format 24-Bit MSB-First Left-Justified Format 16-, 24-Bit I2S Format De-Emphasis Control Disable, Enable Sampling Rate Selection for De-Emphasis Disable, 44.1kHz, 48kHz, 32kHz Digital Filter Roll-Off Selection Sharp Roll-Off, Slow Roll-Off Output Phase Reversal Normal. Reverse DAC Operation Control Enable, Disabled System Clock (SCKO) Output Control Output Enable, Disable System Clock (SCKO) Rate Control SCKI, SCKI/2 System Reset Control Reset Operation, Normal Operation Mode Register Reset Control Reset Operation, Normal Operation Digital-Filter Bypass Control DF Enable, DF Bypass Delta-Sigma Oversampling Rate Selection x64fS, x128fS, x32fS Delta-Sigma Order Selection Third-Order, Fifth-Order Monaural Mode Selection Stereo, Monaural Channel Selection for Monaural Mode Data L-Channel, R-Channel FUNCTIONS AVAILABLE ONLY FOR READ Zero Detection Flag Not Zero, Zero Detected TABLE II. User-Programmable Mode Controls. REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 16 17 18 19 20 21 W/R W/R W/R W/R W/R R 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 ATL7 ATR7 ATLD REV DSOS RSV ATL6 ATR6 FMT2 ATS1 SRST RSV ATL5 ATR5 FMT1 ATS0 MRST RSV ATL4 ATR4 FMT0 OPE DFTH RSV ATL3 ATR3 DMF1 CLKD MONO RSV ATL2 ATR2 DMF0 CLKE CHSL RSV ATL1 ATR1 DME FLT OS1 ZFGR ATL0 ATR0 MUTE INZD OS0 ZFGL NOTE: (1) RSV in Register 21 is assigned for factory test operation. TABLE III. Mode Control Register Map. 16 PCM1738 SBAS174B REGISTER DEFINITIONS B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 16 W/R 0 0 1 0 0 0 0 ATL7 ATL6 ATL5 ATL4 ATL3 ATL2 ATL1 ATL0 REGISTER 17 W/R 0 0 1 0 0 0 1 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 W/R Read/Write Mode Select When W/R = 0, a Write operation is performed. When W/R = 1, a Read operation is performed. Default Value: 0 ATL/R[7:0] Digital Attenuation Level Setting These bits are Read/Write. Default Value: 1111 1111B Each DAC output has a digital attenuator associated with it. The attenuator may be set from 0db to –120dB, in 0.5dB steps. Alternatively, the attenuator may be set to infinite attenuation (or mute). The attenuation data for each channel can be set individually. However, the data load control (ATLD bit of Control Register 18) is common to both attenuators. ATLD must be set to “1” in order to change an attenuator’s setting. The attenuation level may be set using the following formula: Attenuation Level (dB) = 0.5dB • (ATL/R[7:0]DEC – 255) Where: ATL/R[7:0]DEC = 0 through 255 For: ATL/R[7:0]DEC = 0 through 14, the attenuator is set to infinite attenuation. The following table shows attenuator levels for various settings. ATL/R[7:0] Decimal Value Attenuator Level Setting 1111 1111B 1111 1110B 1111 1101B • • 0001 0000B 0000 1111B 0000 1110B • • 0000 0000B 255 254 253 0dB, No Attenuation (default) –0.5dB –1.0dB • • 119.5dB 120.0dB Mute • • Mute REGISTER 18 • • 16 15 14 • • 0 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 W/R 0 0 1 0 0 1 0 ATLD FMT2 FMT1 FMT0 DMF1 DMF0 DME MUTE W/R Read/Write Mode Control When W/R = 0, a Write operation is performed. When W/R = 1, a Read operation is performed. Default Value: 0 ATLD Attenuation Load Control This bit is Read/Write. Default Value: 0 ATLD = 0 ATLD = 1 Attenuation Control Disabled (default) Attenuation Control Enabled The ATLD bit is used to enable loading of attenuation data set by Register 16 through 17. When ATLD = 0, the attenuation settings remain at the previously programmed level, ignoring new data loaded to Register 16 through 17. When ATLD = 1, attenuation data written to Register 16 through 17 is loaded normally. PCM1738 SBAS174B 17 REGISTER 18 (Cont.) FMT[2:0] Audio Interface Data Format These bits are Read/Write. Default Value: 000 For external Digital-Filter Interface Mode (DFTH Mode), this register is operated as shown in the External Digital-Filter Mode section of this data sheet. The FMT[2:0] bits are used to select the data format for the serial audio interface. FMT[2:0] 000 001 010 011 100 101 110 111 DMF[1:0] Audio Data Format Selection 16-Bit Standard Format, Right-Justified Data (default) 20-Bit Standard Format, Right-Justified Data 24-Bit Standard Format, Right-Justified Data 24-Bit MSB-First, Left-Justified Format Data 16-Bit I2S Format Data 24-Bit I2S Format Data Reserved Reserved Sampling Frequency Selection for the De-Emphasis Function These bits are Read/Write. Default Value: 00 DMF[1:0] 00 01 10 11 De-Emphasis Same Rate Selection Disabled (default) 48kHz 44.0kHz 32kHz The DMF[1:0] bits are used to select the sampling frequency used for the Digital De-Emphasis function when it is enabled by setting the DME bit. The De-Emphasis curves are shown in the Typical Performance Curves section of this data sheet. For DSD Mode, Analog FIR filter performance may be selected using this register. Filter response plots are shown in the Typical Performance Curves section of this data sheet. The Register Map is shown in the DSD Mode section of this data sheet. DME Digital De-Emphasis Control This bit is Read/Write. Default Value: 0 For DSD mode, DME must be set to 1. DME = 0 DME = 1 De-Emphasis Disabled (default) De-Emphasis Enabled The DME bit is used to enable or disable the De-Emphasis function for both channels. MUTE Soft Mute Control This bit is Read/Write. Default Value: 0 MUTE = 0 MUTE = 1 MUTE Disabled (default) MUTE Enabled The MUTE bit is used to enable the Soft Mute function for both channels. The mute function is also available through the MUTE control input (pin 15). Soft Mute is performed by using the 256 step attenuator, cycling one step per time interval to – (Mute). The time interval is set by the rate select bit (ATS), located in Register 19. 18 PCM1738 SBAS174B REGISTER 19 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 W/R 0 0 1 0 0 1 1 REV ATS1 ATS0 OPE CLKD CLKE FLT INZD W/R Read/Write Mode Control When W/R = 0, a Write operation is performed. When W/R = 1, a Read operation is performed. Default Value: 0 REV Output Phase Reversal This bit is Read/Write. Default Value: 0 REV = 0 REV = 1 Normal Output (default) Inverted Output The REV bit is used to invert the output phase for both the Left and Right channels. ATS[1:0] Attenuation Rate Select This bit is Read/Write. Default Value: 00 ATS[1:0] 00 01 10 11 Attenuation Rate Selection LRCK (default) 1/2 Times of LRCK 1/4 Times of LRCK 1/8 Times of LRCK The ATS[1:0] bits are used to select the rate at which the attenuator is decremented or incremented during level transitions. OPE DAC Operation Control This bit is Read/Write. Default Value: 0 OPE = 0 OPE = 1 DAC Operation Enabled (default) DAC Operation Disabled The OPE bit is used to enable or disable the analog output for both channels. Disabling the analog outputs forces them to the bipolar zero level (BPZ), ignoring the audio data input(s). CLKD SCKO Frequency Selection This bit is Read/Write. Default Value: 0 CLKD = 0 CLKD = 1 Full Rate, fSCKO = fSCKI (default) Half Rate, fSCKO = fSCKI/2 The CLKD bit is used to determine the output frequency at the system clock output pin, SCKO. CLKE SCKO Frequency Enable This bit is Read/Write. Default Value: 0 CLKE = 0 CLKE = 1 SCKO Enabled (default) SCKO Disabled The CLKE bit is used to enable or disable the system clock output pin, SCKO. PCM1738 SBAS174B 19 REGISTER 19 (Cont.) FLT Digital Filter Roll-Off Control This bit is Read/Write. Default Value: 0 FLT = 0 FLT = 1 Sharp Roll-Off (default) Slow Roll-Off The FLT bit allows the user to select the digital filter roll-off characteristics. The filter responses for these selections are shown in the Typical Performance Curves section of this data sheet. INZD Infinite Zero Detect Mute Control This bit is Read/Write. Default Value: 0 INZD = 0 INZD = 1 Infinite Zero Detect Mute Disabled (default) Infinite Zero Detect Mute Enabled The INZD bit is used to enable or disable the Zero Detect Mute function. Setting INZD = 1 allows the analog outputs to be set to the bipolar zero level when the PCM1738 detects zero data for both Left and Right channels for 1024 sampling periods (or LRCK cycles). REGISTER 20 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 W/R 0 0 1 0 1 0 0 DSOS SRST MRST DFTH MONO CHSL OS1 OS0 W/R Read/Write Mode Control When W/R = 0, a Write operation is performed. When W/R = 1, a Read operation is performed. Default Value: 0 DSOS Delta-Sigma Order Selection This bit is Read/Write. Default Value: 0 DSOS = 0 DSOS = 1 Third-Order Modulation (default) Fifth-Order Modulation The DSOS bit is used to change the order of delta-sigma modulation. It is possible to modify out-of-band noise characteristics when combined with the oversampling controls (OS0 and OS1). SRST System Reset Control This bit is Read/Write. Default Value: 0 SRST = 0 SRST = 1 Normal Operation (default) System Reset Operation The SRST bit is used to reset the PCM1738 to the initial system condition. MRST Mode-Register Reset Control This bit is Read/Write. Default Value: 0 MRST = 0 MRST = 1 Normal Operation (default) Mode-Register Reset Operation The MRST bit is used to set the mode registers to their default conditions. 20 PCM1738 SBAS174B REGISTER 20 (Cont.) DFTH Digital Filter Bypass (or Through Mode) Control This bit is Read/Write. Default Value: 0 DFTH = 0 DFTH = 1 Digital Filter Enabled (default) Digital Filter Bypassed for Either External Digital Filter or DSD Mode The DFTH bit is used to enable or bypass the internal digital filter. This function is used when using the external digital-filter interface or the DSD mode interface. MONO Monaural Mode Selection This bit is Read/Write. Default Value: 0 MONO = 0 MONO = 1 Stereo Mode (default) Monaural Mode The MONO function is used to change the operation mode from normal stereo mode to monaural mode. When the monaural mode is selected, both DACs operate in balanced mode for the selected audio input data. Left and Right channel data selection is set by the CHSL bit, as described below. CHSL Channel Selection for Monaural Mode This bit is Read/Write. Default Value: 0 This bit is available when MONO = 1. CHSL = 0 CHSL = 1 L-Channel Selected (default) R-Channel Selected The CHSL bit is used to set the audio data selection for the monaural mode. OS[1:0] Delta-Sigma Oversampling Rate Selection These bits are available for Read/Write. Default Value: 00 For DSD mode, this register is used to select the speed of BCK (pin 7) for the Analog FIR filter. OS[1:0] 00 01 10 11 Operation Speed Select 64x (default) Reserved 128x 32x The OS bits are used to change the oversampling ratio of the delta-sigma modulator. This function is useful when considering the output low-pass filter design that can handle a wide range of sampling rates. As an example, selecting 128x for fS = 44.1kHz, 64x for fS = 96kHz, and 32x for fS = 192kHz operation would require a lowpass filter with a single cutoff frequency to accommodate all three sampling rates. PCM1738 SBAS174B 21 REGISTER 21 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 W/R 0 0 1 0 1 0 1 RSV RSV RSV RSV RSV RSV ZFGR ZFGL W/R Read/Write Mode Control Only available to set 0 for Read back mode. ZFGx Zero Detection Flag When x = L or R, corresponding to the DAC output channel. These bits are Read only. Default Value: 00 ZFGx = 0 ZFGx = 1 Not ZERO ZERO Detected When the PCM1738 detects that audio input data is continuously zero for 1024fS, the ZFGx bit is set to 1 for the corresponding channel(s). Zero detect flags are also available at ZEROL (pin 2) and ZEROR (pin 3). TYPICAL CONNECTION DIAGRAM IN PCM MODE Controller +5.0V +15V –15V PCM1738E L/R Clock (fS) 1 RST VCC3 28 2 ZEROL AGND2 27 3 ZEROR IOUTL– 26 4 LRCK IOUTL+ 25 + VOUT L-Channel + 5 DATA VCC2 24 Bit Clock 6 BCK VCC1 23 System Clock 7 SCKI VCOM3 22 8 DGND IREF 21 9 VDD VCOM2 20 10 SCKO VCOM1 19 11 MDO AGND1 18 + +3.3V - + + Audio DATA VOUT R-Channel + 12 MDI IOUTR+ 17 13 MC IOUTR– 16 14 CS MUTE 15 - Analog Output Stage FIGURE 8. Typical Application Circuit for Standard PCM Audio Operation. 22 PCM1738 SBAS174B ANALOG OUTPUTS +5.0V PCM1738E 0.1 F VCC3 28 AGND2 27 IOUTL– 26 IOUTL+ 25 VCC2 24 VCC1 23 VCOM3 22 IREF 21 VCOM2 20 VCOM1 19 AGND1 18 IOUTR+ 17 C13 10 F R15 + R11 C17 R13 C11 R14 + R16 C15 R12 + 10 F R1 16k + R18 C14 C12 C23 R25 R21 C27 + C21 MUTE 15 C16 10 F R23 16 R17 - 10 F IOUTR– VOUT L-Channel R24 + R26 C25 VOUT R-Channel R27 - R22 C22 NOTE: Example R/C values for fC 45kHz. R11-R18, R21-R28: 620 , C11, C12, C21, C22: not populated, C13, C14, C23, C24: 5600pF, C15, C25: 8200pF, C16, C17, C26, C27: 1800pF. R28 C26 C24 OPA627BP, BM or OPA5534 Op Amp OPA134, OPA2134, or OPA604, OPA2604 Op Amp FIGURE 9. Typical Application for Analog Output Stage. ANALOG OUTPUT LEVEL AND I/V CONVERTER The signal level of the DAC current output pins (IOUTL+, IOUTL–, IOUTR+, and IOUTR–) is 2.48mA (p-p) at 0dB (Full Scale). The voltage output of the I/V converter is given by the following equation: VOUT = 2.48mApp • RF (1) Here, Rf is the feedback resistor in the I/V (current-tovoltage) conversion circuit, R11, R12, R21, and R22 on a typical application circuit. The common level of the I/V conversion circuit must be the same as the common level of DAC IOUT that is given by the VCOM2 reference voltage, +2.5V DC. The non-inverting inputs of the op amps shown in the I/V circuits are connected to VCOM2 to provide the common bias voltage. Op Amp for I/V Converter Circuit The OPA627BP/BM, or 5534 type op amp, is recommended for the I/V conversion circuit to obtain specified audio performance. Dynamic performance, such as gain bandwidth, settling time, and slew rate of the op amp creates audio dynamic performance at the I/V section. Input noise specification of the op amp should be considered to obtain 120dB S/N ratio. PCM1738 SBAS174B Analog Gain by Balanced Amplifier The I/V converters are followed by balanced amplifier stages that sum the differential signals for each channel, creating a single-ended voltage output. In addition, the balanced amplifiers provide a second-order, low-pass filter function that band limits the audio output signal. The cutoff frequency and gain is given by external R and C component values. In the case of Figure 9, the cutoff frequency is 45kHz with a gain of 1. The output voltage for each channel is 6.2 Vp-p, or 2.2Vrms. REFERENCE CURRENT RESISTOR As shown in the analog output application circuit, marked R1 on Figure 9, there is a resistor connected from IREF (pin 21) to the analog ground, designated as R1. This resistor sets the current for the internal reference circuit. The value of R1 must be 16k , 1% in order to match the specified gain error shown in the Specifications table. 23 APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE VCC3 28 ZEROL AGND2 27 3 ZEROR IOUTL– 26 WDCK (Word Clock) 4 WDCK IOUTL+ 25 DATA-L 5 DATAL VCC2 24 BCK 6 BCK VCC1 23 SCK 7 SCKI VCOM3 22 8 DGND IREF 21 9 VDD VCOM2 20 10 SCKO VCOM1 19 11 MDO AGND1 18 12 MDI IOUTR+ 17 13 MC IOUTR– 16 14 CS DATAR 15 DF1704 DF1706 1 RST 2 Analog Output Stage Same as Standard Application PMD200 Mode Control DATA-R FIGURE 10. Connection Diagram for External Digital Filter (Internal DF Bypass Mode) Application. APPLICATIONS FOR INTERFACING WITH THE EXTERNAL DIGITAL FILTER PART For some applications, it may be desirable to use an external digital filter to perform the interpolation function, as it may provide improved stopband attenuation or other special features not available with the PCM1738’s internal digital filter. The PCM1738 supports the use of an external digital filter, including: • The DF1704 and DF1706 from Texas Instruments. • Pacific Microsonics PMD100/200 HDCD Filter/Decoder ICs. • Programmable Digital Signal Processors. The external digital-filter application mode is available by programming the following bits in the corresponding control registers: DFTH = 1 (Register 20) DME = 0 (Register 18) 24 The pins used to provide the serial interface for the external digital filter are shown in the application diagram of Figure 10. The Word (WDCK) and Bit (BCK) clock signals, as well as the audio data inputs (DATAL and DATAR) must be operated at 8x or 4x the original sampling frequency at the input of the digital filter. SYSTEM CLOCK (SCKI) AND INTERFACE TIMING The PCM1738, in external digital filter application, allows any system-clock frequency synchronized with BCK and WDCK. The system clock may be phase free with BCK and WDCK. See Figure 17 for interface timing among WDCK, BCK, DATAL, and DATAR. AUDIO FORMAT In external Digital-Filter Interface mode, the PCM1738 supports a right-justified audio format interface including 16-, 20-, and 24-bit audio data (see Figure 16) that should be selected by FMT[2:0] of Control Register 18. PCM1738 SBAS174B FUNCTIONS AVAILABLE IN THE EXTERNAL DIGITAL-FILTER MODE The external Digital-Filter mode allows access to the majority of the PCM1738’s mode control functions. Table IV shows the register mapping available when the external Digital-Filter mode is selected, along with descriptions of functions that are modified for this mode selection. REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 16 17 18 19 20 21 W/R W/R W/R W/R W/R R 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 – – – – RSV RSV – – FMT2 – SRST RSV B5 B4 – – – – FMT1 FMT0 – OPE MRST DFTH(1) RSV RSV B3 B2 B1 B0 – – – CLKD RSV RSV – – – CLKE CHSL RSV – – DME(1) – OS1 ZFGR – – – INZD OS0 ZFGL NOTE: (1) This bit is required for selection of the external Digital-Filter mode. (2) “–” = function disabled. TABLE IV. Register Mapping in the External Digital-Filter Mode. FMT[2:0] Audio Data Format Selection These bits are available for Read/Write. Default Value: 000 FMT[2:0] 000 001 010 Other OS[1:0] Audio Data Format Select 16-Bit Right Justified Format (default) 20-Bit Right Justified Format 24-Bit Right Justified Format N/A Delta-Sigma Oversampling Rate Selection These bits are available for Read/Write. Default Value: 00 OS[1:0] 00 01 10 11 Operation Speed Select 8x fWCK (default) Reserved 16x fWCK 4x fWCK The effective oversampling rate is determined by the oversampling performed by both the external digital filter and the delta-sigma modulator. For example, if the external digital filter is 8x oversampling, and the user selects OS[1:0] = 0, then the delta-sigma modulator will oversample by 8x, resulting in an effective oversampling rate of 64x. ZFGx Zero Detection Flag When x = L or R, corresponding to the DAC output channel. These bits are available only for Read back. Default Value: 00 ZFGx = 0 ZFGx = 1 Not ZERO ZERO Detected When the PCM1738 detects that audio input data is continuously zero for 1024fS, the ZFGx bit is set to 1 for the corresponding channel(s). Zero detect flags are also available at ZEROL (pin 2) and ZEROR (pin 3). PCM1738 SBAS174B 25 APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE Always Set LOW DATA-L Always Set LOW Bit Clock (n • fS) DSD Decoder Mode Control 1 RST VCC3 28 2 ZEROL AGND2 27 3 ZEROR IOUTL– 26 4 N/A IOUTL+ 25 5 DATAL VCC2 24 6 N/A VCC1 23 7 BCK VCOM3 22 8 DGND IREF 21 9 VDD VCOM2 20 10 SCKO VCOM1 19 11 MDO AGND1 18 12 MDI IOUTR+ 17 13 MC IOUTR– 16 14 CS DATAR 15 Analog Output Stage Same as Standard Application DATA-R FIGURE 11. Connection Diagram for DSD Format Interface. FEATURES This mode is utilized for interfacing directly to a DSD decoder, found in Super Audio CD (SACD) applications. DSD Mode provides a low-pass filtering function to convert the 1-bit oversampled data stream to the analog domain. The filtering is provided using an Analog FIR filter structure. Four FIR responses are available and may be selected via the serial control interface. Refer to the Typical Performance Curves section of this data sheet for Analog FIR plots. See Figures 1 and 2 for interface timing and specification, and Figures 17 and 18 for timing and interface specification in DSD mode. 26 PIN ASSIGNMENT WHEN IN DSD FORMAT INTERFACE Several pins are redefined for DSD Mode operation. These include: • DATA (Pin 5) DATAL, L-Channel DSD Data Input • MUTE (Pin 15) DATAR, R-Channel DSD Data Input • SCKI (Pin 7) Bit Clock (BCK) for DSD Data (64 x 44.1kHz) • LRCK (Pin 4) Set LOW • BCK (Pin 6) Set LOW Typical connection to a DSD decoder is shown in Figure 11. PCM1738 SBAS174B DSD MODE CONFIGURATION AND FUNCTION CONTROLS Configuration for DSD Interface mode: • DFTH = 1 (Register 20) • DME = 1 (Register 18) Table V shows the register mapping available in DSD Mode. REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 16 17 18 19 20 21 W/R W/R W/R W/R W/R R 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 – – – – RSV RSV – – – – SRST RSV B5 B4 – – – – – – – OPE MRST DFTH(1) RSV RSV B3 B2 B1 B0 – – DMF1 CLKD RSV RSV – – DMF0 CLKE RSV RSV – – DME(1) – OS1 – – – – – OS0 – NOTE: (1) This bit is required for selection of the external Digital Filter mode. (2) “–” = function disabled. TABLE V. Register Mapping in DSD Mode. DMF[1:0] Analog FIR Performance Selection These bits are available for Read/Write. Default Value: 00 DMF[1:0] 00 01 10 11 Analog FIR Performance Select DSD Filter 1 DSD Filter 2 DSD Filter 3 DSD Filter 4 Plots for the four Analog FIR filter responses are shown in the Typical Performance Curves of this data sheet. OS[1:0] Analog FIR Operation Speed Select Selection These bits are available for Read/Write. Default Value: 00 OS[1:0] 00 01 10 11 Operation Speed Select fSCKI (default) Reserved Reserved fSCKI/2 The OS bit in the DSD mode is used to select the operating rate of analog FIR. REQUIREMENTS FOR SYSTEM CLOCK The bit clock (BCK) for DSD Mode is required at pin 7 of the PCM1738. The frequency of the bit clock may be N times of the sampling frequency. Generally, N is 64 in DSD application. The interface timing between the bit clock, DATAL, and DATAR is required to meet the same setup and hold time specifications as shown for the PCM Audio format interface in Figure 5. PCM1738 SBAS174B 27 APPLICATION FOR MONAURAL MODE OPERATION are useful for high-end audio applications to provide over 120dB for dynamic range. A typical MONO mode application is shown in Figure 12. Single-channel signals within stereo-audio data input is output to both IOUTL and IOUTR as differential outputs. Selection of channels to output is available with the CHSL bit in Register 20. Applications, such as monaural operation, PCM1738 L/R Clock LRCK Audio Data DATA IOUTL– IOUTL+ Bit Clock BCK System Clock SCKI IOUTR– Analog Output Stage VOUT L-Channel Analog Output Stage VOUT R-Channel IOUTR+ MC, CS, MDI PCM1738 LRCK IOUTL– Controller DATA IOUTL+ BCK SCKI IOUTR– IOUTR+ MC, CS, MDI FIGURE 12. Connection Diagram for Monaural-Mode Interface. 28 PCM1738 SBAS174B THEORY OF OPERATION ADVANCED SEGMENT DAC Upper 6 Bits ICOB Decoder 0 • 62 Level Digital Input 0 • 66 + 24-Bit 8fS Advanced DWA Current Segment DAC Analog Output 3rd-Order, 5th-Level, MSB and Lower 18 Bits 0•4 Level FIGURE 13. Architecture of Advanced Segment DAC. The PCM1738 utilizes the newly developed Advanced Segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1738 provides balanced current outputs, allowing the user to optimize analog performance externally. The structure of the Advanced Segment DAC architecture is shown in Figure 13. Digital input data from the digital interpolation filter is split into six upper bits and 18 lower bits. The upper six bits are converted to ICOB (Inverted Complementary Offset Binary) code. The lower 18 bits associated with the MSB are processed by fifth-level, third-order, delta-sigma modulators operated at 64fS by default conditions. The first level of the modulator is equivalent to 1LSB of the above code con- PCM1738 SBAS174B verter. The data groups processed in the ICOB converter and the third-order delta-sigma modulator are summed together to create up to 67 levels of digital code that is then processed by the DWA (Data Weighted Averaging) to reduce noise produced by element mismatch. The output data from the DWA block is then converted to an analog output using a differential current segment DAC. To learn more details regarding the Advanced Segment DAC architecture, please refer to the paper presented at the 109th AES Convention entitled “A 117db, D-Range, Current-mode, Multi-Bit, Audio DAC for PCM and DSD Audio Playback” by Nakao, Terasawa, Aoyagi, Terada, and Hamasaki of Burr-Brown Japan (now part of Texas Instruments). 29 Separate power supplies are recommended for the digital and analog sections of the board. This prevents the switching noise present on the digital supply from contaminating the analog power supply and degrading the dynamic performance of the DACs. In cases where a common +5V supply must be used for the analog and digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital +5V supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 15 shows the recommended approach for singlesupply applications. CONSIDERATIONS FOR APPLICATIONS CIRCUITS PCB LAYOUT GUIDELINES A typical PCB floor plan for the PCM1738 is shown in Figure 14. A ground plane is recommended, with the analog and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1738 should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections to the digital audio interface and control signals originating from the digital section of the board. Analog Power Digital Power +VD DGND AGND +5VA +VS –VS REG VCC VDD Digital Logic and Audio Processor Output Circuits DGND PCM1738 Digital Ground AGND DIGITAL SECTION Analog Ground ANALOG SECTION Return Path for Digital Signals FIGURE 14. Recommended PCB Layout. Power Supplies RF Choke or Ferrite Bead +5V AGND +VS –VS REG VCC VDD VDD DGND Output Circuits PCM1738 AGND Common Ground DIGITAL SECTION ANALOG SECTION FIGURE 15. Single-Supply PCB Layout. 30 PCM1738 SBAS174B 1/4fS or 1/8fS WDCK BCK Audio Data Word = 16 Bit DATAL DATAR 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 MSB 15 16 LSB Audio Data Word = 20 Bit DATAL DATAR 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 MSB 19 20 LSB Audio Data Word = 24 Bit DATAL DATAR 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 MSB 22 23 24 LSB FIGURE 16. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application. WDCK 50% of VDD tBCH tBCL tLB BCK 50% of VDD tBCY tBL DATAL DATAR 50% of VDD tDS SYMBOL tBCY tBCL tBCH tBL tLB tDS tDH tDH PARAMETER MIN BCK Pulse Cycle Time BCK Pulse Width LOW BCK Pulse Width HIGH BCK Rising Edge to WDCK Falling Edge WDCK Falling Edge to BCKIN Rising Edge DATA Set-Up Time DATA Hold Time 18 7 7 5 5 5 5 MAX UNITS n ns ns ns ns s ns ns FIGURE 17. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application. BYPASS AND DECOUPLING CAPACITOR REQUIREMENTS Various sized decoupling capacitors can be used, with no special tolerances being required. All capacitors should be located as close as physically possible to the power supply and reference pins of the PCM1738 to reduce noise pickup from surrounding circuitry. Aluminum electrolytic capacitors that are designed for hi-fi audio applications are recommended for larger values, while metal-film or monolithic ceramic capacitors are recommended for smaller values. I/V SECTION I/V conversion, using the circuit shown in Figure 9, achieves data-sheet performance (see Figure 9). To obtain 0.0005% THD+N, 117dB signal-to-noise ratio audio performance, THD+N and input noise performance an op amp IC must be considered. Input noise of the op amp directly effects the output noise level of the application. PCM1738 SBAS174B All components of the I/V section should be located physically close to the PCM1738 current outputs. All connections should be made as short as possible to eliminate pickup of radiated noise. POST LOW-PASS FILTER DESIGN The out-of-band noise level and sampling spectrum level are much lower than typical delta-sigma type DACs, due to the combination of a high-performance digital filer and the advanced segment DAC architecture. The use of a secondor third-order filter is recommended for the post low-pass filter (see Figure 9 for a second-order filter) following the I/ V conversion stage. The cutoff frequency of the post LPF is dependent upon the application, given the variety of sampling rates supported by the CD-DA, DVD-M, DVD-A, and SACD systems. 31 PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2004 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PCM1738E ACTIVE SSOP DB 28 47 None CU SNPB Level-1-235C-UNLIM PCM1738E/2K ACTIVE SSOP DB 28 2000 None CU SNPB Level-1-235C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. 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