IN74HC240A OCTAL 3-STATE INVERTING BUFFER/LINE DRIVER/LINE RECEIVER High-Performance Silicon-Gate CMOS • • • • The IN74HC240A is identical in pinout to the LS/ALS240. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This octal inverting buffer/line driver/line receiver is designed to be used with 3-state memory address drivers, clock drivers, and other bus-oriented systems. The device has inverting outputs and two active-low output enables. Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION IN74HC240AN Plastic IN74HC240ADW SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs Enable A, A,B Enable B L L L H H X PIN 20=VCC PIN 10 = GND X = don’t Z = high impedance 1 Outputs YA,YB H L Z care IN74HC240A MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA ±20 IOUT DC Output Current, per Pin mA ±35 ICC DC Supply Current, VCC and GND Pins mA ±75 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 °C 260 TL Lead Temperature, 1 mm from Case for 10 °C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types t r, tf Input Rise and Fall Time (Figure VCC =2.0 V 1) VCC =4.5 V VCC =6.0 V Min 2.0 0 Max 6.0 VCC Unit V V -55 0 0 0 +125 1000 500 400 °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74HC240A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed Limit VCC Symbol Parameter Test Conditions V 25 °C to ≤85 ≤125 -55°C °C °C 1.5 1.5 VOUT=0.1 V 1.5 VIH Minimum High2.0 3.15 3.15 3.15 Level Input 4.5 IOUT≤ 20 µA 4.2 4.2 4.2 Voltage 6.0 0.5 0.5 VOUT= VCC-0.1 V 0.5 VIL Maximum Low 2.0 1.35 1.35 1.35 Level Input 4.5 IOUT ≤ 20 µA 1.8 1.8 1.8 Voltage 6.0 1.9 1.9 VIN= VIL 1.9 VOH Minimum High2.0 4.4 4.4 4.4 Level Output 4.5 IOUT ≤ 20 µA 5.9 5.9 5.9 Voltage 6.0 VIN=VIL 3.7 3.84 3.98 4.5 IOUT ≤ 6.0 mA 5.2 5.34 5.48 6.0 IOUT ≤ 7.8 mA 0.1 0.1 VIN=VIH 0.1 VOL Maximum Low2.0 0.1 0.1 0.1 Level Output 4.5 IOUT ≤ 20 µA 0.1 0.1 0.1 Voltage 6.0 VIN= VIH 0.4 0.33 0.26 4.5 IOUT ≤ 6.0 mA 0.4 0.33 0.26 6.0 IOUT ≤7.8 mA IIN Maximum Input VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 Leakage Current Output in HighIOZ Maximum three 6.0 ±0.5 ±5.0 ±10. Impedance State State Leakage 0 VIN = VIL or VIH Current VOUT=VCC or GND VIN=VCC or GND ICC Maximum 6.0 4.0 40 160 Quiescent Supply IOUT=0µA Current (per Package) 3 Unit V V V V µA µA µA IN74HC240A AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit VCC Symbol Parameter V 25 °C ≤85°C ≤125 to °C -55°C 120 100 80 tPLH, Maximum Propagation Delay, A to YA or 2.0 24 20 16 tPHL B to YB (Figures 1 and 3) 4.5 20 17 14 6.0 165 140 110 tPLZ, Maximum Propagation Delay, Output 2.0 33 28 22 tPHZ Enable to YA or YB (Figures 2 and 4) 4.5 28 24 19 6.0 165 140 110 tPZH, Maximum Propagation Delay, Output 2.0 33 28 22 tPZL Enable to YA or YB (Figures 2 and 4) 4.5 28 24 19 6.0 90 75 60 tTLH, tTHL Maximum Output Transition Time, Any 2.0 18 15 12 4.5 Output 15 13 10 6.0 (Figures 1 and 3) CIN Maximum Input Capacitance 10 10 10 15 15 15 COUT Maximum Three-State Output Capacitance (Output in High-Impedance State) CPD Power Dissipation Capacitance (Per Transceiver Channel) Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Figure 1. Switching Waveforms ns ns ns ns pF pF Typical @25°C,VCC=5.0 V 32 Figure 2. Switching Waveforms 4 Unit pF IN74HC240A Figure 3. Test Circuit Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM (1/8 of the Device) 5