IN74HC640A OCTAL 3-STATE INVERTING BUS TRANSCEIVER High-Performance Silicon-Gate CMOS • • • • The IN74HC640A is identical in pinout to the LS/ALS640. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The IN74HC640A is a 3-state transceiver that is used for 2way asynchronous communication between data buses. The device has an active-low Output Enable pin, which is used to place the I/O ports into high-impedance states. The Direction control determines whether data flows from A to B or from B to A. Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION IN74HC640AN Plastic IN74HC640ADW SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Control Inputs Output Direction Enable L L PIN 20=VCC PIN 10 = GND L H H X X = don’t care 1 Operation Data Transmitted from Bus B to Bus A (inverted) Data Transmitted from Bus A to Bus B (inverted) Buses Isolated (High Impedance State) IN74HC640A MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA ±20 IOUT DC Output Current, per Pin mA ±35 ICC DC Supply Current, VCC and GND Pins mA ±75 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 °C 260 TL Lead Temperature, 1 mm from Case for 10 °C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types t r, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. 2 IN74HC640A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed Limit VCC Symbol Parameter Test Conditions V ≤85 ≤125 25 °C to °C °C -55°C 1.5 1.5 VOUT=0.1 V or VCC-0.1 V 2.0 1.5 VIH Minimum High3.15 3.15 3.15 Level Input 4.5 IOUT≤ 20 µA 4.2 4.2 4.2 Voltage 6.0 0.3 0.3 VOUT=0.1 V or VCC-0.1 V 2.0 0.3 VIL Maximum Low 0.9 0.9 0.9 Level Input 4.5 IOUT ≤ 20 µA 1.2 1.2 1.2 Voltage 6.0 1.9 1.9 VIN=VIH or VIL 1.9 VOH Minimum High2.0 4.4 4.4 4.4 Level Output 4.5 IOUT ≤ 20 µA 5.9 5.9 5.9 Voltage 6.0 VIN=VIH or VIL 3.7 3.84 3.98 4.5 IOUT ≤ 6.0 mA 5.2 5.34 5.48 6.0 IOUT ≤ 7.8 mA 0.1 0.1 VIN= VIL or VIH 0.1 VOL Maximum Low2.0 0.1 0.1 0.1 Level Output 4.5 IOUT ≤ 20 µA 0.1 0.1 0.1 Voltage 6.0 VIN= VIL or VIH 0.4 0.33 0.26 4.5 IOUT ≤ 6.0 mA 0.4 0.33 0.26 6.0 IOUT ≤ 7.8 mA IIN Maximum Input VIN=VCC or GND, Pin 1 6.0 ±0.1 ±1.0 ±1.0 Leakage Current or 19 IOZ Maximum Three- Output in High6.0 ±0.5 ±5.0 ±10 Impedance State State Leakage VIN= VIL or VIH Current VOUT=VCC or GND VIN=VCC or GND ICC Maximum 6.0 4.0 40 160 Quiescent Supply IOUT=0µA Current (per Package) 3 Unit V V V V µA µA µA IN74HC640A AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit VCC Symbol Parameter V 25 °C ≤85°C ≤125 to °C -55°C 110 95 75 tPLH, Maximum Propagation Delay, A to B , B 2.0 22 19 15 tPHL to A (Figures 1 and 3) 4.5 19 16 13 6.0 165 140 110 tPLZ, Maximum Propagation Delay , Direction 2.0 33 28 22 tPHZ or Output Enable to A or B (Figures 2 4.5 28 24 19 6.0 and 4) 165 140 110 tPZL, Maximum Propagation Delay , Direction 2.0 33 28 22 tPZH or Output Enable to A or B (Figures 2 4.5 28 24 19 6.0 and 4) 90 75 60 tTLH, tTHL Maximum Output Transition Time, Any 2.0 18 15 12 4.5 Output 15 13 10 6.0 (Figures 1 and 3) CIN Maximum Input Capacitance (Pin 1 or 10 10 10 Pin 19) COUT Maximum Three-State I/O Capacitance 15 15 15 (Output in High-Impedance State) CPD Power Dissipation Capacitance (Per Transceiver Channel) Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Figure 1. Switching Waveforms ns ns ns ns pF pF Typical @25°C,VCC=5.0 V 40 Figure 2. Switching Waveforms 4 Unit pF IN74HC640A Figure 3. Test Circuit Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM 5