SL74HC367 Hex 3-State Noninverting Buffer with Separate 2-Bit and 4-Bit Sections High-Performance Silicon-Gate CMOS The SL74HC367 is identical in pinout to the LS/ALS367. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device is arranged into 2-Bit and 4-Bit sections, each having its own active-low Output Enable. When either of the enables is high, the affected buffer outputs are placed into high-impedance states. The SL74HC367 has noninverting outputs. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC367N Plastic SL74HC367D SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs PIN 16 =VCC PIN 8 = GND SLS System Logic Semiconductor Output Enable 1,Enable 2 A Y L L L L H H H X Z Z = high impedance X = don’t care SL74HC367 MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA DC Output Current, per Pin ±35 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN IOUT Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL74HC367 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC V 25 °C to -55°C ≤85 °C ≤125 °C Unit VOUT= VCC-0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V Maximum Low -Level Input Voltage VOUT=0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V Minimum High-Level Output Voltage VIN=VIH IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN= VIL IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 Symbol Parameter VIH Minimum High-Level Input Voltage VIL VOH Test Conditions VIN=VIH IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA VOL Guaranteed Limit Maximum Low-Level Output Voltage VIN= VIL IOUT ≤ 20 µA V IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA IOZ Maximum Three-State Leakage Current Output in High-Impedance State VIN= VIL or VIH VOUT=VCC or GND 6.0 ±0.5 ±5.0 ±10 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 8.0 80 160 µA SLS System Logic Semiconductor SL74HC367 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol Parameter Guaranteed Limit V 25 °C to -55°C ≤85°C ≤125°C Unit TPLH, t PHL Maximum Propagation Delay, Input A to Output Y (Figures 1 and 3) 2.0 4.5 6.0 120 24 20 150 30 26 180 36 31 ns TPLZ, t PHZ Maximum Propagation Delay ,Output Enable to Output Y (Figures 2 and 4) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 46 ns TPZL, t PZH Maximum Propagation Delay ,Output Enable to Output Y (Figures 2 and 4) 2.0 4.5 6.0 190 38 32 240 48 41 285 57 48 ns TTLH, t THL Maximum Output Transition Time, Any Output (Figures 1 and 3) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns Maximum Input Capacitance - 10 10 10 pF Maximum Three-State Output Capacitance (Output in High-Impedance State) - 15 15 15 pF CIN COUT Power Dissipation Capacitance (Per Buffer) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Figure 1. Switching Waveforms Typical @25°C,VCC=5.0 V 40 pF Figure 2. Switching Waveforms SLS System Logic Semiconductor SL74HC367 Figure 3. Test Circuit Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM (1/6 of the Device) SLS System Logic Semiconductor