IN74HC251A 8-INPUT DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS High-Performance Silicon-Gate CMOS • • • • The IN74HC251 is identical in pinout to the LS/ALS251. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The device selects one of the eight binary Data Inputs, as determined by the Address Inputs. The Output Enable pin must be at a low level for the selected data to appear at the outputs. If Output Enable is high, the Y and the Y outputs are in the highimpedance state. This 3-State feature allows the IN74HC251 to be used in bus-oriented systems. Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION IN74HC251N Plastic IN74HC251D SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE A2 X L L L L H H H H PIN 16 =VCC PIN 8 = GND A1 X L L H H L L H H Inputs A0 X L H L H L H L H OE H L L L L L L L L Outputs Y Y Z Z D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 D0,D1...D7=the level of the respective D input Z = high-impedance state X = don’t care 1 IN74HC251A MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA ±25 IOUT DC Output Current, per Pin mA ±50 ICC DC Supply Current, VCC and GND Pins mA ±75 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 °C 260 TL Lead Temperature, 1 mm from Case for 10 °C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types t r, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74HC251A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed Limit VCC Symbol Parameter Test Conditions V ≤85 ≤125 25 °C to °C °C -55°C 1.5 1.5 VOUT=0.1 V or VCC-0.1 V 2.0 1.5 VIH Minimum High3.15 3.15 3.15 Level Input 4.5 IOUT≤ 20 µA 4.2 4.2 4.2 Voltage 6.0 0.3 0.3 VOUT=0.1 V or VCC-0.1 V 2.0 0.3 VIL Maximum Low 0.9 0.9 0.9 Level Input 4.5 IOUT ≤ 20 µA 1.2 1.2 1.2 Voltage 6.0 1.9 1.9 VIN=VIH or VIL 1.9 VOH Minimum High2.0 4.4 4.4 4.4 Level Output 4.5 IOUT ≤ 20 µA 5.9 5.9 5.9 Voltage 6.0 4.5 3.98 3.84 3.7 VIN=VIH or VIL 6.0 5.48 5.34 5.2 IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 0.1 0.1 VIN=VIH or VIL 0.1 VOL Maximum Low2.0 0.1 0.1 0.1 Level Output 4.5 IOUT ≤ 20 µA 0.1 0.1 0.1 Voltage 6.0 4.5 0.26 0.33 0.4 VIN=VIH or VIL 6.0 0.26 0.33 0.4 IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA IIN Maximum Input VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 Leakage Current IOZ Maximum Three- Output in High6.0 ±0.5 ±5.0 ±10 Impedance State State Leakage VIN= VIL or VIH Current VOUT=VCC or GND VIN=VCC or GND ICC Maximum 6.0 8.0 80 160 Quiescent Supply IOUT=0µA Current (per Package) 3 Unit V V V V µA µA µA IN74HC251A AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit VCC Symbol Parameter V 25 °C ≤85°C ≤125 to °C -55°C 280 230 185 tPLH, Maximum Propagation Delay, Input D to 2.0 56 46 37 tPHL Output Y or Y (Figures 1,2 and 5) 4.5 48 39 31 6.0 310 255 205 tPLH, Maximum Propagation Delay , Input A to 2.0 62 51 41 tPHL Output Y or Y (Figures 3 and 5) 4.5 53 43 35 6.0 295 245 195 tPLZ, Maximum Propagation Delay , Output 2.0 59 48 39 tPHZ Enable to 4.5 50 42 33 6.0 Output Y (Figures 4 and 6) 220 180 145 tPZL, Maximum Propagation Delay , Output 2.0 44 36 29 tPZH Enable to 4.5 38 31 25 6.0 Output Y (Figures 4 and 6) 330 275 220 tPLZ, Maximum Propagation Delay , Output 2.0 66 55 44 tPHZ Enable to 4.5 56 47 37 6.0 Output Y (Figures 4 and 6) 225 190 150 tPZL, Maximum Propagation Delay , Output 2.0 45 38 30 tPZH Enable to 4.5 38 33 26 6.0 Output Y (Figures 4 and 6) 110 95 75 tTLH, tTHL Maximum Output Transition Time, Any 2.0 22 19 15 4.5 Output 19 16 13 6.0 (Figures 1 and 6) CIN Maximum Input Capacitance 10 10 10 15 15 15 COUT Maximum Three-State Output Capacitance (Output in High-Impedance State) CPD Power Dissipation Capacitance (Per Package) Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Figure 1. Switching Waveforms ns ns ns ns ns ns ns pF pF Typical @25°C,VCC=5.0 V 36 Figure 2. Switching Waveforms 4 Unit pF IN74HC251A Figure 3. Switching Waveforms Figure 5. Test Circuit Figure 4. Switching Waveforms Figure 6.Test Circuit EXPANDED LOGIC DIAGRAM 5