TECHNICAL DATA SL74LV04 Hex Inverter The SL74LV04 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT04A. The SL74LV04 provides six inverting buffers. • • • • Wide Operating Voltage: 1.0 ~ 5.5 V Optimized for Low Voltage applications: 1.0 ~ 3.6 V Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V Low Input Current ORDERING INFORMATION SL74LV04N Plastic SL74LV04D SOIC SL74LV04 Chip TA = -40° ÷ 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Input Output A Y L H H L PIN 14 =VCC PIN 7 = GND SLS System Logic Semiconductor 1 SL74LV04 MAXIMUM RATINGS * Symbol Value Unit -0.5 ~ +7.0 V DC input diode current ±20 mA DC output diode current ±50 mA DC output source or sink current -bus driver outputs ±25 mA DC GND current for types with - bus driver outputs ±50 mA ICC DC VCC current for types with - bus driver outputs ±50 mA PD Power dissipation per package, plastic DIP+ SOIC package+ 750 500 mW -65 ~ +150 °C 260 °C VCC IIK* DC supply voltage (Referenced to GND) 1 IOK* 2 Io* Parameter 3 IGND Tstg Storage temperature TL Lead temperature, 1.5 mm from Case for 10 seconds (Plastic DIP ), 0.3 mm (SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SOIC Package: : - 8 mW/°C from 70° to 125°C * 1: VI < -0.5V or VI > VCC+0.5V * 2: Vo < -0.5V or Vo > VCC+0.5V * 3: -0.5V < Vo < VCC+0.5V RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V Min Max Unit 1.0 5.5 V 0 VCC V -40 +125 °C 0 0 0 0 1000 700 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor 2 SL74LV04 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC, -40°C ÷ 85°C 25°C V -40°C ÷ 125°C min max min max min max Unit VIH High-Level Input Voltage 1.2 2.0 3.0 3.6 0.9 1.4 2.1 2.5 - 0.9 1.4 2.1 2.5 - 0.9 1.4 2.1 2.5 - V VIL Low-Level Input Voltage 1.2 2.0 3.0 3.6 - 0.3 0.6 0.9 1.1 - 0.3 0.6 0.9 1.1 - 0.3 0.6 0.9 1.1 V VOH High-Level Output VI = VIL Voltage IO = -50 µA 1.2 2.0 * 1.1 1.92 2.92 - 1.0 1.9 2.9 - 1.0 1.9 2.9 - V * 2.48 - 2.34 - 2.20 - V 1.2 2.0 - 0.09 0.09 0.09 - 0.1 0.1 0.1 - 0.1 0.1 0.1 V 3.0 - 0.33 - 0.4 - 0.5 V - -0.1 - -1.0 - -1.0 µA VI = VIL IO = -6.0 µA VOL Low-Level Output VI = VIH Voltage IO = 50 µA VI = VIH or VIL IO = 6.0 mÀ IIL Low-Level Input Leakage Current IIÍ High-Level Input VI = VCC Leakage Current * - 0.1 - 1.0 - 1.0 µA IÑÑ Quiescent Supply VI = 0 Â or VCC Current IO = 0 µA (per Package) * - 2.0 - 20 - 40 µA * : VCC= (3.3±0.3) V SLS System Logic Semiconductor 3 SL74LV04 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t LH = t HL = 6.0 ns, VIL=0V, VIH=VCC, RL=1 kÙ) Guaranteed Limit VCC Symbol Parameter 25°C V -40°C ÷ 85°C -40°C ÷ 125°C min max min max min max tTHL, (t TLH) Output Transition Time, Any Output (Figure 1) 1.2 2.0 * - 70 16 10 - 85 20 13 - 100 24 15 tPHL, (t PLH) Propagation Delay, Input A to Output Y (Figure 1) 1.2 2.0 * - 90 23 14 - 120 28 18 - 150 34 21 Input Capacitance 3.0 - - - 3.5 - 3.5 CI CPD Power Dissipation Capacitance (Per Inverter) Ò À=25°Ñ, VI=0V÷VCC Unit ns pF pF 42 Used to determine the no-load dynamic power consumption: PD = CPDVCC2fI+ (CLVCC2fo), fI - input frequency, fo - output frequency (MHz) (CLVCC2fo) – sum of the outputs tHL tLH V CC 0.9 0.9 Input À V1 V1 0.1 0.1 tPHL 0.9 0.9 Output Y V CC V1 V1 0.1 V 1 = 0.5 VC C GND tPLH 0.1 tTHL GND tTLH Figure 1. Switching Waveforms V CC VI Termination resistance RT – should be equal to ZOUT of pulse generators VO PULSE GENERATOR RT DEVICE UNDER TEST CL RL Figure 2. Test Circuit SLS System Logic Semiconductor 4 SL74LV04 CHIP PAD DIAGRAM SL74LV04 12 11 10 09 13 14 07 1.20 ± 0.03 08 Chip marking 25LV04 (x=0.127; y=0.580) 06 01 02 03 04 05 1.35 ± 0.03 Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer) Thickness of chip 0.46 ± 0,02 mm PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 SLS System Logic Semiconductor Symbol À1 Y1 A2 Y2 A3 Y3 GND Y4 A4 Y5 A5 Y6 A6 Vcc X 0.111 0.333 0.600 0.770 1.006 1.138 1.138 1.138 1.006 0.771 0.600 0.332 0.111 0.111 Y 0.228 0.111 0.111 0.111 0.111 0.293 0.477 0.786 0.970 0.970 0.970 0.970 0.855 0.619 5