M87C196KC/M87C196KD 16-BIT HIGH-PERFORMANCE CHMOS MICROCONTROLLERS WITH ON-CHIP EPROM Special Environment M87C196KCÐ16 KBytes EPROM, 512 Bytes RAM M87C196KDÐ32 KBytes EPROM, 1024 Bytes RAM Y M87C196KC: 16 MHz Operation Y Y Dynamically Configurable 8-Bit or 16-Bit Buswidth M87C196KD: 16 and 20 MHz Operation Y Register-to-Register Architecture Y Full Duplex Serial Port 28 Interrupt Sources/16 Vectors Y High Speed I/O Subsystem Peripheral Transaction Server Y 16-Bit Timer 1.4 ms 16 x 16 Multiply (20 MHz) Y 16-Bit Up/Down Counter with Capture 1.75 ms 16 x 16 Multiply (16 MHz) Y 3 Pulse-Width-Modulated Outputs Y 2.4 ms 32/16 Divide (20 MHz) Y Four 16-Bit Software Timers 3.0 ms 32/16 Divide (16 MHz) Y Y Y Powerdown and Idle Modes 8- or 10-Bit A/D Converter with Sample/Hold Y Five 8-Bit I/O Ports HOLD/HLDA Bus Protocol Y Y Product Grades Ð SE1 (QML): b 55§ C to a 125§ C Ð SE2 (QML): b 40§ C to a 125§ C (M87C196KD only) Y Y Y Y Y 16-Bit Watchdog Timer Y Available in 68-Lead PGA and 68-Lead Ceramic Quad Flatpack Packages The M87C196KC/KD 16-bit microcontroller is a high performance member of the MCSÉ-96 microcontroller family. The M87C196KC/KD is an enhanced M80C196KB device with on-chip RAM and EPROM. Intel’s CHMOS III-E process provides a high performance processor along with low power consumption. Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are available for pulse or waveform generation. The high-speed output can also generate four software timers or start an A/D conversion. Events can be based on the timer or up/down counter. For bus design information, configuration, and programming, please see the 8XC196KC/8XC196KD User’s Manual (order Ý272238). MCSÉ-96 is a registered trademark of Intel Corporation. *Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. COPYRIGHT © INTEL CORPORATION, 1996 February 1996 Order Number: 271116-005 M87C196KC/M87C196KD 271116 – 1 Figure 1. M87C196KC/KD Block Diagram PACKAGING PGA CQFP Signal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 ACH7/P0.7 ACH6/P0.6 ACH2/P0.2 ACH0/P0.0 ACH1/P0.1 ACH3/P0.3 NMI EA VCC VSS XTAL1 XTAL2 CLKOUT BUSWIDTH INST ALE/ADV RD AD0/P3.0 AD1/P3.1 AD2/P3.2 AD3/P3.3 AD4/P3.4 AD5/P3.5 PGA CQFP 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Signal PGA CQFP Signal AD6/P3.6 AD7/P3.7 AD8/P4.0 AD9/P4.1 AD10/P4.2 AD11/P4.3 AD12/P4.4 AD13/P4.5 AD14/P4.6 AD15/P4.7 T2CLK/P2.3 READY T2RST/P2.4/AINC BHE/WRH WR/WRL PWM0/P2.5 T2CAPTURE/P2.7/PACT VPP VSS HS0.3 HS0.2 T2UP-DN/P2.6 P1.7/HOLD 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 P1.6/HLDA P1.5/BREQ HSO.1 HSO.0 HSO.5/HSI.3 HSO.4/HSI.2 HSI.1 HSI.0 P1.4/PWM2 P1.3/PWM1 P1.2 P1.1 P1.0 TXD/P2.0 RXD/P2.1 RESET EXTINT/P2.2 VSS VREF ANGND ACH4/P0.4 ACH5/P0.5 Figure 2. Pin Definitions 2 M87C196KC/M87C196KD PACKAGING The M87C196KC/KD is available in a ceramic pin grid array, shown in Figure 3, and a leaded ceramic quad pack shown in Figure 4. 271116 – 33 Figure 3. 68-Pin Grid Array Pinout 3 M87C196KC/M87C196KD 271116 – 2 Figure 4. 68-Pin Ceramic Quad Flatpack 4 M87C196KC/M87C196KD PIN DESCRIPTIONS Symbol Name and Function VCC Main supply voltage (5V). VSS Digital circuit ground (0V). There are three VSS pins, all of which must be connected. VREF Reference voltage for the A/D converter (5V). VREF is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as VSS. VPP Timing pin for the return from powerdown circuit. Connect this pin with a 1 mF capacitor to VSS and a 1 MX resistor to VCC. If this function is not used VPP may be tied to VCC. This pin is the programming voltage on the EPROM device. XTAL1 Input of the oscillator inverter and of the internal clock generator. XTAL2 Output of the oscillator inverter. CLKOUT Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator frequency. RESET Reset input to the chip. BUSWIDTH Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus. NMI A positive transition causes a vector through 203EH. INST Output high during an external memory read indicates the read is an instruction fetch. INST is valid throughout the bus cycle. INST is activated only during external memory accesses and output low for a data fetch. EA Input for memory select (External Access). EA equal to a TTL-high causes memory accesses to locations 2000H through 5FFFH to be directed to on-chip EPROM. EA equal to a TTL-low causes accesses to those locations to be directed to off-chip memory. ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide a signal to demultiplex the address from the address/data bus. When the pin is ADV, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during external memory accesses. RD Read signal output to external memory. RD is activated only during external memory reads. WR/WRL Write and Write Low output to external memory, as selected by the CCR. WR will go low for every external write, while WRL will go low only for external writes where an even byte is being written. WR/WRL is activated only during external memory writes. BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCR. BHE e 0 selects the bank of memory that is connected to the high byte of the data bus. A0 e 0 selects the bank of memory that is connected to the low byte of the data bus. Thus accesses to a 16-bit wide memory can be to the low byte only (A0 e 0, BHE e 1), to the high byte only (A0 e 1, BHE e 0), or both bytes (A0 e 0, BHE e 0). If the WRH function is selected, the pin will go low if the bus cycle is writing to an odd memory location. BHE/WRH is valid only during 16-bit external memory write cycles. 5 M87C196KC/M87C196KD PIN DESCRIPTIONS (Continued) Symbol 6 Name and Function READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory, or for bus sharing. When the external memory is not being used, READY has no effect. HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2, HSI.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit. Port 0 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. Port 1 8-bit quasi-bidirectional I/O port. Port 2 8-bit multi-functional port. All of its pins are shared with other functions in the M87C196KC. Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups. HOLD Bus Hold input requesting control of the bus. HLDA Bus Hold acknowledge output indicating release of the bus. BREQ Bus Request output activated when the bus controller has a pending external memory cycle. M87C196KC/M87C196KD ELECTRICAL CHARACTERISTICS NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. Absolute Maximum Ratings* Case Temperature Under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 55§ C to a 125§ C *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 150§ C Voltage On Any Pin to VSS ÀÀÀÀÀÀÀÀ b 0.5V to a 7.0V Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W OPERATING CONDITIONS Symbol Min Max Units Case Temperature (Instant On) b 55 a 125 §C TC (SE2) Case Temperature (Instant On) b 40 a 125 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.50 5.50 V FOSC Oscillator Frequency 3.5 16 MHz FOSC Oscillator Frequency (M87C196KD-20 only) 3.5 20 MHz TC (SE1) Description NOTE: ANGND and VSS should be nominally at the same potential. DC Characteristics Symbol (Over Specified Operating Conditions) Description VIL Input Low Voltage VIH Input High Voltage (Note 1) VIH1 Input High Voltage on XTAL 1, EA VIH2 Input High Voltage on RESET VOL Output Low Voltage VOL1 Output Low Voltage in RESET on P2.5 (Note 2) Min Max Units Test Conditions b 0.5 0.8 V 0.2 VCC a 1.0 VCC V 0.7 VCC VCC V 2.32 VCC V 0.3 0.45 1.5 V V V IOL e 200 mA IOL e 2.8 mA IOL e 7 mA 0.8 V IOL e a 0.4 mA NOTES: 1. All pins except RESET, XTAL1 and EA. 2. Violating these specifications in Reset may cause the part to enter test modes. 7 M87C196KC/M87C196KD DC Characteristics Symbol (Over Specified Operating Conditions) (Continued) Description Min Max Units Test Conditions VOH Output High Voltage (Standard Outputs) VCC b 0.3 VCC b 0.7 VCC b 1.5 V V V IOH e b 200 mA IOH e b 3.2 mA IOH e b 7 mA VOH1 Output High Voltage (Quasi-bidirectional Outputs) VCC b 0.3 VCC b 0.7 VCC b 1.5 V V V IOH e b 10 mA IOH e b 30 mA IOH e b 60 mA VOH2 Output High Voltage in RESET on P2.0 (Note 7) 2.0 V IOH e b 0.8 mA ILI Input Leakage Current (Std. Inputs) ILI1 Input Leakage Current (Port 0) g 10 mA 0 k VIN k VCC b 0.3V g3 mA 0 k VIN k VREF b 650 mA VIN e 2.0V ITL 1 to 0 Transition Current (QBD Pins) IIL Logical 0 Input Current (QBD Pins) b 70 mA VIN e 0.45V IIH Logical 1 Input Current (NMI Pin) 250 mA VIN e VCC b 0.3V ICC Active Mode Current in Reset 75 93 mA mA XTAL1 e 16 MHz XTAL1 e 20 MHz IREF A/D Converter Reference Current 5 mA VCC e VPP e VREF e 5.5V IIDLE Idle Mode Current 30 mA IPD Powerdown Mode Current 70 mA VCC e VPP e VREF e 5.5V RRST Reset Pullup Resistor 65K X VCC e 5.5V, VIN e 4.0V CS Pin Capacitance (Any Pin to VSS) 10 pF 6K NOTES: (Notes apply to all specifications) 1. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7. 2. Standard Outputs include AD0–15, RD, WR, ALE, BHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4, TXD/P2.0, and RXD (in serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs. 3. Standard Inputs include HSI pins, READY, BUSWIDTH, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3, and T2RST/P2.4. 4. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held below VCC b 0.7V: IOL on Output pins: 10 mA IOH on quasi-bidirectional pins: self limiting IOH on Standard Output pins: 10 mA 5. Maximum current per bus pin (data and control) during normal operation is g 3.2 mA. 6. During normal (non-transient) conditions the following total current limits apply: IOH is self limiting Port 1, P2.6 IOL: 29 mA IOH: 26 mA HSO, P2.0, RXD, RESET IOL: 29 mA IOL: 13 mA IOH: 11 mA P2.5, P2.7, WR, BHE IOH: 52 mA AD0 – AD15 IOL: 52 mA IOH: 13 mA RD, ALE, INST–CLKOUT IOL: 13 mA 7. Violating these specifications in Reset may cause the part to enter test modes. 8 M87C196KC/M87C196KD ICC Max e 3.88 c FREQ a 8.43 IIDLE Max e 1.65 c FREQ a 2.2 271116 – 21 Figure 5. ICC and IIDLE vs Frequency AC Characteristics For use over specified operating conditions. The system must meet these specifications to work with the M87C196KC/KD: Symbol Description TAVYV Address Valid to READY Setup TLLYV ALE Low to READY Setup TYLYH Non READY Time TCLYX READY Hold after CLKOUT Low TLLYX READY Hold after ALE Low TAVGV Address Valid to Buswidth Setup TLLGV ALE Low to Buswidth Setup TCLGX Buswidth Hold after CLKOUT Low TAVDV Address Valid to Input Data Valid TRLDV TCLDV TRHDZ End of RD to Input Data Float TRXDX Data Hold after RD Inactive Min Max Units 2 TOSC b 75 ns TOSC b 75 No upper limit Notes ns ns 0 TOSC b 30 ns (Note 1) TOSC b 15 2 TOSC b 40 ns (Note 1) 2 TOSC b 75 ns TOSC b 65 ns 0 ns 3 TOSC b 55 ns (Note 2) RD Active to Input Data Valid TOSC b 26 ns (Note 2) CLKOUT Low to Input Data Valid TOSC b 50 ns TOSC b 5 0 ns ns NOTES: 1. If max is exceeded, additional wait states will occur. 2. If wait states are used, add 2 TOSC * N, where N e number of wait states. 3. Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16 MHz. 9 M87C196KC/M87C196KD AC Characteristics (Continued) For user over specified operating conditions. The M87C196KC/KD will meet these specifications: Symbol Description Min Max Units Notes FXTAL Frequency on XTAL1 3.5 3.5 16 20 MHz MHz KC/KD-16 KD-20 TOSC 1/FXTAL 62.5 50 286 286 ns ns KC/KD-16 KD-20 TXHCH XTAL1 High to CLKOUT High or Low 110 ns TCLCL CLKOUT Cycle Time 10 2 TOSC ns TOSC b 10 TOSC a 20 TCHCL CLKOUT High Period TCLLH CLKOUT Falling Edge to ALE Rising b5 15 ns ns TLLCH ALE Falling Edge to CLKOUT Rising b 29 a 15 ns TLHLH ALE Cycle Time 4 TOSC ns TLHLL ALE High Period TOSC b 10 TAVLL Address Setup to ALE Falling Edge TOSC b 15 TLLAX Address Hold after ALE Falling Edge TOSC b 49 ns TLLRL ALE Falling Edge to RD Falling Edge TOSC b 36 ns TRLCL RD Low to CLKOUT Falling Edge TRLRH RD Low Period 0 TOSC a 15 30 TOSC b 5 TOSC ns ns ns (Note 3) TOSC a 25 ns (Note 1) 15 30 ns ns KC-16 KD-16/20 TRHLH RD Rising Edge to ALE Rising Edge TRLAZ RD Low to Address Float TLLWL ALE Falling Edge to WR Falling Edge TCLWL CLKOUT Low to WR Falling Edge TQVWH Data Stable to WR Rising Edge TCHWH CLKOUT High to WR Rising Edge TWLWH WR Low Period TOSC b 30 TWHQX Data Hold after WR Rising Edge TOSC b 30 TWHLH WR Rising Edge to ALE Rising Edge TOSC b 10 TWHBX BHE, INST after WR Rising Edge TOSC b 10 ns TWHAX AD8–15 HOLD after WR Rising TOSC b 50 ns TRHBX BHE, INST after RD Rising Edge TOSC b 10 ns TRHAX AD8–15 HOLD after RD Rising TOSC b 25 ns TOSC b 10 0 ns 25 ns 15 ns TOSC b 23 b 10 ns (Note 3) ns TOSC a 15 ns NOTES: 1. Assuming back-to-back bus cycles. 2. 8-Bit bus only. 3. If wait states are used, add 2 TOSC * N, where N e number of wait states. 4. Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16 MHz. 10 (Note 3) (Note 1) (Note 2) (Note 2) M87C196KC/M87C196KD 271116 – 22 Figure 6. System Bus Timings 11 M87C196KC/M87C196KD 271116 – 23 Figure 7. READY Timings (One Waitstate) 271116 – 24 Figure 8. Buswidth Timings 12 M87C196KC/M87C196KD HOLD/HLDA Timings Symbol Description Min Max THVCH HOLD Setup TCLHAL CLKOUT Low to HLDA Low b 15 55 TCLBRL CLKOUT Low to BREQ Low b 15 THALAZ HLDA Low to Address Float THALBZ HLDA Low to BHE, INST, RD, WR Weakly Driven TCLHAH CLKOUT Low to HLDA High b 15 TCLBRH CLKOUT Low to BREQ High b 15 15 THAHAX HLDA High to Address No Longer Float b 15 THAHBV HLDA High to BHE, INST, RD, WR Valid b 10 TCLLH CLKOUT Low to ALE High b5 15 Units Notes ns (Note 1) ns 15 ns 10 ns 15 ns 15 ns ns ns ns 15 ns NOTE: 1. To guarantee recognition at next clock. DC SPECIFICATIONS IN HOLD Min Weak Pullups on ADV, RD, WR, WRL, BHE Weak Pulldowns on ALE, INST Max Units 50K 250K VCC e 5.5V, VIN e 0.45V 10K 50K VCC e 5.5V, VIN e 2.4 271116 – 25 Figure 9. HOLD/HLDA Timings 13 M87C196KC/M87C196KD EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units Notes 1/TXLXL Oscillator Frequency 3.5 3.5 16.0 20.0 MHz MHz KC/KD-16 KD-20 TXLXL Oscillator Frequency 62.5 50 286 286 ns KC/KD-16 KD-20 TXHXX High Time 22 17 ns ns KC/KD-16 KD-20 TXLXX Low Time 22 17 ns ns KC/KD-16 KD-20 TXLXH Rise Time 10 ns TXHXL Fall Time 10 ns 271116 – 26 Figure 10. External Clock Drive Waveforms 271116 – 27 AC Testing inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0’’ Timing measurements are made at 2.0V for a Logic ‘‘1’’ and 0.8V for a Logic ‘‘0’’. 271116 – 28 For Timing Purposes a Port Pin is no Longer Floating when a 100 mV change from Load Voltage Occurs and Begins to Float when a 100 mV change from the Loaded VOH/VOL Level occurs IOL/IOH e g 15 mA. Figure 11. AC Testing Input, Output Waveforms Figure 12. Float Waveforms EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. Conditions: HÐ High LÐ Low VÐ Valid XÐ No Longer Valid ZÐ Floating Signals: AÐ Address BÐ BHE CÐ CLKOUT DÐ DATA GÐ Buswidth HÐ HOLD HAÐ HLDA 14 LÐ ALE/ADV BRÐ RÐ WÐ XÐ YÐ QÐ BREQ RD WR/WRH/WRL XTAL1 READY Data Out M87C196KC/M87C196KD AC CHARACTERISTICSÐSERIAL PORTÐSHIFT REGISTER MODE SERIAL PORT TIMINGÐSHIFT REGISTER MODE Symbol Parameter Min Max Units TXLXL Serial Port Clock Period (BRR t 8002H) TXLXH Serial Port Clock Falling Edge to Rising Edge (BRR t 8002H) TXLXL Serial Port Clock Period (BRR e 8001H) 4 TOSC ns TXLXH Serial Port Clock Falling Edge to Rising Edge (BRR e 8001H) 2 TOSC g 50 ns TQVXH Output Data Setup to Clock Rising Edge 2 TOSC b 50 ns TXHQX Output Data Hold after Clock Rising Edge 2 TOSC b 50 TXHQV Next Output Data Valid after Clock Rising Edge TDVXH Input Data Setup to Clock Rising Edge TXHDX Input Data Hold after Clock Rising Edge TXHQZ Last Clock Rising to Output Float 6 TOSC ns 4 TOSC g 50 ns ns 2 TOSC a 50 ns TOSC a 50 ns 0 ns 1 TOSC ns WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE 271116 – 29 Figure 13. Serial Port WaveformÐShift Register Mode THERMAL CHARACTERISTICS M87C196KC Package Type PGA CQFP ija M87C196KD ijc ija ijc 29.5§ C/W 6§ C/W 29§ C/W 4§ C/W 30§ C/W 9.5§ C/W 30§ C/W 11§ C/W All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operation conditions and application. See the Intel Packaging Handbook (order number 240800) for a description of Intel’s thermal impedance test methodology. 15 M87C196KC/M87C196KD EPROM SPECIFICATIONS AC EPROM Programming Characteristics Operating Conditions: Load Capacitance e 150 pF, TA e a 25§ C g 5§ C, VCC, VREF e 5V, VSS, ANGND e 0V, VPP e 12.50V g 0.25V, EA e 12.50V g 0.25V Symbol Description Min Max Units TSHLL Reset High to First PALE Low TLLLH PALE Pulse Width 1100 TOSC 50 TOSC TAVLL TLLAX Address Setup Time 0 TOSC Address Hold Time 100 TOSC TPLDV PROG Low to Word Dump Valid 50 TOSC TPHDX Word Dump Data Hold 50 TOSC TDVPL Data Setup Time 0 TOSC TPLDX Data Hold Time 400 TOSC TPLPH(2) PROG Pulse Width 50 TOSC TPHLL PROG High to Next PALE Low 220 TOSC TLHPL PALE High to PROG Low 220 TOSC TPHPL PROG High to Next PROG Low 220 TOSC TPHIL PROG High to AINC Low 0 TOSC TILIH AINC Pulse Width 240 TOSC TILVH PVER Hold after AINC Low 50 TOSC TILPL AINC Low to PROG Low 170 TPHVL PROG High to PVER Valid TOSC 220 TOSC NOTES: 1. Run Time Programming is done with Fosc e 6.0 MHz to 12.0 MHz, VREF e 5V g 0.50V. TA e a 25§ C to g 5§ C and VPP e 12.50V. 2. This specification is for the Word Dump Mode. For programming pulses, use 300 TOSC a 100 ms. DC EPROM Programming Characteristics Symbol IPP Description VPP Supply Current (When Programming) Min Max Units 100 mA NOTE: VPP must be within 1V of VCC while VCC k 4.5V. VPP must not have a low impedance path to ground of VSS while VCC l 4.5V. 16 M87C196KC/M87C196KD Erasing the M87C196KC/KD EPROM Initially, and after each erasure, all bits of the M87C196KC/KD are in the ‘‘1’’ state. Data is introduced by selectively programming ‘‘0s’’ into the desired bit locations. Although only ‘‘0s’’ will be programmed, both ‘‘1s’’ and ‘‘0s’’ can be present in the data word. The only way to change a ‘‘0’’ to a ‘‘1’’ is by ultraviolet light erasure. The erasure characteristics of the M87C196KC/KD are such that erasure begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms (Ð). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000–4000 Ð range. Constant exposure to room level fluorescent lighting could erase the typical M87C196KC/KD in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M87C196KC/KD is to be exposed to light for extended periods of time, opaque labels must be placed over the EPROM’s window to prevent unintentional erasure. The recommended erasure procedure for the M87C196KC/KD is exposure to shortwave ultraviolet light which has a wavelength of 2537 Ð. The integrated dose (i.e., UV intensity c exposure time) for erasure should be a minimum of 15 Wsec/cm2. The erasure time with this dosage is approximately 35 to 60 minutes using an ultraviolet lamp with a 12000 mW/cm2 power rating. The M87C196KC/KD should be placed within 1 inch of the lamp tubes during erasure. The maximum integrated dose an M87C196KC/KD can be exposed to without damage is 7258 Wsec/cm2 (1 week @ 12000 mW/cm2). Exposure of the M87C196KC/KD to high intensity UV light for long periods may cause permanent damage. EPROM PROGRAMMING WAVEFORMS 271116 – 30 Figure 14. Slave Programming Mode Data Program Mode with Single Program Pulse 17 M87C196KC/M87C196KD 271116 – 31 Figure 15. Slave Programming Mode in Word Dump with Auto Increment 271116 – 32 Figure 16. Slave Programming Mode Timing in Data Program with Repeated Prog Pulse and Auto Increment 18 M87C196KC/M87C196KD 10-BIT A/D CHARACTERISTICS The speed of the A/D converter in the 10-bit mode can be adjusted by setting a clock prescaler on or off. At high frequencies more time is needed for the comparator to settle. The maximum frequency with the clock prescaler disabled is 6 MHz. The conversion times with the prescaler turned on or off is shown in the table below. The ADÐTIME register has not been characterized for the 10-bit mode. of VREF. VREF must be close to VCC since it supplies both the resistor ladder and the digital section of the converter. A/D CONVERTER SPECIFICATIONS The specifications given below assume adherence to the Operating Conditions section of this data sheet. Testing is performed with VREF e 5.12V. The converter is ratiometric, so the absolute accuracy is dependent on the accuracy and stability Clock Prescaler On IOC2.4 e 0 Clock Prescaler Off IOC2.4 e 1 156.5 States 19.5 ms @ 16 MHz 89.5 States 29.8 ms @ 6 MHz Parameter Typical(3) Resolution Absolute Error Minimum Maximum Units* 1024 10 1024 10 Levels Bits 0 g8 LSBs Full Scale Error g3 LSBs Zero Offset Error g3 LSBs Non-Linearity 0 g8 LSBs Differential Non-Linearity Error l b1 a2 LSBs Channel-to-Channel Matching 0 g1 LSBs Repeatability g 0.25 LSBs Temperature Coefficients: Offset Full Scale Differential Non-Linearity 0.009 0.009 0.009 LSB/§ C LSB/§ C LSB/§ C Off Isolation b 60 Notes dB 1, 2 Feedthrough b 60 dB 1 VCC Power Supply Rejection b 60 dB 1 Input Resistance 750 1.2K X DC Input Leakage 0 3.0 mA Sample Time: Prescaler On Prescaler Off 16 8 States States Input Capacitance 3 pF NOTES: *An ‘‘LSB’’, as used here, has a value of approximately 5 mV. 1. DC to 100 KHz. 2. Multiplexer Break-Before-Make Guaranteed. 3. Typical values are expected for most devices at 25§ C. 19 M87C196KC/M87C196KD 8-BIT MODE A/D CHARACTERISTICS Sample Time 20 States The 8-bit mode trades off resolution for a faster conversion time. The ADÐTIME register must be used when performing an 8-bit conversion. The following specifications are tested with OA6H in ADÐTIME. Parameter @ A6H in ADÐTIME 9.8 ms @ 16 MHz 16 MHz Typical Minimum Maximum Units* 256 8 256 8 Levels Bits 0 g2 LSBs Resolution Absolute Error Full Scale Error g1 Zero Offset Error g2 LSBs LSBs Non-Linearity Differential Non-Linearity Error 0 g2 LSBs l b1 a1 LSBs g1 LSBs Channel-to-Channel Matching Repeatability g 0.25 LSBs Temperature Coefficients: Offset Full Scale Differential Non-Linearity 0.003 0.003 0.003 LSB/§ C LSB/§ C LSB/§ C NOTES: *An ‘‘LSB’’, as used here, has a value of approximately 20 mV. 1. Typical values are expected for most devices at 25§ C. 20 Convert Time 56 States Notes M87C196KC/M87C196KD M87C196KC DESIGN INFORMATION M87C196KC Enhanced Feature Set over the M80C196KB 1. The M87C196KC has twice the RAM of the M80C196KB and 16 Kbytes of EPROM. Also, a Vertical Register Windowing Scheme allows the extra 256 bytes of RAM to be used as registers. This greatly reduces the context switching time. 2. Peripheral Transaction Server (PTS). The PTS is an alternative way to service an interrupt, reducing latency and overhead. Each interrupt can be mapped to its PTS channel, which acts like a DMA channel. Each interrupt can now do a single or block transfer, without executing an interupt service routine. Special PTS modes exist for the A/D converter, HSI, and HSO. 3. Two extra Pluse Width Modulated outputs. The M87C196KC has added 2 PWM outputs that are functionally compatible to the 80C196KB PWM. 4. Timer2 Internal Clocking. Timer2 can now be clocked with an internal source, every 1 or 8 state times. 5. The A/D can now perform an 8- as well as a 10-bit conversion. This trades off resolution for a faster conversion time. 6. Additional On-chip Memory Security. Two UPROM (Uneraseable Programmable Read Only Memory) bits can be programmed to disable the bus controller for external code and data fetches. Once programmed, a UPROM bit cannot be erased. By shutting off the bus controller for external fetches, no one can try and gain access to your code by executing from external memory. 7. New Instructions. The M87C196KC has 5 new instructions. An exchange (XCHB/XCHW) instruction swaps two memory locations, an Interruptable Block Move Instruction (BMOVI), a Table Indirect Jump (TIJMP) instruction, and two instructions for enabling and disabling the PTS (EPTS/DPTS). M80C196KB TO M87C196KC DESIGN CONSIDERATIONS 1. Memory Map. The M87C196KC has 512 bytes of RAM/SFRs and 16K of EPROM. The extra 256 bytes of RAM will reside in locations 100H–1FFH and the extra 8K of EPROM will reside in locations 4000H–5FFFH. These locations are external memory on the M80C196KB. 2. EPROM programming. The M87C196KC has a different programming algorithm to support 16K of on-board memory. 3. ONCE Mode Entry. The ONCE mode is entered on the M87C196KC by driving the TXD pin low on the rising edge of RESET. The TXD pin is held high by a pullup that is specified at 1.4 mA and remain at 2.0V. This Pullup must not be overridden or the M87C196KC will enter the ONCE mode. 4. During the bus HOLD state, the M87C196KC weakly holds RD, WR, ALE, BHE and INST in their inactive states. The 80C196KB only holds ALE in its inactive state. 5. A RESET pulse from the M87C196KC is 16 states rather than 4 states as on the 80C196KB (i.e., a watchdog timer overflow). This provides a longer RESET pulse for other devices in the system. 6. The CDE pin on the KB has become a VSS pin on the KC to support 16 MHz operation. M87C196KC ERRATA 1. Missed EXTINT on P0.7. The 80C196KC20 could possibly miss an EXTINT on P0.7. See faxback Ý2049. 2. HISÐMODE divide-by-eight. See Faxback Ý2192. 3. IPD hump. See Faxback Ý2311. 21 M87C196KC/M87C196KD M87C196KD DESIGN INFORMATION M87C196KD Enhancements over the M87C196KC The M87C196KD is an enhanced, pin-for-pin compatible upgrade to the M87C196KC. The M87C196KD offers the same functionality, packages, and pin-outs as the M87C196KC with twice the on-chip EPROM and register RAM. 1. Doubling the on-chip EPROM to 32 KBytes allows for larger on-chip programs. 2. Doubling the on-chip RAM to 1000 bytes allows for faster and more optimized code execution. M87C196KC TO M87C196KD DESIGN CONSIDERATIONS Due to the added memory, a few memory-specific functions have been modified on the M87C196KD. 1. The AC characteristic RD Low to Address Float (TRLAZ) maximum has been increased from 15 ns on the M87C196KC to 30 ns on the M87C196KD. 2. The memory map is expanded to accommodate the additional memory. Because the added memory resides in memory locations that were always external to the M87C196KC, M87C196KC code may have to be modified to run on the M87C196KD. 3. The vertical windowing map is extended to allow all 1000 bytes of register RAM to be windowed into the lower register file. 4. The M87C196KD has a different autoprogramming algorithm to support 32 KBytes of on-chip EPROM. 22 M87C196KC/M87C196KD NEW M87C196KC/KD FEATURE DATASHEET REVISION HISTORY A CLKOUT disable bit has been added to the IOC3 SFR. This can be used to reduce noise in systems that do not require the CLKOUT signal. Figure 17 indicates the placement of the new bit. The changes made since the October 1992 revision of the M87C196KC datasheet (271116-004) are as follows: 1. Added M87C196KD information. 2. Deleted the memory map figure.* 3. Deleted the horizontal windowing figure.* 4. Deleted the SFR bit summaries.* 5. Added the new CLKOUT disable feature. 6. Modified the VIH2 and ICC DC specifications. 7. Modified the TLLYV, TLLGV, TRLDV, TRHDZ, TLLCH, TLHLL, TLLAX, TLLRL, TRLAZ, and TWHQX AC specifications. 8. Modified the THALBZ and THAHAX HOLD/HLDA specifications. 9. Added the package thermal characteristics. *See the 87C196KC/KD User’s Manual (order Ý272238) for this information. 271116 – 34 NOTE: *RSVÐReserved bits must be e 0 Figure 17. M87C196KD New SFR Bit (CLKOUT Disable) 23