INTEL VS28F016SV

VS28F016SV, MS28F016SV
16-Mbit (1-Mbit x 16, 2-Mbit x 8) FlashFile TM MEMORY
Y
Y
VS28F016SV
Ð b 40§ C to a 125§ C
Ð SE2 Grade
MS28F016SV
Ð b 55§ C to a 125§ C
Ð QML Certified
Ð SE1 Grade
Y
SmartVoltage Technology
Ð User-Selectable 3.3V or 5V VCC
Ð User-Selectable 5V or 12V VPP
Y
Three Voltage/Speed Options
Ð 80 ns Access Time, 5.0V g 5%
Ð 85 ns Access Time, 5.0V g 10%
Ð 120 ns Access Time, 3.3V g 10%
Y
1 Million Erase Cycles per Block
Typical
Y
14.3 MB/sec Burst Write Transfer Rate
Y
Configurable x8 or x16 Operation
Y
56-Lead SSOP Plastic Package
Y
Backwards-Compatible with VE28F008,
M28F008 and 28F016SA Command Set
Y
Revolutionary Architecture
Ð Multiple Command Execution
Ð Write During Erase
Ð Command Super-Set of the Intel
VE28F008, M28F008
Ð Page Buffer Write
Y
Multiple Power Savings Modes
Y
Two 256-Byte Page Buffers
Y
State-of-the-Art 0.6 mm ETOX TM IV
Flash Technology
Intel’s VS/MS28F016SV, 16-Mbit FlashFiIe TM Memory is the latest member of Intel’s high density, high performance memory family for the Industrial, Special Environment, and Military markets. Its user selectable VCC
and VPP (SmartVoltage Technology), innovative capabilities, 100% compatibility with the VE28F008 and
M28F008, multiple power savings modes, selective block locking, and very fast read/write performance make
it the ideal choice for any applications that need a high density and a wide temperature range memory device.
The VS/MS28F016SV is the ideal choice for designers who need to break free from the dependence on slow
rotating media or battery backed up memory arrays.
With two product grades (SE1: b 55§ C to a 125§ C, and SE2: b 40§ C to a 125§ C) available, the
VS/MS28F016SV is perfect for the non-PC industries like Telecommunications, Embedded/Industrial, Automotive, Navigation, Wireless Communication, Commercial Aircraft, and all Military programs.
The VS/MS28F016SV’s x8/x16 architecture allows for the optimization of the memory to processor interface.
The flexible block locking options enable bundling of executable application software in a Resident Flash Array
(RFA), PCMCIA Memory or ATA Cards or Memory modules.
The VS/MS28F016SV is offered in a 56-lead SS0P (Shrink Small Outline Package) and is manufactured on
Intel’s 0.6 mm ETOX TM IV process technology.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 1995
December 1995
Order Number: 271312-002
VS28F016SV, MS28F016SV FlashFile TM MEMORY
CONTENTS
PAGE
1.0 INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3
1.1 Enhanced Features ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3
1.2 Product Overview ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3
2.0 DEVICE PINOUT ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
2.1 Lead Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
3.0 MEMORY MAPS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
3.1 Extended Status Registers Memory
Map ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11
4.0 BUS OPERATIONS, COMMANDS
AND STATUS REGISTER
DEFINITIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
4.1 Bus Operations for Word-Wide
Mode (BYTEÝ e VIH) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
4.2 Bus Operations for Byte-Wide
Mode (BYTEÝ e VIL) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
4.3 VE28F008 or M28F008 Compatible
Mode Command Bus Definitions ÀÀÀÀÀ 13
4.4 VS/MS28F016SV-Performance
Enhancement Command Bus
Definitions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
4.5 Compatible Status Register ÀÀÀÀÀÀÀÀÀ 16
4.6 Global Status Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17
4.7 Block Status Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18
4.8 Device Configuration Code ÀÀÀÀÀÀÀÀÀ 19
CONTENTS
PAGE
5.0 ELECTRICAL SPECIFICATIONS ÀÀÀÀÀ 20
5.1 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀ 20
5.2 Capacitance ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21
5.3 Timing Nomenclature ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
5.4 DC Characteristics (VCC e 3.3V
g 0.5V) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25
5.5 DC Characteristics (VCC e 5.0V
g 0.5V) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28
5.6 AC CharacteristicsÐRead Only
Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31
5.7 Power-Up and Reset Timings ÀÀÀÀÀÀÀ 35
5.8 AC Characteristics for
WEÝÐControlled Command Write
Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36
5.9 AC Characteristics for
CEÝÐControlled Command Write
Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39
5.10 AC Characteristics for
WEÝÐControlled Page Buffer Write
Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42
5.11 AC Characteristics for
CEÝÐControlled Page Buffer Write
Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44
5.12 Erase and Word/Byte Write
Performance ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45
6.0 MECHANICAL SPECIFICATIONS ÀÀÀÀ 47
DEVICE NOMENCLATURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48
ADDITIONAL INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀ 48
DATA SHEET REVISION HISTORY ÀÀÀÀÀÀ 48
2
VS28F016SV, MS28F016SV FlashFile TM Memory
1.0
INTRODUCTION
The documentation of the Intel VS/MS28F016SV
memory device includes this data sheet, a detailed
user’s manual, and a number of application notes,
all of which are referenced at the end of this data
sheet.
The implementation of a new architecture, with
many enhanced features, will improve the device operating characteristics and result in greater product
reliability and ease of use.
The data sheet is intended to give an overview of
the chip feature-set and of the operating AC/DC
specifications. The 28F016SA (compatible with
VS/MS28F016SV) User’s Manual provides complete descriptions of the user modes, system interface examples and detailed descriptions of all principles of operation. It also contains the full list of
software algorithm flowcharts, and a brief section on
compatibility with the Intel VE28F008 and M28F008.
The VS/MS28F016SV incorporates SmartVoltage
technology, providing VCC operation at both 3.3V
and 5.0V and program and erase capability at VPP e
12.0V or 5.0V. Operating at VCC e 3.3V, the
VS/MS28F016SV consumes approximately one-half
the power consumption at 5.0V VCC, while 5.0V VCC
provides highest read performance capability. VPP
e 5.0V operation eliminates the need for a separate
12.0V converter, while VPP e 12.0V maximizes
write/erase performance. In addition to the flexible
program and erase voltages, the dedicated VPP
gives complete code protection with VPP s VPPLK.
1.1 Enhanced Features
Depending on system design specifications, the
VS/MS28F016SV is capable of supporting
The VS/MS28F016SV is backwards compatible with
the VE28F008 and M28F008 and offers the following enhancements:
# SmartVoltage Technology
Ð Selectable 5.0V or 12.0V VPP
# VPP Level Bit in Block Status Register
# Additional RY/BYÝ Configuration
Ð Pulse-On-Write/Erase
# Additional Upload Device Information Command
Feedback
Ð Device Revision Number
Ð Device Proliferation Code
Ð Device Configuration Code
#
#
#
#
x8/x16 Architecture
Block Locking
2 Page Buffers
Instruction Queuing
1.2 Product Overview
The VS/MS28F016SV is a high-performance,
16-Mbit (16,777,216-bit) block erasable, non-volatile
random access memory, organized as either
1 Mword x 16 or 2 Mbyte x 8. The VS/MS28F016SV
includes thirty-two 64-KB (65,536 byte) blocks or
thirty-two 32-KW (32,768 word) blocks. A chip memory map is shown in Figure 3.
Ð 80 ns access times with a VCC of 5.0V g 5% and
loading of 30 pF
Ð 85 ns access times with a VCC of 5.0V g 10%
and loading of 100 pF
Ð 120 ns access times with a VCC of 3.3V g 5%
and loading of 50 pF
A 3/5Ý input pin configures the device’s internal circuitry for optimal 3.3V or 5.0V Read/Write operation.
A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation.
Internal Algorithm Automation allows Byte/Word
Writes and Block Erase operations to be executed
using a Two-Write command sequence to the CUI in
the same way as the VE28F008 or M28F008 8-Mbit
FlashFile memory.
A super-set of commands has been added to the
basic VE28F008 or M28F008 command-set to
achieve higher write performance and provide additional capabilities. These new commands and features include:
#
#
#
#
#
#
Page Buffer Writes to Flash
Command Queuing Capability
Automatic Data Writes during Erase
Software Locking of Memory Blocks
Two-Byte Successive Writes in 8-bit Systems
Erase All Unlocked Blocks
3
VS28F016SV, MS28F016SV FlashFile TM Memory
Writing of memory data is performed in either byte or
word increments typically within 6 msec (12.0V VPP)
b a 33% improvement over the VE28F008 or
M28F008. A Block Erase operation erases one of
the 32 blocks in about 1.0 sec (12.0V VPP), independent of the other blocks, which is about a 65% improvement over the VE28F008 or M28F008.
# A Global Status Register (GSR) which informs
Each block can be written and erased a minimum of
100,000 cycles. Systems can achieve one million
Block Erase Cycles by providing wear-leveling algorithms and graceful block retirement. These techniques have already been employed in many flash
file systems and hard disk drive designs.
The GSR and BSR memory maps for Byte-Wide and
Word-Wide modes are shown in Figures 4 and 5.
The VS/MS28F016SV incorporates two Page Buffers of 256 bytes (128 words) each to allow page
data writes. This feature can improve a system write
performance by up to 4.8 times over previous flash
memory devices, which have no Page Buffers.
All operations are started by a sequence of Write
commands to the device. Three Status Registers
(described in detail later in this data sheet) and a
RY/BYÝ output pin provide information on the progress of the requested operation.
While the VE28F008 or M28F008 requires an operation to complete before the next operation can be
requested, the VS/MS28F016SV allows queuing of
the next operation while the memory executes the
current operation. This eliminates system overhead
when writing several bytes in a row to the array or
erasing several blocks at the same time. The
VS/MS28F016SV can also perform Write operations
to one block of memory while performing Erase of
another block.
the system of command Queue status, Page
Buffer status, and overall Write State Machine
(WSM) status.
# 32 Block Status Registers (BSRs) which provide
block-specific status information such as the
block lock-bit status.
The VS/MS28F016SV incorporates an open drain
RY/BYÝ output pin. This feature allows the user to
OR-tie many RY/BYÝ pins together in a multiple
memory configuration such as a Resident Flash Array.
Other configurations of the RY/BYÝ pin are enabled via special CUI commands and are described
in detail in the 16-Mbit Flash Product Family User’s
Manual.
The VS/MS28F016SV’s Upload Device Information
command is enhanced compared to the VE28F008
or M28F008, providing access to additional device
information. This command uploads the Device Revision Number, Device Proliferation Code and Device Configuration Code. The Device Proliferation
Code for the VS/MS28F016SV is 01H, and the Device Configuration Code identifies the current
RY/BYÝ configuration. Section 4.4 documents the
exact page buffer address locations for all uploaded
information. A subsequent Page Buffer Swap and
Page Buffer Read command sequence is necessary
to read the correct device information.
# A Compatible Status Register (CSR) which is
The VS/MS28F016SV also incorporates a dual chipenable function with two input pins, CE0Ý and
CE1Ý. These pins have exactly the same functionality as the regular chip-enable pin, CEÝ, on the
VE28F008 or M28F008. For minimum chip designs,
CE1Ý may be tied to ground and system logic may
use CE0Ý as the chip enable input. The
VS/MS28F016SV uses the logical combination of
these two signals to enable or disable the entire
chip. Both CE0Ý and CE1Ý must be active low to
enable the device. If either one becomes inactive,
the chip will be disabled. This feature, along with the
open drain RY/BYÝ pin, allows the system designer
to reduce the number of control pins used in a large
array of 16-Mbit devices.
100% compatible with the VE28F008 or
M28F008 FlashFile memory Status Register. The
CSR, when used alone, provides a straightforward upgrade capability to the VS/MS28F016SV
from a VE28F008- or M28F008-based design.
The BYTEÝ pin allows either x8 or x16 read/writes
to the VS/MS28F016SV. BYTEÝ at logic low selects 8-bit mode with address A0 selecting between
low byte and high byte. On the other hand, BYTEÝ
The VS/MS28F016SV provides selectable block
locking to protect code or data such as Device Drivers, PCMCIA card information, ROM-Executable
O/S or Application Code. Each block has an associated non-volatile lock-bit which determines the
lock status of the block. In addition, the
VS/MS28F016SV has a master Write Protect pin
(WPÝ) which prevents any modifications to memory
blocks whose lock-bits are set.
The VS/MS28F016SV contains three types of
Status Registers to accomplish various functions:
4
VS28F016SV, MS28F016SV FlashFile TM Memory
at logic high enables 16-bit operation with address
A1 becoming the lowest order address and address
A0 is not used (don’t care). A device block diagram
is shown in Figure 1.
The VS/MS28F016SV is specified for a maximum
access time of 80 ns (tACC) at 5.0V operation (4.75V
to 5.25V) in either the SE1 or SE2 grades. A corresponding maximum access time of 120 ns at 3.3V
(3.15V to 3.45V) is achieved for reduced power consumption applications.
The VS/MS28F016SV incorporates an Automatic
Power Saving (APS) feature which substantially reduces the active current when the device is in static
mode of operation (addresses not switching). In APS
mode, the typical ICC current is 1 mA at 5.0V (0.8 mA
at 3.3V).
A deep power-down mode of operation is invoked
when the RPÝ (called PWDÝ on the VE28F008 or
M28F008) pin transitions low. This mode brings the
device power consumption to less than 30.0 mA, typically, and provides additional write protection by
acting as a device reset pin during power transitions.
A reset time of 500 ns (5.0V VCC operation) is required from RPÝ switching high until outputs are
again valid. In the Deep Power-Down state, the
WSM is reset (any current operation will abort) and
the CSR, GSR and BSR registers are cleared.
A CMOS standby mode of operation is enabled
when either CE0Ý or CE1Ý transitions high and
RPÝ stays high with all input control pins at CMOS
levels. In this mode, the device typically draws an
ICC standby current of 70 mA at 5V VCC.
2.0
DEVICE PINOUT
The VS/MS28F016SV 56L-SSOP pinout configuration is shown in Figure 2.
5
VS28F016SV, MS28F016SV FlashFile TM Memory
271312 – 21
Figure 1. Block Diagram
6
VS28F016SV, MS28F016SV FlashFile TM Memory
2.1 Lead Descriptions
Symbol
Type
Name and Function
A0
INPUT
BYTE-SELECT ADDRESS: Selects between high and low byte when
device is in x8 mode. This address is latched in x8 Data Writes. Not
used in x16 mode (i.e., the A0 input buffer is turned off when BYTEÝ
is high).
A1 - A15
INPUT
WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte
block. A6-15 selects 1 of 1024 rows, and A1-5 selects 16 of 512
columns. These addresses are latched during Data Writes.
A16 - A20
INPUT
BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These
addresses are latched during Data Writes, Erase and Lock-Block
operations.
DQ0 - DQ7
INPUT/OUTPUT
LOW-BYTE DATA BUS: Inputs data and commands during CUI write
cycles. Outputs array, buffer, identifier or status data in the
appropriate read mode. Floated when the chip is de-selected or the
outputs are disabled.
DQ8 - DQ15
INPUT/OUTPUT
HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write
operations. Outputs array, buffer or identifier data in the appropriate
read mode; not used for Status Register reads. Floated when the
chip is de-selected or the outputs are disabled.
CE0Ý, CE1Ý
INPUT
CHIP ENABLE INPUTS: Activate the device’s control logic, input
buffers, decoders and sense amplifiers. With either CE0Ý or CE1Ý
high, the device is de-selected and power consumption reduces to
standby levels upon completion of any current Data-Write or Erase
operations. Both CE0Ý, CE1Ý must be low to select the device.
All timing specifications are the same for both signals. Device
Selection occurs with the latter falling edge of CE0Ý or CE1Ý. The
first rising edge of CE0Ý or CE1Ý disables the device.
RPÝ
INPUT
RESET/POWER-DOWN: RPÝ low places the device in a Deep
Power-Down state. All circuits that consume static power, even those
circuits enabled in standby mode, are turned off. When returning from
Deep Power-Down, a recovery time of tPHQV at 5.0V VCC is required
to allow these circuits to power-up.
When RPÝ goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to
ready (with all status flags cleared).
Exit from Deep Power-Down places the device in read array mode.
OEÝ
INPUT
OUTPUT ENABLE: Gates device data through the output buffers
when low. The outputs float to tri-state off when OEÝ is high.
NOTE:
CExÝ overrides OEÝ, and OEÝ overrides WEÝ.
WEÝ
INPUT
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data
Queue Registers and Address Queue Latches. WEÝ is active low,
and latches both address and data (command or array) on its rising
edge. Page Buffer addresses are latched on the falling edge of WEÝ.
7
VS28F016SV, MS28F016SV FlashFile TM Memory
2.1 Lead Descriptions
(Continued)
Symbol
Type
Name and Function
RY/BYÝ
OPEN DRAIN
OUTPUT
READY/BUSY: Indicates status of the internal WSM. When low, it indicates
that the WSM is busy performing an operation. RY/BYÝ floating indicates
that the WSM is ready for new operations (or WSM has completed all
pending operations), or erase is suspended, or the device is in deep powerdown mode. This output is always active (i.e., not floated to tri-state off when
OEÝ or CE0Ý, CE1Ý are high), except if a RY/BYÝ Pin Disable command
is issued.
WPÝ
INPUT
WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile lockbit for each block. When WPÝ is low, those locked blocks as reflected by
the Block-Lock Status bits (BSR.6), are protected from inadvertent data
writes or erases. When WPÝ is high, all blocks can be written or erased
regardless of the state ot the lock-bits. The WPÝ input buffer is disabled
when RPÝ transitions low (deep power-down mode).
BYTEÝ
INPUT
BYTE ENABLE: BYTEÝ low places device in x8 mode. All data is then input
or output on DQ0–7, and DQ8–15 float. Address A0 selects between the high
and low byte. BYTEÝ high places the device in x16 mode, and turns off the
A0 input buffer. Address A1, then becomes the lowest order address.
3/5Ý
INPUT
3.3/5.0 VOLT SELECT: 3/5Ý high configures internal circuits for 3.3V
operation. 3/5Ý low configures internal circuits for 5.0V operation.
NOTE:
Reading the array with 3/5Ý high in a 5.0V system could damage the
device. Reference the power-up and reset timings (Section 5.7) for 3/5Ý
switching delay to valid data.
VPP
SUPPLY
WRITE/ERASE POWER SUPPLY (12.0V g 0.6V, 5.0V g 0.5V): For erasing
memory array blocks or writing words/bytes/pages into the flash array. VPP
e 5.0V g 0.5V eliminates the need for a 12V converter, while connection to
1 2.0V g 0.6V maximizes Write/Erase Performance.
NOTE:
Successful completion of write and erase attempts is inhibited with VPP at or
below 1.5V. Write and erase attempts with VPP between 1.5V and 4.5V,
between 5.5V and 11.4V, and above 12.6V produce spurious results and
should not be attempted.
VCC
SUPPLY
DEVICE POWER SUPPLY (3.3V g 0.45V, 5.0V g 0.5V, 5.0 g 0.25V): To
switch 3.3V to 5.0V (or vice versa), first ramp VCC down to GND, and then
power to the new VCC voltage.
Do not leave any power pins floating.
GND
SUPPLY
GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins
floating.
NC
8
NO CONNECT: Lead may be driven or left floating.
VS28F016SV, MS28F016SV FlashFile TM Memory
271312 – 2
24mm x 13.5mm 0.8mm Lead Pitch
Top View
NOTE:
56-Lead SSOP Mechanical Diagrams and dimensions are shown at the end of this data sheet.
Figure 2. SSOP Pinout Configuration
9
VS28F016SV, MS28F016SV FlashFile TM Memory
3.0
MEMORY MAPS
271312 – 3
Figure 3. VS/MS28F016SV Memory Maps (Byte-Wide and Word-Wide Modes)
10
VS28F016SV, MS28F016SV FlashFile TM Memory
3.1 Extended Status Registers Memory Map
271312 – 4
Figure 4. Extended Status Register Memory Map
(Byte-Wide Mode)
271312 – 5
Figure 5. Extended Status Register Memory Map
(Word-Wide Mode)
11
VS28F016SV, MS28F016SV FlashFile TM Memory
4.0
BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
4.1 Bus Operations for Word-Wide Mode (BYTEÝ e VIH)
Notes
RPÝ
CE1Ý
CE0Ý
OEÝ
WEÝ
A1
DQ0-15
RY/BYÝ
Read
Mode
1,2,7
VIH
VIL
VIL
VIL
VIH
X
DOUT
X
Output Disable
1,6,7
VIH
VIL
VIL
VIH
VIH
X
High Z
X
Standby
1,6,7
VIH
VIL
VIH
VIH
VIH
VIL
VIH
X
X
X
High Z
X
Deep Power-Down
Manufacturer ID
Device ID
Write
1,3
VIL
X
X
X
X
X
High Z
VOH
4
VIH
VIL
VIL
VIL
VIH
VIL
0089H
VOH
4
VIH
VIL
VIL
VIL
VIH
VIH
66A0H
VOH
1,5,6
VIH
VIL
VIL
VIH
VIL
X
DIN
X
4.2 Bus Operations for Byte-Wide Mode (BYTEÝ e VIL)
Mode
Read
Notes
RPÝ
CE1Ý
CE0Ý
OEÝ
WEÝ
A0
DQ0-7
RY/BYÝ
1,2,7
VIH
VIL
VIL
VIL
VIH
X
DOUT
X
Output Disable
1,6,7
VIH
VIL
VIL
VIH
VIH
X
High Z
X
Standby
1,6,7
VIH
VIL
VIH
VIH
VIH
VIL
VIH
X
X
X
High Z
X
Deep Power-Down
Manufacturer ID
Device ID
Write
1,3
VIL
X
X
X
X
X
High Z
VOH
4
VIH
VIL
VIL
VIL
VIH
VIL
89H
VOH
4
VIH
VIL
VIL
VIL
VIH
VIH
A0H
VOH
1,5,6
VIH
VIL
VIL
VIH
VIL
X
DIN
X
NOTES:
1. X can be VIH or VIL for address or control pins except for RY/BYÝ, which is either VOL or VOH.
2. RY/BYÝ output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode.
RY/BYÝ will be at VOH if it is tied to VCC through a resistor. RY/BYÝ at VOH is independent of OEÝ while a WSM
operation is in progress.
3. RPÝ at GND g 0.2V ensures the lowest deep power-down current.
4. A0 and A1 at VIL provide device manufacturer codes in x8 and x16 modes respectively. A0 and A1 at VIH provide device
ID codes in x8 and x16 modes respectively. All other addresses are set to zero.
5. Commands for Erase, Data Write, or Lock-Block operations can only be completed successfully when VPP e VPPH1or
VPP e VPPH2.
6. While the WSM is running, RY/BYÝ in level-mode (default) stays at VOL until all operations are complete. RY/BYÝ goes
to VOH when the WSM is not busy or in erase suspend mode.
7. RY/BYÝ may be at VOL while the WSM is busy performing various operations. For example, a Status Register read
during a Write operation.
12
VS28F016SV, MS28F016SV FlashFile TM Memory
4.3 VE28F008 and M28F008 Compatible Mode Command Bus Definitions
Command
Notes
Read Array
First Bus Cycle
Oper
Addr
Data(4)
Write
X
xxFFH
Second Bus Cycle
Oper
Addr
Data(4)
Read
AA
AD
Intelligent Identiier
1
Write
X
xx90H
Read
IA
ID
Read Compatible Status Register
2
Write
X
xx70H
Read
X
CSRD
Clear Status Register
3
WD
Write
X
xx50H
Word/Byte Write
Write
X
xx40H
Write
WA
Alternate Word/Byte Write
Write
X
xx10H
Write
WA
WD
Block Erase/Confirm
Write
X
xx20H
Write
BA
xxD0H
Erase Suspend/Resume
Write
X
xxB0H
Write
X
xxD0H
ADDRESS
AA e Array Address
BA e Block Address
IA e ldentitier Address
WA e Write Address
X e Don’t Care
DATA
AD e Array Data
CSRD e CSR Data
ID e Identifier Data
WD e Write Data
NOTES:
1. Following the Intelligent Identifier command, two Read operations access the manutacturer and device signature codes.
2. The CSR is automatically available after device enters data write, erase, or suspend operations.
3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5, BSR.4 and BSR.2 bits. See Status Register definitions.
4. The upper byte of the data bus (DQ8 – 15) during command writes is a ‘‘Don’t Care’’ in x16 operation of the device.
13
VS28F016SV, MS28F016SV FlashFile TM Memory
4.4 VS/MS28F016SVÐPerformance Enhancement Command Bus Definitions
Command
Mode
Notes
First Bus Cycle
Second Bus Cycle
Oper
Addr
Data(13)
Oper
Addr
Data(13)
Read
RA
GSRD
BSRD
Read Extended
Status Register
1
Write
X
xx71H
Page Buffer Swap
7
Write
X
xx72H
Read Page Buffer
Write
X
xx75H
Read
PA
PD
Single Load to
Page Buffer
Write
X
xx74H
Write
PA
PD
Sequential Load to
Page Buffer
Page Buffer Write
to Flash
Two-Byte Write
Addr
Data
x8
4,6,10
Write
X
xxE0H
Write
X
BCL
Write
X
BCH
x16
4,5,6,10
Write
X
xxE0H
Write
X
WCL
Write
X
WCH
BC(H,L)
x8
3,4,9,10
Write
X
xx0CH
Write
A0
BC(L,H)
Write
WA
x16
4,5,10
Write
X
xx0CH
Write
X
WCL
Write
WA
WCH
x8
3
Write
X
xxFBH
Write
A0
WD(L,H)
Write
WA
WD(H,L)
Write
X
xx77H
Write
BA
xxD0H
Lock Block/
Confirm
Upload Status
Bits/Confirm
2
Write
X
xx97H
Write
X
xxD0H
Upload Device
Information/
Confirm
11
Write
X
xx99H
Write
X
xxD0H
Write
X
xxA7H
Write
X
xxD0H
Erase All Unlocked
Blocks/Confirm
RY/BYÝ Enable to
Level-Mode
8
Write
X
xx96H
Write
X
xx01H
RY/BYÝ PulseOn-Write
8
Write
X
xx96H
Write
X
xx02H
RY/BYÝ PulseOn-Erase
8
Write
X
xx96H
Write
X
xx03H
RY/BYÝ Disable
8
Write
X
xx96H
Write
X
xx04H
RY/BYÝ PulseOn-Write/Erase
8
Write
X
xx96H
Write
X
xx05H
Sleep
12
Write
X
xxF0H
Write
X
xx80H
Abort
ADDRESS
BA e Block Address
PA e Page Butter Address
RA e Extended Register Address
WA e Write Address
X e Don’t Care
14
Third Bus Cycle
Oper
DATA
AD e Array Data
PD e Page Buffer Data
BSRD e BSR Data
GSRD e GSR Data
WC (L,H) e Word Count (Low, High)
BC (L,H) e Byte Count (Low, High)
WD (L,H) e Write Data (Low, High)
VS28F016SV, MS28F016SV FlashFile TM Memory
NOTES:
1. RA can be the GSR address or any BSR address. See Figures 4 and 5 for Extended Status Register memory maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
actual lock-bit status.
3. A0 is automatically complemented to load second byte of data. BYTEÝ must be at VIL. A0 value determines which
WD/BC is supplied first: A0 e 0 looks at the WDL/BCL, A0 e 1 looks at the WDH/BCH.
4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size, and to avoid writing the
Page Buffer contents to more than one 256-byte segment within an array block. They are simply shown for future Page
Buffer expandability.
5. In x16 mode, only the lower byte DQ0-7 is used for WCL and WCH. The upper byte DQ8-15 is a don’t care.
6. PA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.
7. This command allows the user to swap between available Page Buffers (0 or 1).
8. These commands reconfigure RY/BYÝ output to one of two pulse-modes or enable and disable the RY/BYÝ function.
9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer.
Refer to the 16-Mbit Flash Product Family User’s Manual.
10. BCL e 00H corresponds to a byte count of 1. Similarly, WCL e 00H corresponds to a word count of 1.
11. After writing the Upload Device Information command and the Confirm command, the following information is output at
Page Buffer addresses specified below:
Address
Information
06H, 07H (Byte Mode)
Device Revision Number
03H (Word Mode)
Device Revision Number
1EH (Byte Mode)
Device Configuration Code
Device Configuration Code
0FH (DQ0 – 7) (Word Mode)
1FH (Byte Mode)
Device Proliferation Code (01H)
Device Proliferation Code (01H)
0FH (DQ8 – 15) (Word Mode)
A page buffer swap followed by a page buffer read sequence is necessary to access this information. The contents of
all other Page Buffer locations, after the Upload Device Information command is written, are reserved for future implementation by Intel Corporation. See Section 4.8 for a description of the Device Configuration Code. This code also
corresponds to data written to the 28F016SV after writing the RY/BYÝ Reconfiguration command.
12. To ensure that the 28F0165V’s power consumption during Sleep Mode reaches the deep power-down current level, the
system also needs to de-select the chip by taking either or both CE0Ý or CE1Ý high.
13. The upper byte of the data bus (DQ8 – 15) during command wntes is a Don’t Care in x16 operation of the device.
15
VS28F016SV, MS28F016SV FlashFile TM Memory
4.5 Compatible Status Register
WSMS
ESS
ES
DWS
VPPS
R
R
R
7
6
5
4
3
2
1
0
CSR.7 e WRITE STATE MACHINE STATUS
1 e Ready
0 e Busy
CSR.6
1
0
CSR.5
1
0
CSR.4
1
0
CSR.3
1
0
e
e
e
e
e
e
e
e
e
e
e
e
ERASE-SUSPEND STATUS
Erase Suspended
Erase In Progress/Completed
ERASE STATUS
Error In Block Erasure
Successful Block Erase
DATA-WRITE STATUS
Error in Data Write
Data Write Successful
VPP STATUS
VPP Error Detect, Operation Abort
VPP OK
NOTES:
RY/BYÝ output or WSMS bit must be checked to
determine completion of an operation (Erase, Erase
Suspend, or Data Write) before the appropriate Status bit
(ESS, ES or DWS) is checked for success.
If DWS and ES are set to ‘‘1’’ during an erase attempt, an
improper command sequence was entered. Clear the
CSR and attempt the operation again.
The VPPS bit, unlike an A/D converter, does not provide
continuous indication of VPP level. The WSM interrogates
VPP’s level only after the Data-Write or Erase command
sequences have been entered, and informs the system if
VPP has not been switched on. VPPS is not guaranteed to
report accurate feedback between VPPLK(max) and
VPPH1(min) and between VPPH1(max) and VPPH2(min)
and above VPPH2(max).
CSR.2-0 e RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the CSR.
16
VS28F016SV, MS28F016SV FlashFile TM Memory
4.6 Global Status Register
WSMS
OSS
DOS
DSS
QS
PBAS
PBS
PBSS
7
6
5
4
3
2
1
0
GSR.7 e WRITE STATE MACHINE STATUS
1 e Ready
0 e Busy
GSR.6 e OPERATION SUSPEND STATUS
1 e Operation Suspended
0 e Operation in Progress/Completed
GSR.5 e DEVICE OPERATION STATUS
1 e Operation Unsuccessful
0 e Operation Successful or Currently
Running
GSR.4 e DEVICE SLEEP STATUS
1 e Device in Sleep
0 e Device Not in Sleep
MATRIX 5/4
0 0 e Operation Successful or Currently
Running
0 1 e Device in Sleep mode or Pending
Sleep
1 0 e Operation Unsuccessful
1 1 e Operation Unsuccessful or Aborted
GSR.3
1
0
GSR.2
1
0
GSR.1
1
0
e
e
e
e
e
e
e
e
e
QUEUE STATUS
Queue Full
Queue Available
PAGE BUFFER AVAILABLE STATUS
One or Two Page Buffers Available
No Page Buffer Available
PAGE BUFFER STATUS
Selected Page Buffer Ready
Selected Page Buffer Busy
NOTES:
[1] RY/BYÝ output or WSMS bit must be checked to
determine completion of an operation (Block Lock,
Suspend, any RY/BYÝ reconfiguration, Upload Status
Bits, Erase or Data Write) before the appropriate Status
bit (OSS or DOS) is checked for success.
If operation currently running, then GSR.7 e 0.
If device pending sleep, then GSR.7 e 0.
Operation aborted: Unsuccessful due to Abort
command.
The device contains two Page Buffers.
Selected Page Buffer is currently busy with WSM
operation
GSR.0 e PAGE BUFFER SELECT STATUS
1 e Page Buffer 1 Selected
0 e Page Buffer 0 Selected
NOTE:
1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.
GSR.7 provides indication when all queued operations are completed.
17
VS28F016SV, MS28F016SV FlashFile TM Memory
4.7 Block Status Register
BS
BLS
BOS
BOAS
QS
VPPS
VPPL
R
7
6
5
4
3
2
1
0
BSR.7 e BLOCK STATUS
1 e Ready
0 e Busy
BSR.6
1
0
BSR.5
1
0
BLOCK LOCK STATUS
Block Unlocked for Write/Erase
Block Locked for Write/Erase
BLOCK OPERATION STATUS
Operation Unsuccessful
Operation Successful or
Currently Running
BSR.4 e BLOCK OPERATION ABORT STATUS
1 e Operation Aborted
0 e Operation Not Aborted
MATRIX 5/4
0 0 e Operation Successful or
Currently Running
0 1 e Not a Valid Combination
1 0 e Operation Unsuccessful
1 1 e Operation Aborted
BSR.3 e QUEUE STATUS
1 e Queue Full
0 e Queue Available
BSR.2 e VPP STATUS
1 e VPP Error Detect, Operation Abort
0 e VPP OK
BSR.1 e VPP LEVEL
1 e VPP Detected at 5.0V g 10%
0 e VPP Detected at 12.0V g 5%
NOTES:
[1] RY/BYÝ output or BS bit must be checked to
determine completion of an operation (Block Lock,
Suspend, Erase or Data Write) before the appropriate
Status bits (BOS, BLS) is checked for success.
e
e
e
e
e
e
The BOAS bit will not be set until BSR.7 e 1.
Operation halted via Abort command.
BSR.1 is not guaranteed to report accurate feedback
between the VPPH1 and VPPH2 voltage ranges. Writes
and erases with VPP between VPPLK(max) and VPPH1
(min), between VPPH1(max) and VPPH2(min), and
above VPPH2(max) produce spurious results and
should not be attempted. BSR.1 was a RESERVED bit
on the 28F016SA.
BSR.0 e RESERVED FOR FUTURE ENHANCEMENTS
This bit is reserved for future use; mask it out when polling the BSRs.
NOTE:
1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.
GSR.7 provides indication when all queued operations are completed.
18
VS28F016SV, MS28F016SV FlashFile TM Memory
4.8 Device Configuration Code
R
R
R
R
R
RB2
RB1
RB0
7
6
5
4
3
2
1
0
NOTES:
DCC.2-DCC.0 e RY/BYÝ CONFIGURATION (RB2-RB0)
Undocumented combinations of RB2-RB0
are reserved by Intel Corporation for future
001 e Level Mode (Default)
implementations and should not be used.
010 e Pulse-On-Write
011 e Pulse-On-Erase
100 e RY/BYÝ Disabled
101 e Pulse-On-Write/Erase
DCC.7-DCC.3 e RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when reading the Device Configuration Code.
Set these bits to ‘‘0’’ when writing the desired RY/BYÝ configuration to the device.
19
VS28F016SV, MS28F016SV FlashFile TM Memory
5.0
ELECTRICAL SPECIFICATIONS
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet before finalizing a design.
5.1 Absolute Maximum Ratings*
Temperature Under Bias
ÐSE1 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 55§ C to a 125§ C
ÐSE2 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 40§ C to a 125§ C
Storage Temperature ÀÀÀÀÀÀÀÀÀÀÀÀ b 65§ to a 125§ C
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
VCC e 3.3V g 0.15V Systems(4)
Min
Max
Units
TCSE2
Sym
Operating Temperature, SE2
Parameter
Notes
b 40
a 125
§C
TCSE1
Operating Temperature, SE1
b 55
a 125
§C
VCC
VCC with Respect to GND
1
b 0.2
7.0
V
1,2
b 0.2
14.0
V
b 0.5
VCC
a 0.5
V
VPP
VPP Supply Voltage with Respect to GND
V
Voltage on any Pin (except VCC,VPP) with
Respect to GND
I
Current into any Non-Supply Pin
5
g 30
mA
IOUT
Output Short Circuit Current
3
100
mA
1,5
Test Conditions
VCC e 5.0V g 0.5V, VCC e 5.0V g 0.25V Systems(4, 5)
Sym
Parameter
TCSE2
Operating Temperature, SE2
TCSE1
Operating Temperature, SE1
VCC
VCC with Respect to GND
Notes
Min
Max
Units
b 40
a 125
§C
b 55
a 125
§C
1
b 0.2
7.0
V
VPP
VPP Supply Voltage with Respect to GND
1,2
b 0.2
14.0
V
V
Voltage on any Pin (except VCC,VPP) with
Respect to GND
1,5
b 2.0
7.0
V
I
Current into any Non-Supply Pin
5
g 30
mA
IOUT
Output Short Circuit Current
3
100
mA
Test Conditions
NOTES:
1. Minimum DC voltage is b0.5V on input/output pins. During transitions, this level may undershoot to b2.0V for periods
k 20 ns. Maximum DC voltage on input/output pins is VCC a 0.5V which, during transitions, may overshoot to VCC a 2.0V
for periods k20 ns.
2. Maximum DC voltage on VPP may overshoot to a 14.0V for periods k20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
4. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.
5. This specification also applies to pin marked ‘‘NC’’.
6. 5% VCC specifications refer to the VS/MS28F016SV-80 in its high speed test configuration.
20
VS28F016SV, MS28F016SV FlashFile TM Memory
5.2 Capacitance
For a 3.3V g 0.15V System:
Notes
Typ
Max
Units
Test Conditions
CIN
Sym
Capacitance Looking into an
Address/Control Pin
Parameter
1
6
8
pF
TA e 25§ C, f e 1.0 MHz
COUT
Capacitance Looking into an
Output Pin
1
8
12
pF
TA e 25§ C, f e 1.0 MHz
CLOAD
Load Capacitance Driven by
Outputs for Timing Specifications
50
pF
For VCC e 3.3V g 0.15V
2.5
ns
50X transmission line
delay
1,2
Equivalent Load Timing Circuit
For a 5.0V System:
Notes
Typ
Max
Units
Test Conditions
CIN
Sym
Capacitance Looking into an
Address/Control Pin
Parameter
1
6
8
pF
TA e 25§ C, f e 1.0 MHz
COUT
Capacitance Looking into an
Output Pin
1
8
12
pF
TA e 25§ C, f e 1.0 MHz
CLOAD
Load Capacitance Driven by
Outputs for Timing Specifications
100
pF
For VCC e 5.0V g 0.5V
30
pF
For VCC e 5.0V g 0.25V
Equivalent Testing Load Circuit for
VCC g 10%
2.5
ns
25X transmission line
delay
Equivalent Testing Load Circuit for
VCC g 5%
2.5
ns
85X transmission line
delay
1,2
NOTES:
1. Sampled, not 100% tested. Guaranteed by design.
2. To obtain iBIS models for the VS/MS28F016SV, please contact your local Intel/Distribution Sales Office.
21
VS28F016SV, MS28F016SV FlashFile TM Memory
5.3 Timing Nomenclature
tCE
tELQV time(t) from CEÝ (E) going low (L)
to the outputs (Q) becoming valid (V)
All 3.3V system timings are measured from where
signals cross 1.5V.
tOE
For 5.0V systems use the standard JEDEC cross
point definitions.
tACC
tGLQV time(t) from OE Ý (G) going low (L)
to the outputs (Q) becoming valid (V)
tAVQV time(t) from address (A) valid (V) to
the outputs (Q) becoming valid (V)
tAS
Each timing parameter consists of 5 characters.
Some common examples are defined as follows:
tDH
tAVWH time(t) from address (A) valid (V) to
WEÝ (W) going high (H)
tWHDX time(t) from WEÝ (W) going high
(H) to when the data (D) can become undefined (X)
Pin Characters
22
Pin States
A
Address Inputs
H
High
D
Data Inputs
L
Low
Q
Data Outputs
V
Valid
E
CEÝ (Chip Enable)
X
Driven, but not Necessarily Valid
Z
High Impedance
F
BYTEÝ (Byte Enable)
G
OEÝ (Output Enable)
W
WEÝ (Write Enable)
P
RPÝ (Deep Power-Down Pin)
R
RY/BYÝ (Ready Busy)
V
Any Voltage Level
Y
3/5Ý Pin
5V
VCC at 4.5V Minimum
3V
VCC at 3.15V Minimum
VS28F016SV, MS28F016SV FlashFile TM Memory
271312 – 6
AC test inputs are driven at VOH (2.4 VTTL) for a Logic ‘‘1’’ and VOL (0.45 VTTL) for a Logic ‘‘0.’’ Input timing begins at
VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) k10 ns.
Figure 6. Transient Input/Output Reference Waveform for
VCC e 5.0V g 10% (Standard Testing Configuration)
271312 – 7
AC test inputs are driven at 3.15V for a Logic ‘‘1’’ and 0.0V for a Logic ‘‘0.’’ Input timing begins, and output timing ends,
at 1.5V. Input rise and fall times (10% to 90%) k10 ns.
Figure 7. Transient Input/Output Reference Waveform (VCC e 3.3V g 0.15V)
High Speed Reference Waveform (VCC e 5.0V g 5%)
NOTE:
1. Testing characteristics for VS/MS28F016SV-085 (Standard Testing Configuration) and VS/MS28F016SV-100.
23
VS28F016SV, MS28F016SV FlashFile TM Memory
2.5 ns of 25X Transmission Line
Total Capacitance e 100 pF
271312 – 8
Figure 8. Transient Equivalent Testing Load Circuit (VCC e 5.0V g 10%)
2.5 ns of 50X Transmission Line
Total Capacitance e 50 pF
271312 – 9
Figure 9. Transient Equivalent Testing Load Circuit (VCC e 3.3V g 0.15V)
2.5 ns of 83X Transmission Line
Total Capacitance e 30 pF
271312 – 10
Figure 10. High Speed Transient Equivalent Testing Load Circuit (VCC e 5.0V g 5%)
24
VS28F016SV, MS28F016SV FlashFile TM Memory
5.4 DC Characteristics
VCC e 3.3V g 0.15V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C
Sym
Parameter
Notes
Min
Max
Units
Test Conditions
ILI
Input Load Current
1
g1
mA
VCC e VCC Max,
VIN e VCC or GND
ILO
Output Leakage Current
1
g 10
mA
VCC e VCC Max,
VOUT e VCC or GND
ICCS
VCC Standby
Current
1,5
130
mA
VCC e VCC Max,
CE0Ý, CE1Ý, RPÝ e VCC
g 0.2V
BYTEÝ, WPÝ, 3/5Ý e VCC
g 0.2V or GND g 0.2V
4
mA
VCC e VCC Max,
CE0Ý, CE1Ý, RPÝ e VIH
BYTEÝ, WPÝ, 3/5Ý e VIH or VIL
ICCD
VCC Deep PowerDown Current
1
50
mA
RPÝ e GND g 0.2V
BYTEÝ e VCC g 0.2V or
GND g 0.2V
ICCR1
VCC Read Current
1,4,5
60
mA
VCC e VCC Max
CMOS: CE0Ý, CE1Ý e GND
g 0.2V
BYTEÝ e GND g 0.2V or
VCC g 0.2V
Inputs e GND g 0.2V or
VCC g 0.2V
TTL: CE0Ý, CE1Ý e VIL,
BYTEÝ e VIL or VIH
INPUTS e VIL or VIH,
f e 8 MHz, IOUT e 0 mA
ICCR2
VCC Read Current
1,4,5,6
40
mA
VCC e VCC Max
CMOS: CE0Ý, CE1Ý e GND
g 0.2V
BYTEÝ e GND g 0.2V or
VCC g 0.2V
Inputs e GND g 0.2V or
VCC g 0.2V
TTL: CE0Ý, CE1Ý e VIL,
BYTEÝ e VIL or VIH
INPUTS e VIL or VIH,
f e 4 MHz, IOUT e 0 mA
25
VS28F016SV, MS28F016SV FlashFile TM Memory
5.4 DC Characteristics
(Continued)
VCC e 3.3V g 0.3V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C
Sym
Parameter
Notes
ICCW
VCC Write Current
1,6
ICCE
VCC Block Erase
Current
Min
Max
Units
Test Conditions
12
mA
Word/Byte Write in Progress
VPP e 12.0V g 5%
17
mA
Word/Byte Write in Progress
VPP e 5.0V g 10%
12
mA
Block Erase in Progress
VPP e 12.0V g 5%
17
mA
Block Erase in Progress
VPP e 5.0V g 10%
1,2
6
mA
CE0Ý, CE1Ý e VIH
Block Erase Suspended
g 100
mA
VPP s VCC
1,6
ICCES
VCC Erase
Suspend Current
IPPS
IPPR
VPP Standby/Read
Current
1
200
mA
VPP l VCC
IPPD
VPP Deep PowerDown Current
1
50
mA
RPÝ e GND g 0.2V
IPPW
VPP Write Current
1
15
mA
VPP e 12.0V g 5%
Word/Byte Write in Progress
25
mA
VPP e 5.0V g 10%
Word/Byte Write in Progress
10
mA
VPP e 12.0V g 5%
Block Erase in Progress
20
mA
VPP e 5.0V g 10%
Block Erase in Progress
200
mA
VPP e VPPH1 or VPPH2,
Block Erase Suspended
0.8
V
IPPE
VPP Erase Current
IPPES
VPP Erase
Suspend Current
VIL
Input Low Voltage
VIH
Input High Voltage
1
1
b 0.3
VCC
2.0
a
V
0.3
VOL
26
Output Low
Voltage
0.4
V
VCC e VCC Min and
IOL e 4 mA
VS28F016SV, MS28F016SV FlashFile TM Memory
5.4 DC Characteristics
(Continued)
VCC e 3.3V g 0.15V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C
Sym
VOH1
Parameter
Notes
Output High
Voltage
VOH2
Min
Max
Units
Test Conditions
2.4
V
IOH e b 2.0 mA
VCC e VCC Min
VCC b 0.2
V
IOH e b 100 mA
VCC e VCC Min
VPPLK
VPP Erase/Write
Lock Voltage
3
0.0
1.8
V
VPPH1
VPP during
Write/Erase
Operations
3
4.5
5.5
V
VPPH2
VPP during
Write/Erase
Operations
3
11.4
12.6
V
VLKO
VCC Erase/Write
Lock Voltage
1.8
V
NOTES:
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of ICCES and ICCR.
3. Block Erases, Word/Byte Writes and Lock Block operations are inhibited when VPP s VPPLK and not guaranteed in the
ranges between VPPLK(max) and VPPH1(min), between VPPH1(max) and VPPH2(min) and above VPPH2(max).
4. Automatic Power Savings (APS) reduces ICCR to less than 3 mA in static operation.
5. CMOS Inputs are either VCC g 0.2V or GND g 0.2V. TTL Inputs are either VIL or VIH.
6. Sampled, but not 100% tested. Guaranteed by design.
27
VS28F016SV, MS28F016SV FlashFile TM Memory
5.5 DC Characteristics
VCC e 5.0V g 0.5V, 5.0V g 0.25V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C
Parameter
Notes
Max
Units
ILI
Sym
Input Load Current
1
Min
g1
mA
VCC e VCC Max
VIN e VCC or GND
Test Conditions
ILO
Output Leakage
Current
1
g 10
mA
VCC e VCC Max
VIN e VCCor GND
ICCS
VCC Standby
Current
1,5
130
mA
VCC e VCC Max
CE0Ý, CE1Ý, RPÝ e VCC g
0.2V
BYTEÝ, WPÝ e VCC g
0.2V or GND g 0.2V
4
mA
VCC e VCC Max
CE0Ý, CE1Ý, RPÝ e VIH
BYTEÝ, WPÝ, 3/5Ý e VIH or VIL
ICCD
VCC Deep PowerDown Current
1
50
mA
RPÝ e GND g 0.2V
BYTEÝ e VCC g 0.2V or
GND g 0.2V
ICCR1
VCC Read Current
1,4,5
135
mA
VCC e VCC Max,
CMOS:CE0Ý, CE1Ý e GND g
0.2V
BYTEÝ e GND g 0.2V or
VCC g 0.2V
Inputs e GND g 0.2V or
VCC g 0.2V
TTL: CE0Ý, CE1Ý e VIL,
BYTEÝ e VIL or VIH,
Inputs e VIL or VIH,
f e 10 MHz, IOUT e 0 mA
ICCR2
VCC Read Current
1,4,5,6
90
mA
VCC e VCC Max,
CMOS:CE0Ý, CE1Ý e GND g
0.2V
BYTEÝ e GND g 0.2V or
VCC g 0.2V
Inputs e GND g 0.2V or
VCC g 0.2V
TTL: CE0Ý, CE1Ý e VIL,
BYTEÝ e VIL or VIH,
Inputs e VIL or VIH,
f e 5 MHz, IOUT e 0 mA
28
VS28F016SV, MS28F016SV FlashFile TM Memory
5.5 DC Characteristics
(Continued)
VCC e 5.0V g 0.5V, 5.0V g 0.25V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C
Sym
Parameter
Notes
ICCW
VCC Write Current
1,6
ICCE
VCC Block Erase
Current
Min
Max
Units
35
mA
Word/Byte in Progress
VPP e 12.0V g 5%
40
mA
Word/Byte in Progress
VPP e 5.0V g 10%
25
mA
Block Erase in Progress
VPP e 12.0V g 5%
30
mA
Block Erase in Progress
VPP e 5.0V g 10%
1,2
10
mA
CE0Ý, CE1Ý e VIH
Block Erase Suspended
g 100
mA
VPP s VCC
200
mA
VPP l VCC
1,6
Test Conditions
ICCES
VCC Erase
Suspend Current
IPPS
IPPR
VPP Standby/Read
Current
1
IPPD
VPP Deep PowerDown Current
1
50
mA
RPÝ e GND g 0.2V
IPPW
VPP Write Current
1,6
12
mA
VPP e 12.0V g 5%
Word/Byte Write in Progress
22
mA
VPP e 5.0V g 10%
Word/Byte Write in Progress
10
mA
VPP e 12.0V g 5%
Block Erase in Progress
20
mA
VPP e 5.0V g 10%
Block Erase in Progress
200
mA
VPP e VPPH1 or VPPH2,
Block Erase Suspended
IPPE
VPP Block Erase
Current
1,6
IPPES
VPP Erase
Suspend Current
1
VIL
Input Low Voltage
6
b 0.5
0.8
V
VIH
Input High Voltage
6
2.0
VCC
a 0.5
V
29
VS28F016SV, MS28F016SV FlashFile TM Memory
5.5 DC Characteristics
(Continued)
VCC e 5.0V g 0.5V, 5.0V g 0.25V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C
Sym
Parameter
Notes
VOL
Output Low
Voltage
6
VOH1
Output High
Voltage
6
VOH2
6
Min
Max
Units
0.45
V
VCC e VCC Min
IOL e 5.8 mA
V
IOH e b 2.5 mA
VCC e VCC Min
0.85
VCC
VCC
IOH e b 100 mA
VCC e VCC Min
b 0.4
VPPLK
VPP Write/Erase
Lock Voltage
VPPH1
3,6
Test Conditions
0.0
1.8
V
VPP during
Write/Erase
Operations
4.5
5.5
V
VPPH2
VPP during
Write/Erase
Operations
11.4
12.6
V
VLKO
VCC Write/Erase
Lock Voltage
1.8
V
NOTES:
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of ICCESand ICCR.
3. Block Erases, Word/Byte Writes and Lock Block operations are inhibited when VPP s VPPLK and not guaranteed in the
ranges between VPPLK(max) and VPPH1(min), between VPPH1(max) and VPPH2(min) and above VPPH2(max).
4. Automatic Power Saving (APS) reduces ICCR to less than 1 mA in Static operation.
5. CMOS Inputs are either VCC g 0.2V or GND g 0.2V. TTL Inputs are either VIL or VIH.
6. Sampled, not 100% tested. Guaranteed by design.
30
VS28F016SV, MS28F016SV FlashFile TM Memory
5.6 AC CharacteristicsÐRead Only Operations(1)
VCC e 3.3V g 0.15V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 50 pF
Versions
Sym
Parameter
Notes
Min
Max
120
Units
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay (TACC)
ns
tELQV
CEÝ to Output Delay (TCE)
tPHQV
RPÝ High to Output Delay
tGLQV
OEÝ to Output Delay (TOE)
tELQX
CEÝ to Output in Low Z
3,7
tEHQZ
CEÝ to Output in High Z
3,7
tGLQX
OEÝ to Output in Low Z
3
tGHQZ
OEÝ to Output in High Z
tOH
Output Hold from Address, CEÝ or OEÝ
Change, Whichever Occurs First
tFLQV
tFHQV
BYTEÝ to Output Delay
3
120
ns
tFLQZ
BYTEÝ Low to Output in High Z
3
30
ns
tELFL
tELFH
CEÝ Low to BYTEÝ High or Low
3,7
5
ns
120
2,7
2
120
ns
620
ns
45
0
50
3
ns
ns
0
ns
ns
30
3,7
ns
0
ns
ns
Extended Status Register Reads
Sym
Parameter
Notes
Min
tAVEL
Address Setup to CEÝ Going Low
3,7,8,9
0
Max
Units
ns
tAVGL
Address Setup to OEÝ Going Low
3,7,9
0
ns
31
VS28F016SV, MS28F016SV FlashFile TM Memory
5.6 AC CharacteristicsÐRead Only Operations(1)
(Continued)
VCC e 5.0V g 0.25V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 30 pF
VCC e 5.0V g 0.5V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 100 pF
VS/MS28F016SV-85
VCC g 5%(5)
Versions(4)
Sym
Parameter
Notes
Min
VS/MS28F016SV-85
VCC g 10%(6)
Max
Min
80
VS/MS28F016SV-100
VCC g 10%
Max
Min
tAVAV
Read Cycle Time
tAVQV
Address to Output
Delay (TACC)
tELQV
CEÝ to Output
Delay (TCE)
tPHQV
RPÝ to Output
Delay
tGLQV
OEÝ to Output
Delay (TOE)
2
tELQX
CEÝ to Output in
Low Z
3
tEHQZ
CEÝ to Output in
High Z
3
tGLQX
OEÝ to Output in
Low Z
3
tGHQZ
OEÝ to Output in
High Z
3
tOH
Output Hold from
Address, CEÝ or
OEÝ Change,
Whichever Occurs
First
3
tFLQV
tFHQV
BYTEÝ to Output
Delay
3
80
85
100
ns
tFLQZ
BYTEÝ Low to
Output in High Z
3
25
30
35
ns
tELFL
tELFH
CEÝ Low to
BYTEÝ High or
Low
3
5
5
5
ns
2
85
Unit
Max
100
ns
80
85
100
ns
80
85
100
ns
400
480
480
ns
30
35
40
ns
0
0
0
25
ns
30
0
35
0
0
25
ns
30
0
35
0
ns
0
ns
ns
Extended Status Register Reads
Sym
tAVEL
Parameter
Address Setup to CEÝ Going
Notes
Min
Max
Min
Max
Min
Max
Unit
3,7,8,9
0
0
0
ns
3,7,9
0
0
0
ns
Low
tAVGL
32
Address Setup to OEÝ Going
Low
VS28F016SV, MS28F016SV FlashFile TM Memory
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements, Figures 6 and 7.
2. OEÝ may be delayed up to tELQV – tGLQV after the falling edge of CEÝ, without impacting tELQV.
3. Sampled, not 100% tested. Guaranteed by design.
4. Device speeds are defined as:
80/85, 100 ns at VCC e 5.0V equivalent to
120 ns at VCC e 3.3V
5. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
6. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
7. CExÝ is defined as the latter of CE0Ý or CE1Ý going low, or the f.
8. This timing parameter is used to latch the correct BSR data onto the outputs.
9. The address setup requirement for Extended Status Register reads must only be met referenced to the falling edge of the
last control signal to become active (CE0Ý, CE1Ý, or OEÝ). For example, if CE0Ý or CE1Ý are activated prior to OEÝ for
an Extended Status Register read, specification tAVGL must be met. On the other hand, if either CE0Ý or CE1Ý (or both)
are activated after OEÝ, specification tAVEL must be referenced.
271312 – 11
NOTE:
CExÝ is defined as the latter of CE0Ý or CE1Ý going low, or the first of CE0Ý or CE1Ý going high.
Figure 11. Read Timing Waveforms
33
VS28F016SV, MS28F016SV FlashFile TM Memory
271312 – 12
NOTE:
CExÝ is defined as the latter of CE0Ý or CE1Ý going low, or the first of CE0Ý or CE1Ý going high.
Figure 12. BYTEÝ Timing Waveforms
34
VS28F016SV, MS28F016SV FlashFile TM Memory
5.7 Power-Up and Reset Timings
271312 – 22
Figure 13. VCC Power-Up and RPÝ Reset Waveforms
Symbol
Parameter
Notes
Min
Max
Unit
tPLYL
tPLYH
RPÝ Low to 3/5Ý Low (High)
0
ms
tYLPH
tYHPH
3/5Ý Low (High) to RPÝ High
1
2
ms
tPL5V
tPL3V
RPÝ Low to VCC at 4.5V minimum (to VCC at 3.0V min or
3.6V max)
2
0
ms
tPHEL3
RPÝ High to CEÝ Low (3.3V VCC)
1
405
ns
tPHEL5
RPÝ High to CEÝ Low (5V VCC)
1
330
ns
tAVQV
Address Valid to Data Valid for VCC e 5V g 10%
3
70
ns
tPHQV
RPÝ High to Data Valid for VCC e 5V g 10%
3
400
ns
NOTES:
CE0Ý, CE1Ý and OEÝ are switched low after Power-Up.
1. The tYLPH and/or tYHPH times must be strictly followed to guarantee all other read and write specifications for the
VS/MS28F016SV.
2. The power supply may start to switch concurrently with RPÝ going low.
3. The address access time and RPÝ high to data valid time are shown for 5.0V VCC operation of the 28F016SV-085
(Standard Test Configuration). Refer to the AC ChracteristicsÐRead Only Operations for 3.3V VCC and 5.0V VCC (High
Speed Test Configuration) values.
35
VS28F016SV, MS28F016SV FlashFile TM Memory
5.8 AC Characteristics for WEÝÐControlled Command Write Operations(1)
VCC e 3.3V g 0.15V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 50 pF
Versions
Sym
36
Parameter
Notes
Min
Max
Unit
tAVAV
Write Cycle Time
tVPWH(1,2)
VPP Setup to WEÝ Going High
120
ns
3
100
ns
tPHEL
tELWL
RPÝ Setup to CEÝ Going Low
3,7
480
ns
CEÝ Setup to WEÝ Going Low
3,7
10
ns
tAVWH
Address Setup to WEÝ Going High
2,6
75
ns
tDVWH
Data Setup to WEÝ Going High
2,6
75
ns
tWLWH
WEÝ Pulse Width
75
ns
tWHDX
Data Hold from WEÝ High
2
10
ns
tWHAX
Address Hold from WEÝ High
2
10
ns
tWHEH
CEÝ Hold from WEÝ High
3,7
10
ns
tWHWL
WEÝ Pulse Width High
tGHWL
Read Recovery before Write
tWHRL
WEÝ High to RY/BYÝ Going Low
3
tRHPL
RPÝ Hold from Valid Status Register (CSR,
GSR, BSR) Data and RY/BYÝ High
3
0
ns
tPHWL
RPÝ High Recovery to WEÝ Going Low
3
480
ns
tWHGL
Write Recovery before Read
tQVVL(1,2)
VPP Hold from Valid Status Register (CSR,
GSR, BSR) Data and RY/BYÝ High
tWHQV(1)
Duration of Word/Byte Write Operation
tWHQV(2)
Duration of Block Erase Operation
3
45
ns
0
ns
100
ns
95
ns
3
0
ms
3,4,5,11
5
ms
3,4
0.3
10
sec
VS28F016SV, MS28F016SV FlashFile TM Memory
5.8 AC Characteristics for WEÝÐControlled Command Write Operations(1)
(Continued)
VCC e 5.0V g 0.25V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 30 pF
VCC e 5.0V g 0.5V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 100 pF
VS/MS28F016SV-85
VCC g 5%
Versions
Sym
Parameter
tAVAV
Write Cycle
Time
tVPWH(1)
tVPWH(2)
VPP Setup to
WEÝ Going
High
tPHEL
Notes
Min
Max
VS/MS28F016SV-85
VCC g 10%
Min
Max
VS/MS28F016SV-100
VCC g 10%
Min
Unit
Max
80
85
100
ns
3
100
100
100
ns
RPÝ Setup to
CEÝ Going
Low
3,7
480
480
480
ns
tELWL
CEÝ Setup to
WEÝ Going
Low
3,7
0
0
0
ns
tAVWH
Address
Setup to
WEÝ Going
High
2,6
50
50
50
ns
tDVWH
Data Setup to
WEÝ Going
High
2,6
50
50
50
ns
tWLWH
WEÝ Pulse
Width
50
60
70
ns
tWHDX
Data Hold
from WEÝ
High
2
10
10
10
ns
tWHAX
Address Hold
from WEÝ
High
2
10
10
10
ns
tWHEH
CEÝ Hold
from WEÝ
High
3,7
10
10
10
ns
tWHWL
WEÝ Pulse
Width High
30
30
30
ns
tGHWL
Read
Recovery
before Write
3
0
0
0
ns
tWHRL
WEÝ High to
RY/BYÝ
Going Low
3
tRHPL
RPÝ Hold
from Valid
Status
Register
(CSR, GSR,
BSR) Data
and RY/BY Ý
High
3
100
0
100
0
100
0
ns
ns
37
VS28F016SV, MS28F016SV FlashFile TM Memory
5.8 AC Characteristics for WEÝÐControlled Command Write Operations(1)
VCC e 5.0V g 0.25V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 30 pF
VCC e 5.0V g 0.5V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 100 pF
(Continued)
VS/MS28F016SV-85
VCC g 5%
Versions
Max
VS/MS28F016SV-85
VCC g 10%
Parameter
Notes
Min
tPHWL
RPÝ High
Recovery to
WEÝ Going
Low
3
1
1
1
ms
tWHGL
Write
Recovery
before Read
60
65
70
ns
tQVVL(1)
tQVVL(2)
VPP Hold
from Valid
Status
Register
(CSR, GSR,
BSR) Data
and RY/
BYÝ High
3
0
0
0
ms
tWHQV(1)
Duration of
Word/Byte
Write
Operation
3,4,5,11
4.5
4.5
4.5
ms
tWHQV(2)
Duration of
Block Erase
Operation
3,4
0.3
0.3
Max
10
Min
Unit
Sym
10
Min
VS/MS28F016SV-100
VCC g 10%
0.3
Max
10
sec
NOTES:
1. Read timings during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, not 100% tested. Guaranteed by design.
4. Write/Erase durations are measured to valid Status Register (CSR) Data. VPP e 12.0V g 0.6V
5. Word/Byte Write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of WEÝ for all Command Write operations.
7. CExÝ is defined as the latter of CE0Ý or CE1Ý going low, or the first of CE0Ý or CE1Ý going high.
8. Device speeds are defined as:
80/85, 100 ns at VCC e 5.0V equivalent to
120 ns at VCC e 3.3V
9. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
10. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
11. The TBD information will be available in a technical paper. Please contact Intel’s Application Hotline or your local sales
office for more information.
38
VS28F016SV, MS28F016SV FlashFile TM Memory
271312 – 23
NOTES:
1. This address string depicts data write/erase cycles with corresponding verification via ESRD.
2. This address string depicts data write/erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during data write/erase operations.
4. CExÝ is defined as the latter of CE0Ý or CE1Ý going low or the first of CE0Ý or CE1Ý going high.
5. RPÝ low transition is only to show tRHPL; not valid for above Read and Write cycles.
6. VPP voltage during write/erase operations valid at both 12.0V and 5.0V.
7. VPP voltage equal to or below VPPLK provides complete flash memory array protection.
Figure 14. AC Waveforms for Command Write Operations
39
VS28F016SV, MS28F016SV FlashFile TM Memory
5.9 AC Characteristics for CEÝÐControlled Command Write Operations(1)
VCC e 3.3V g 0.15V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 50 pF
Versions
Sym
Notes
Min
Max
Unit
tAVAV
Write Cycle Time
120
ns
tPHWL
RPÝ Setup to WEÝ Going Low
3
480
ns
tVPEH
VPP Setup to CEÝ Going High
3,7
100
ns
tWLEL
WEÝ Setup to CEÝ Going Low
3,7
0
ns
tAVEH
Address Setup to CEÝ Going High
2,6,7
75
ns
tDVEH
Data Setup to CEÝ Going High
2,6,7
75
ns
tELEH
CEÝ Pulse Width
7
75
ns
tEHDX
Data Hold from CEÝ High
2,7
10
ns
tEHAX
Address Hold from CEÝ High
2,7
10
ns
tEHWH
WEÝ hold from CEÝ High
3
10
ns
tEHEL
CEÝ Pulse Width High
7
45
ns
tGHEL
Read Recovery before Write
3
0
tEHRL
CEÝ High to RY/BYÝ Going Low
tRHPL
RPÝ Hold from Valid Status Register (CSR,
GSR, BSR) Data and RY/BYÝ High
tPHEL
RPÝ High Recovery to CEÝ Going Low
tEHGL
Write Recovery before Read
tQVVL(1,2)
VPP Hold from Valid Status Register (CSR,
GSR, BSR) Data and RY/BYÝ High
tEHQV(1)
Duration of Word/Byte Write Operation
tEHQV(2)
Duration of Block Erase Operation
(1,2)
40
Parameter
3,7
ns
100
ns
3
0
3,7
480
ns
95
ns
0
ms
3
3,4,5,11
5
4
0.3
ns
ms
10
sec
VS28F016SV, MS28F016SV FlashFile TM Memory
5.9 AC Characteristics for CEÝÐControlled Command Write Operations(1)
(Continued)
VCC e 5.0V g 0.25V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 30 pF
VCC e 5.0V g 0.5V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 100 pF
Versions(4)
Sym
Parameter
tAVAV
Write Cycle
Time
tPHWL
RPÝ Setup to
WEÝ Going
Low
tVPEH(1,2)
Notes
VS/MS28F016SV-85
VS/MS28F016SV-85
VCC g 5%
VCC g 10%
Min
Max
Min
Max
VS/MS28F016SV-100
VCC g 10%
Min
Unit
Max
80
85
100
ns
3
480
480
480
ns
VPP Setup to
CEÝ Going
High
3,7
100
100
100
ns
tWLEL
WEÝ Setup to
CEÝ Going
Low
3,7
0
0
0
ns
tAVEH
Address Setup
to CEÝ Going
High
2,6,7
50
50
50
ns
tDVEH
Data Setup to
CEÝ Going
High
2,6,7
50
50
50
ns
tELEH
CEÝ Pulse
Width
7
50
60
70
ns
tEHDX
Data Hold from
CEÝ High
2,7
10
10
10
ns
tEHAX
Address Hold
from CEÝ High
2,7
10
10
10
ns
tEHWH
WE Hold from
CEÝ High
3,7
10
10
10
ns
tEHEL
CEÝ Pulse
Width High
7
30
30
30
ns
tGHEL
Read Recovery
before Write
3
0
0
0
ns
tEHRL
CEÝ High to
RY/BYÝ Going
Low
3,7
tRHPL
RPÝ Hold from
Valid Status
Register
(CSR, GSR,
BSR) Data and
RY/BYÝ High
3
100
0
100
0
100
0
ns
ns
41
VS28F016SV, MS28F016SV FlashFile TM Memory
5.9 AC Characteristics for CEÝÐControlled Command Write Operations(1)
VCC e 5.0V g 0.25V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 30 pF
VCC e 5.0V g 0.5V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 100 pF
(Continued)
Versions(4)
Sym
Parameter
VS/MS28F016SV-85
VS/MS28F016SV-85
VCC g 5%
VCC g 10%
3,7
1
1
1
ms
60
65
70
ns
3
0
0
0
ms
4.5
4.5
ms
tEHGL
Write
Recovery
before Read
tQVVL(1,2)
VPP Hold
from Valid
Status
Register
(CSR, GSR,
BSR) Data at
RY/BYÝ
High
tEHQV(1)
Duration of
Word/Byte
Write
Operation
3,4,5,11
4.5
tEHQV(2)
Duration of
Block Erase
Operation
3,4
0.3
10
0.3
Max
10
Min
Unit
Min
RPÝ High
Recovery to
CEÝ Going
Low
Min
VCC g 10%
Notes
tPHEL
Max
VS/MS28F016SV-100
0.3
Max
10
sec
NOTES:
1. Read timings during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, not 100% tested. Guaranteed by design.
4. Write/erase durations are measured to valid Status Data. VPP e 12.0V g 0.6V.
5. Word/Byte Write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of CEÝ for all command write operations.
7. CExÝ is defined as the latter of CE0Ý or CE1Ý going low, or the first of CE0Ý or CE1Ý going high.
8. Device speeds are defined as:
80/85, 100 ns at VCC e 5.0V equivalent to
120 ns at VCC e 3.3V
9. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
10. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
11. The TBD information will be available in a technical paper. Please contact Intel’s Application Hotline or your local sales
office for more information.
42
VS28F016SV, MS28F016SV FlashFile TM Memory
271312 – 24
NOTES:
1. This address string depicts data-write/erase cycles with corresponding verification via ESRD.
2. This address string depicts data-write/erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during data write/erase operations.
4. CExÝ is defined as the latter of CE0Ý or CE1Ý going low or the first of CE0Ý or CE1Ý going high.
5. RPÝ low transition is only to show tRHPL; not valid for above Read and Write cycles.
6. VPP voltage during Write/Erase operations valid at both 12.0V and 5.0V.
7. VPP voltage equal to or below VPPLK provides complete flash memory array protection.
Figure 15. Alternate AC Waveforms for Command Write Operations
43
VS28F016SV, MS28F016SV FlashFile TM Memory
5.10 AC Characteristics for WEÝÐControlled Page Buffer Write Operations(1)
VCC e 3.3V g 0.3V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 50 pF
Versions
28F016SV-120
Sym
Parameter
Notes
Min
tAVWL
Address Setup to WEÝ Going Low
2
25
Typ
Max
Unit
ns
VCC e 5.0V g 0.5V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 50 pF
Versions(3)
VCC g 5%
28F016SV-080(4)
VCC g 10%
28F016SV-080(5)
Sym
Parameter
Notes
Min
tAVWL
Address Setup
to WEÝ Going Low
2
15
Typ
Max
28F016SV-085(5)
Min
15
NOTES:
1. All other specifications for WEÝÐControlled Write Operations can be found in section 5.8.
2. Address must be valid during the entire WEÝ low pulse.
3. Device speeds are defined as:
80/85, 100 ns at VCC e 5.0V equivalent to
120 ns at VCC e 3.3V
4. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
5. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
44
Typ
Unit
Max
ns
VS28F016SV, MS28F016SV FlashFile TM Memory
271312 – 25
NOTE:
1. CEXÝ is defined as the latter of CE0Ý or CE1Ý going low, or the first of CE0Ý or CE1Ý going high.
Figure 16. WEÝÐControlled Page Buffer Write Timing Waveforms (Loading Data to the Tape Buffer)
45
VS28F016SV, MS28F016SV FlashFile TM Memory
5.11 AC Characteristics for CEÝÐControlled Page Buffer Write Operations(1)
VCC e 3.3V g 0.3V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 50 pF
Versions
28F016SV-120
Sym
Parameter
Notes
Min
tAVEL
Address Setup to CEÝ Going Low
2, 3
25
Typ
Unit
Max
ns
VCC e 5.0V g 0.5V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C, Load e 50 pF
Versions(4)
VCC g 5%
28F016SV-080(5)
VCC g 10%
28F016SV-080(6)
Sym
Parameter
Notes
Min
tAVEL
Address Setup
to CEÝ Going Low
2, 3
15
Typ
Max
28F016SV-085(6)
Min
Typ
15
Unit
Max
ns
NOTES:
1. All other specifications for CEÝÐControlled Write Operations can be found in section 5.9.
2. Address must be valid during the entire CEÝ low pulse.
3. CExÝ is defined as the latter of CE0Ý or CE1Ý going low, or the first of CE0Ý or CE1Ý going high.
4. Device speeds are defined as:
80/85, 100 ns at VCC e 5.0V equivalent to
120 ns at VCC e 3.3V
5. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
6. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
271312 – 26
NOTE:
1. CExÝ is defined as the latter of CE0Ý or CE1Ý going low, or the first of CE0Ý or CE1Ý going high.
Figure 17. Controller Page Buffer Write Timing Waveforms
(Loading Data to the Page Buffer)
46
VS28F016SV, MS28F016SV FlashFile TM Memory
5.12 Erase and Word/Byte Write Performance(3,5)
VCC e 3.3V g 0.15V, VPP e 5.0V g 0.5V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C
Sym
Parameter
Notes
Typ(1)
Units
Page Buffer Byte Write Time
2,6,7
8
ms
Page Buffer Word Write Time
2,6,7
16
ms
tWHRH1A
Byte Write Time
2,7
29
ms
Test Conditions
tWHRH1B
Word Write Time
2,7
35
ms
tWHRH(2)
Block Write Time
2,7
1.9
sec
Byte Write Mode
tWHRH(3)
Block Write Time
2,7
1.2
sec
Word Write Mode
Block Erase Time
2,7
1.4
sec
Full Chip Erase Time
2,7
44.8
sec
4
12
ms
15
ms
Erase Suspend Latency Time
to Read
Auto Erase Suspend Latency
Time to Write
VCC e 3.3V g 0.15V, VPP e 12.0V g 0.6V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C
Sym
Parameter
Notes
Typ(1)
Units
Page Buffer Byte Write Time
2,6,7
2.2
ms
Page Buffer Word Write Time
2,6,7
4.4
ms
Test Conditions
tWHRH(1)
Word/Byte Write Time
2,7
9
ms
tWHRH(2)
Block Write Time
2,7
0.6
sec
Byte Write Mode
tWHRH(3)
Block Write Time
2,7
0.3
sec
Word Write Mode
Block Erase Time
2
0.8
sec
2,7
25.6
sec
4
9
ms
12
ms
Full Chip Erase Time
Erase Suspend Latency Time
to Read
Auto Erase Suspend Latency
Time to Write
47
VS28F016SV, MS28F016SV FlashFile TM Memory
5.12 Erase and Word/Byte Write Performance(3,5)
(Continued)
VCC e 5.0V, VPP e 5.0V g 0.5V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C
Sym
Parameter
Notes
Typ(1)
Units
Page Buffer Byte Write Time
2,6,7
8
ms
Page Buffer Word Write Time
2,6,7
16
ms
tWHRH1A
Byte Write Time
2,7
20
ms
Test Conditions
tWHRH1B
Word Write Time
2,7
25
ms
tWHRH(2)
Block Write Time
2,7
1.4
sec
Byte Write Mode
tWHRH(3)
Block Write Time
2,7
0.85
sec
Word Write Mode
Block Erase Time
2,7
1.0
sec
Full Chip Erase Time
2,7
32.0
sec
4
9
ms
12
ms
Erase Suspend Latency Time
to Read
Auto Erase Suspend Latency
Time to Write
VCC e 5.0V g 0.5V, VPP e 12.0V g 0.6V, TCSE2 e b 40§ C to a 125§ C, TCSE1 e b 55§ C to a 125§ C
Sym
Parameter
Notes
Typ(1)
Units
Page Buffer Byte Write Time
2,6,7
2.1
ms
Page Buffer Word Write Time
2,6,7
4.1
ms
Test Conditions
tWHRH(1)
Word/Byte Write Time
2,7
6
ms
tWHRH(2)
Block Write Time
2,7
0.4
sec
Byte Write Mode
tWHRH(3)
Block Write Time
2,7
0.2
sec
Word Write Mode
Block Erase Time
2
0.6
sec
2,7
19.2
sec
4
7
ms
10
ms
Full Chip Erase Time
Erase Suspend Latency Time
to Read
Auto Erase Suspend Latency
Time to Write
NOTES:
1. 25§ C, and normal voltages.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Specification applies to interrupt latency for single block erase. Suspend latency for erase all unlocked blocks operation
extends the maximum latency time to 270 ms.
5. Sampled, but not 100% tested. Guaranteed by design.
6. Assumes using the full Page Buffer to Write to Flash (256 bytes or 128 words).
48
VS28F016SV, MS28F016SV FlashFile TM Memory
6.0
MECHANICAL SPECIFICATIONS
271312 – 27
Figure 18. Mechanical Specifications of the VS/MS28F0165V 56-Lead SSOP Package
Family: Shrink Small Out-Line Package
Symbol
Millimeters
Minimum
Nominal
1.80
1.90
A1
0.47
0.52
0.57
A2
1.18
1.28
1.38
B
0.25
0.30
0.40
A
Maximum
C
0.13
0.15
0.20
D
23.40
23.70
24.00
E
13.10
13.30
13.50
e1
He
0.80
15.70
N
L1
16.00
16.30
56
0.45
0.50
2§
3§
Y
a
Notes
0.55
0.10
4§
b
3§
4§
5§
R1
0.45
0.20
0.25
R2
0.15
0.20
0.25
49
VS28F016SV, MS28F016SV FlashFile TM Memory
DEVICE NOMENCLATURE
V
S
2
8
F
0
1
6
S
V
Ð
8
5
M
S
2
8
F
0
1
6
S
V
Ð
8
5
l
V e SE2
M e SE1
l
l
l
Access Speed
l
SV e SmartVoltage Technology
S e SSOP
Depending on system design specifcations, the VS/MS28F016SV-85 is capable of supporting
Ð 85 ns access time with a VCC of 5.0V g 10% and loading of 100 pF
Ð 100 ns access time with a VCC of 5.0V g 10% and loading of 100 pF
ADDITIONAL INFORMATION
Order Number
297372
Document/Tool
16-Mbit Flash Product Family User’s Manual
292163
AP-610 ‘‘Flash Memory In-System Code and Data Update Techinques’’
292144
AP-393 ‘‘28F016SV Compatibility with 28F016SA’’
292127
AP-378 ‘‘System Optimization Using the Enhanced Features of the
28F016SA’’
AP-377 ‘‘16-Mbit Flash Product Family Software Drivers, 28F016SA/
28F016SV/28F016XS/28F016XD’’
292126
292124
AP-387 ‘‘Upgrade Considerations from the 28F008SA to the 28F016SA’’
292123
292092
292165
294016
AP-374 ‘‘Flash Memory Write Protection Techniques’’
AP-357 ‘‘Power Supply Solutions for Flash Memory’’
AB-62 ‘‘Compiling Optimized Code for Embedded Flash RAM Memories’’
ER-33 ‘‘ETOX TM Flash Memory TechnologyÐInsight to Intel’s Fourth
Generation Process Innovation’’
297508
Contact Intel/Distribution
Sales Office
FLASHBuilder Utility
Flash Cycling Utility
Contact Intel/Distribution
Sales Office
Contact Intel/Distribution
Sales Office
28F016SV iBIS Models
Contact Intel/Distribution
Sales Office
Contact Intel/Distribution
Sales Office
28F016SV Timing Designer Library Files
28F016SV VHDL/Verilog Models
28F016SV Orcad and ViewLogic Schematic Symbols
DATA SHEET REVISION HISTORY
Number
Description
001
Original Version
INTEL CORPORATION, 2200 Mission College Blvd., Santa Clara, CA 95052; Tel. (408) 765-8080
Printed in U.S.A./xxxx/1295/B10M/xx xx