INTEL TN28F001BX-T150

1-MBIT (128K x 8)
BOOT BLOCK FLASH MEMORY
28F001BX-T/28F001BX-B/28F001BN-T/28F001BN-B
Y
High-Integration Blocked Architecture
Ð One 8 KB Boot Block w/Lock Out
Ð Two 4 KB Parameter Blocks
Ð One 112 KB Main Block
Y
High-Performance Read
Ð 70/75 ns, 90 ns, 120 ns, 150 ns
Maximum Access Time
Ð 5.0V g 10% VCC
Y
100,000 Erase/Program Cycles Per
Block
Y
Y
Simplified Program and Erase
Ð Automated Algorithms via On-Chip
Write State Machine (WSM)
Hardware Data Protection Feature
Ð Erase/Write Lockout during Power
Transitions
Y
Advanced Packaging, JEDEC Pinouts
Ð 32-Pin PDIP
Ð 32-Lead PLCC, TSOP
Y
ETOX TM II Nonvolatile Flash
Technology
Ð EPROM-Compatible Process Base
Ð High-Volume Manufacturing
Experience
Y
Extended Temperature Options
Y
SRAM-Compatible Write Interface
Y
Deep Power-Down Mode
Ð 0.05 mA ICC Typical
Ð 0.8 mA IPP Typical
Y
12.0V g 5% VPP
Intel’s 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with
features that simplify write and allow block erase. These devices aid the system designer by combining the
functions of several components into one, making boot block flash an innovative alternative to EPROM and
EEPROM or battery-backed static RAM. Many new and existing designs can take advantage of the
28F001BX’s integration of blocked architecture, automated electrical reprogramming, and standard processor
interface.
The 28F001BX-B and 28F001BX-T are 1,048,576 bit nonvolatile memories organized as 131,072 bytes of
8 bits. They are offered in 32-pin plastic DIP, 32-lead PLCC and 32-lead TSOP packages. Pin assignment
conform to JEDEC standards for byte-wide EPROMs. These devices use an integrated command port and
state machine for simplified block erasure and byte reprogramming. The 28F001BX-T’s block locations provide compatibility with microprocessors and microcontrollers that boot from high memory, such as Intel’s
MCSÉ-186 family, 80286, i386 TM , i486 TM , i860 TM and 80960CA. With exactly the same memory segmentation,
the 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory,
such as Intel’s MCS-51, MCS-196, 80960KX and 80960SX families. All other features are identical, and unless
otherwise noted, the term 28F001BX can refer to either device throughout the remainder of this document.
The boot block section includes a reprogramming write lock out feature to guarantee data integrity. It is
designed to contain secure code which will bring up the system minimally and download code to the other
locations of the 28F001BX. Intel’s 28F001BX employs advanced CMOS circuitry for systems requiring highperformance access speeds, low power consumption, and immunity to noise. Its access time provides
no-WAIT-state performance for a wide range of microprocessors and microcontrollers. A deep-powerdown
mode lowers power consumption to 0.25 mW typical through VCC, crucial in laptop computer, handheld instrumentation and other low-power applications. The RPÝ power control input also provides absolute data protection during system powerup or power loss.
Manufactured on Intel’s ETOX process base, the 28F001BX builds on years of EPROM experience to yield the
highest levels of quality, reliability, and cost-effectiveness.
NOTE: The 28F001BN is equivalent to the 28F001BX.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 1995
November 1995
Order Number: 290406-007
28F001BX-T/28F001BX-B
290406 – 1
Figure 1. 28F001BX Block Diagram
Table 1. Pin Description
Symbol
A0 –A16
DQ0 –DQ7
Type
Name and Function
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally latched during
a write cycle.
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs data and commands during memory write
cycles; outputs data during memory, Status Register and Identifier read cycles. The
data pins are active high and float to tri-state off when the chip is deselected or the
outputs are disabled. Data is internally latched during a write cycle.
CEÝ
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CEÝ is active low; CEÝ high deselects the memory device and
reduces power consumption to standby levels.
RPÝ
INPUT
POWERDOWN: Puts the device in deep powerdown mode. RPÝ is active low;
RPÝ high gates normal operation. RPÝ e VHH allows programming of the boot
block. RPÝ also locks out erase or write operations when active low, providing data
protection during power transitions. RPÝ active resets internal automation. Exit
from deep powerdown sets device to Read Array mode.
OEÝ
INPUT
OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a
read cycle. OEÝ is active low. OEÝ e VHH (pulsed) allows programming of the
boot block.
WEÝ
INPUT
WRITE ENABLE: Controls writes to the Command Register and array blocks. WEÝ
is active low. Addresses and data are latched on the rising edge of the WEÝ pulse.
VPP
ERASE/PROGRAM POWER SUPPLY for erasing blocks of the array or
programming bytes of each block. Note: With VPP k VPPL max, memory contents
cannot be altered.
VCC
DEVICE POWER SUPPLY: (5V g 10%)
GND
GROUND
2
28F001BX-T/28F001BX-B
28F010
28F010
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VCC
WEÝ
NC
A14
A13
A8
A9
A11
OEÝ
A10
CEÝ
DQ7
DQ6
DQ5
DQ4
DQ3
290406 – 2
Figure 2. DIP Pin Configuration
28F010
28F010
A11
A9
A8
A13
A14
NC
WEÝ
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
OEÝ
A10
CEÝ
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
290406 – 3
Figure 3. TSOP Lead Configuration
3
28F001BX-T/28F001BX-B
290406 – 4
Figure 4. PLCC Lead Configuration
APPLICATIONS
The 28F001BX flash ‘boot block’ memory augments
the non-volatility, in-system electrical erasure and
reprogrammability of Intel’s standard flash memory
by offering four separately erasable blocks and integrating a state machine to control erase and program functions. The specialized blocking architecture and automated programming of the 28F001BX
provide a full-function, non-volatile flash memory
ideal for a wide range of applications, including PC
boot/BIOS memory, minimum-chip embedded program memory and parametric data storage. The
28F001BX combines the safety of a hardware-protected 8-KByte boot block with the flexibility of three
separately reprogrammable blocks (two 4-KByte parameter blocks and one 112-KByte code block) into
one versatile, cost-effective flash memory. Additionally, reprogramming one block does not affect code
stored in another block, ensuring data integrity.
4
The flexibility of flash memory reduces costs
throughout the life cycle of a design. During the early
stages of a system’s life, flash memory reduces prototype development and testing time, allowing the
system designer to modify in-system software electrically versus manual removal of components. During production, flash memory provides flexible firmware for just-in-time configuration, reducing system
inventory and eliminating unnecessary handling and
less reliable socketed connections. Late in the life
cycle, when software updates or code ‘‘bugs’’ are
often unpredictable and costly, flash memory reduces update costs by allowing the manufacturers to
send floppy updates versus a technician. Alternatively, remote updates over a communication link are
possible at speeds up to 9600 baud due to flash
memory’s fast programming time.
28F001BX-T/28F001BX-B
Reprogrammable environments, such as the personal computer, are ideal applications for the
28F001BX. The internal state machine provides
SRAM-like timings for program and erasure, using
the Command and Status Registers. The blocking
scheme allows BIOS update in the main and parameter blocks, while still providing recovery code in the
boot block in the unlikely event a power failure occurs during an update, or where BIOS code is corrupted. Parameter blocks also provide convenient
configuration storage, backing up SRAM and battery
configurations. EISA systems, for example, can
store hardware configurations in a flash parameter
block, reducing system SRAM.
Laptop BIOSs are becoming increasingly complex
with the addition of power management software
and extended system setup screens. BIOS code
complexity increases the potential for code updates
after the sale, but the compactness of laptop designs makes hardware updates very costly. Boot
block flash memory provides an inexpensive update
solution for laptops, while reducing laptop obsolescence. For portable PCs and hand-held equipment,
the deep powerdown mode dramatically lowers sys-
tem power requirements during periods of slow operation or sleep modes.
The 28F001BX gives the embedded system designer several desired features. The internal state machine reduces the size of external code dedicated to
the erase and program algorithms, as well as freeing
the microcontroller or microprocessor to respond to
other system requests during program and erasure.
The four blocks allow logical segmentation of the
entire embedded software: the 8-KByte block for the
boot code, the 112-KByte block for the main program code and the two 4-KByte blocks for updatable
parametric data storage, diagnostic messages and
data, or extensions of either the boot code or program code. The boot block is hardware protected
against unauthorized write or erase of its vital code
in the field. Further, the powerdown mode also locks
out erase or write operations, providing absolute
data protection during system powerup or power
loss. This hardware protection provides obvious advantages for safety related applications such as
transportation, military, and medical. The 28F001BX
is well suited for minimum-chip embedded applications ranging from communications to automotive.
290406 – 5
Figure 5. 28F001BX-T in a 80C188 System
290406 – 6
Figure 6. 28F001BX-B in a 80C51 System
5
28F001BX-T/28F001BX-B
PRINCIPLES OF OPERATION
Data Protection
The 28F001BX introduces on-chip write automation
to manage write and erase functions. The write state
machine allows for 100% TTL-level control inputs,
fixed power supplies during erasure and programming, minimal processor overhead with RAM-like
write timings, and maximum EPROM compatiblity.
Depending on the application, the system designer
may choose to make the VPP power supply switchable (available only when memory updates are required) or hardwired to VPPH. When VPP e VPPL,
memory contents cannot be altered. The 28F001BX
Command Register architecture provides protection
from unwanted program or erase operations even
when high voltage is applied to VPP. Additionally, all
functions are disabled whenever VCC is below the
write lockout voltage VLKO, or when RPÝ is at VIL.
The 28F001BX accommodates either design practice and encourages optimization of the processormemory interface.
After initial device powerup, or after return from
deep powerdown mode (see Bus Operations), the
28F001BX functions as a read-only memory. Manipulation of external memory-control pins yield standard EPROM read, standby, output disable or Intelligent Identifier operations. Both Status Register and
Intelligent Identifiers can be accessed through the
Command Register when VPP e VPPL.
This same subset of operations is also available
when high voltage is applied to the VPP pin. In addition, high voltage on VPP enables successful erasure
and programming of the device. All functions associated with altering memory contentsÐprogram,
erase, status, and inteligent IdentifierÐare accessed
via the Command Register and verified through the
Status Register.
Commands are written using standard microprocessor write timings. Register contents serve as input to
the WSM, which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for programming or erase
operations. With the appropriate command written to
the register, standard microprocessor read timings
output array data, access the intelligent identifier
codes, or output program and erase status for verification.
Interface software to initiate and poll progress of internal program and erase can be stored in any of the
28F001BX blocks. This code is copied to, and executed from, system RAM during actual flash memory
update. After successful completion of program
and/or erase, code execution out of the 28F001BX
is again possible via the Read Array command.
Erase suspend/resume capability allows system
software to suspend block erase and read data/execute code from any other block.
The two-step program/erase write sequence to the
Command Register provides additional software
write protection.
1FFFF
8-KByte BOOT BLOCK
1E000
1DFFF
1D000
1CFFF
1C000
1BFFF
6
4-KByte PARAMETER BLOCK
112-KByte MAIN BLOCK
00000
Figure 7. 28F001BX-T Memory Map
1FFFF
112-KByte MAIN BLOCK
Command Register and Write
Automation
An on-chip state machine controls block erase and
byte program, freeing the system processor for other
tasks. After receiving the erase setup and erase
confirm commands, the state machine controls
block pre-conditioning and erase, returning progress
via the Status Register. Programming is similarly
controlled, after destination address and expected
data are supplied. The program algorithm of past Intel Flash Memories is now regulated by the state
machine, including program pulse repetition where
required and internal verification and margining of
data.
4-KByte PARAMETER BLOCK
04000
03FFF
03000
02FFF
02000
01FFF
4-KByte PARAMETER BLOCK
4-KByte PARAMETER BLOCK
8-KByte BOOT BLOCK
00000
Figure 8. 28F001BX-B Memory Map
28F001BX-T/28F001BX-B
BUS OPERATION
Standby
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
CEÝ at a logic-high level (VIH) places the 28F001BX
in standby mode. Standby operation disables much
of the 28F001BX’s circuitry and substantially reduces device power consumption. The outputs (DQ0 –
DQ7) are placed in a high-impedance state independent of the status of OEÝ. If the 28F001BX is deselected during erase or program, the device will
continue functioning and consuming normal active
power until the operation is completed.
Read
The 28F001BX has three read modes. The memory
can be read from any of its blocks, and information
can be read from the Intelligent Identifier or the
Status Register. VPP can be at either VPPL or VPPH.
Deep Power-Down
The first task is to write the appropriate read mode
command to the Command Register (array, Intelligent Identifier, or Status Register). The 28F001BX
automatically resets to Read Array mode upon initial
device powerup or after exit from deep powerdown.
The 28F001BX has four control pins, two of which
must be logically active to obtain data at the outputs.
Chip Enable (CEÝ) is the device selection control,
and when active enables the selected memory device. Output Enable (OEÝ) is the data input/output
(DQ0 –DQ7) direction control, and when active
drives data from the selected memory onto the I/O
bus. RPÝ and WEÝ must also be at VIH. Figure 12
illustrates read bus cycle waveforms.
The 28F001BX offers a 0.25 mW VCC power-down
feature, entered when RPÝ is at VIL. During read
modes, RPÝ low deselects the memory, places output drivers in a high-impedance state and turns off
all internal circuits. The 28F001BX requires time
tPHQV (see AC Characteristics-Read Only Operations) after return from power-down until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The Command
Register is reset to Read Array, and the Status Register is cleared to value 80H, upon return to normal
operation.
During erase or program modes, RPÝ low will abort
either operation. Memory contents of the block being altered are no longer valid as the data will be
partially programmed or erased. Time tPHWL after
RPÝ goes to logic-high (VIH) is required before another command can be written.
Output Disable
With OEÝ at a logic-high level (VIH), the device outputs are disabled. Output pins (DQ0 –DQ7) are
placed in a high-impedance state.
Table 2. 28F001BX Bus Operations
Mode
Read
Notes
RPÝ
CEÝ
OEÝ
WEÝ
A9
A0
VPP
DQ0–7
1, 2, 3
VIH
VIL
VIL
VIH
X
X
X
DOUT
Output Disable
2
VIH
VIL
VIH
VIH
X
X
X
High Z
Standby
2
VIH
VIH
X
X
X
X
X
High Z
Deep Power Down
2
VIL
X
X
X
X
X
X
High Z
Intelligent Identifier (Mfr)
2, 3, 4
VIH
VIL
VIL
VIH
VID
VIL
X
89H
Intelligent Identifier (Device)
2, 3, 4, 5
VIH
VIL
VIL
VIH
VID
VIH
X
94H, 95H
Write
2, 6, 7, 8
VIH
VIL
VIH
VIL
X
X
X
DIN
NOTES:
1. Refer to DC Characteristics. When VPP e VPPL, memory contents can be read but not programmed or erased.
2. X can be VIL or VIH for control pins and addresses, and VPPL or VPPH for VPP.
3. See DC Characteristics for VPPL, VPPH, VHH and VID voltages.
4. Manufacturer and device codes may also be accessed via a Command Register write sequence. Refer to Table 3. A1 –A8,
A10 – A16 e VIL.
5. Device ID e 94H for the 28F001BX-T and 95H for the 28F001BX-B.
6. Command writes involving block erase or byte program are successfully executed only when VPP e VPPH.
7. Refer to Table 3 for valid DIN during a write operation.
8. Program or erase the boot block by holding RPÝ at VHH or toggling OEÝ to VHH. See AC Waveforms for program/erase
operations.
7
28F001BX-T/28F001BX-B
The use of RPÝ during system reset is important
with automated write/erase devices. When the system comes out of reset it expects to read from the
flash memory. Automated flash memories provide
status information when accessed during write/
erase modes. If a CPU reset occurs with no flash
memory reset, proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data. Intel’s
Flash Memories allow proper CPU initialization following a system reset through the use of the RPÝ
input. In this application RPÝ is controlled by the
same RESETÝ signal that resets the system CPU.
Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manufacturer code, 89H; and the device code, 94H for the
28F001BX-T and 95H for the 28F001BX-B. Programming equipment or the system CPU can then
automatically match the device with its proper erase
and programming algorithms.
PROGRAMMING EQUIPMENT
CEÝ and OEÝ at a logic low level (VIL), with A9 at
high voltage VID (see DC Characteristics) activates
this operation. Data read from locations 00000H and
00001H represent the manufacturer’s code and the
device code respectively.
IN-SYSTEM PROGRAMMING
The manufacturer- and device-codes can also be
read via the Command Register. Following a write of
90H to the Command Register, a read from address
location 00000H outputs the manufacturer code
(89H). A read from address 00001H outputs the device code (94H for the 28F001BX-T and 95H for the
28F001BX-B). It is not necessary to have high voltage applied to VPP to read the Intelligent Identifiers
from the Command Register.
Write
Writes to the Command Register allow read of device data and Intelligent Identifiers. They also control inspection and clearing of the Status Register.
Additionally, when VPP e VPPH, the Command Register controls device erasure and programming. The
contents of the register serve as input to the internal
state machine.
The Command Register itself does not occupy an
addressable memory location. The register is a latch
used to store the command and address and data
information needed to execute the command. Erase
8
Setup and Erase Confirm commands require both
appropriate command data and an address within
the block to be erased. The Program Setup Command requires both appropriate command data and
the address of the location to be programmed, while
the Program command consists of the data to be
written and the address of the location to be programmed.
The Command Register is written by bringing WEÝ
to a logic-low level (VIL) while CEÝ is low. Addresses and data are latched on the rising edge of WEÝ.
Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the AC Waveform for Write Operations, Figure 13, for specific timing parameters.
COMMAND DEFINITIONS
When VPPL is applied to the VPP pin, read operations from the Status Register, intelligent identifiers,
or array blocks are enabled. Placing VPPH on VPP
enables successful program and erase operations
as well.
Device operations are selected by writing specific
commands into the Command Register. Table 3 defines these 28F001BX commands.
Read Array Command
Upon initial device powerup and after exit from
deep-powerdown mode, the 28F001BX defaults to
Read Array mode. This operation is also initiated by
writing FFH into the Command Register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the Command Register contents are altered. Once the internal write
state machine has started an erase or program operation, the device will not recognize the Read Array
command, until the WSM has completed its operation. The Read Array command is functional when
VPP e VPPL or VPPH.
Intelligent Identifier Command for
In-System Programming
The 28F001BX contains an Intelligent Identifier operation to supplement traditional PROM-programming methodology. The operation is initiated by writing 90H into the Command Register. Following the
command write, a read cycle from address 00000H
retrieves the manufacturer code of 89H. A read cycle from address 00001H returns the device code of
94H (28F001BX-T) or 95H (28F001BX-B). To terminate the operation, it is necessary to write another
valid command into the register. Like the Read Array
command, the Intelligent Identifier command is functional when VPP e VPPL or VPPH.
28F001BX-T/28F001BX-B
Table 3. 28F001BX Command Definitions
Command
Bus
First Bus Cycle
Second Bus Cycle
Cycles Notes
Req’d
Operation Address Data Operation Address Data
Read Array/Reset
1
1
Write
X
FFH
Intelligent Identifier
3
2, 3, 4
Write
X
90H
Read
IA
IID
Read Status Register
2
3
Write
X
70H
Read
X
SRD
Write
X
50H
2
Write
BA
20H
Write
BA
D0H
Write
X
B0H
Write
X
D0H
2, 3
Write
PA
40H
Write
PA
PD
Clear Status Register
1
Erase Setup/Erase Confirm
2
Erase Suspend/Erase Resume
2
Program Setup/Program
2
NOTES:
1. Bus operations are defined in Table 2.
2. IA e Identifier Address: 00H for manufacturer code, 01H for device code.
BA e Address within the block being erased.
PA e Address of memory location to be programmed.
3. SRD e Data read from Status Register. See Table 4 for a description of the Status Register bits.
PD e Data to be programmed at location PA. Data is latched on the rising edge of WEÝ.
IID e Data read from Intelligent Identifiers.
4. Following the Intelligent Identifier command, two read operations access manufacture and device codes.
5. Commands other than those shown above are reserved by Intel for future device implementations and should not be
used.
Read Status Register Command
The 28F001BX contains a Status Register which
may be read to determine when a program or erase
operation is complete, and whether that operation
completed successfully. The Status Register may be
read at any time by writing the Read Status Register
command (70H) to the Command Register. After
writing this command, all subsequent read operations output data from the Status Register, until another valid command is written to the Command
Register. The contents of the Status Register are
latched on the falling edge of OEÝ or CEÝ, whichever occurs last in the read cycle. OEÝ or CEÝ
must be toggled to VIH before further reads to update the Status Register latch. The Read Status
Register command functions when VPP e VPPL or
VPPH.
reset by the Clear Status Register command. These
bits indicate various failure conditions (see Table 4).
By allowing system software to control the resetting
of these bits, several operations may be performed
(such as cumulatively programming several bytes or
erasing multiple blocks in sequence). The Status
Register may then be polled to determine if an error
occurred during that series. This adds flexibility to
the way the device may be used.
Additionally, the VPP Status bit (SR.3), when set to
‘‘1’’, MUST be reset by system software before further byte programs or block erases are attempted.
To clear the Status Register, the Clear Status Register command (50H) is written to the Command Register. The Clear Status Register command is functional when VPP e VPPL or VPPH.
Clear Status Register Command
The Erase Status and Program Status bits are set to
‘‘1’’ by the Write State Machine and can only be
9
28F001BX-T/28F001BX-B
Table 4. 28F001BX Status Register Definitions
WSMS
ESS
ES
PS
VPPS
R
R
R
7
6
5
4
3
2
1
0
SR.7 e WRITE STATE MACHINE STATUS
1 e Ready
0 e Busy
SR.6 e ERASE SUSPEND STATUS
1 e Erase Suspended
0 e Erase In Progress/Completed
SR.5 e ERASE STATUS
1 e Error in Block Erasure
0 e Successful Block Erase
SR.4 e PROGRAM STATUS
1 e Error in Byte Program
0 e Successful Byte Program
SR.3 e VPP STATUS
1 e VPP Low Detect; Operation Abort
0 e VPP OK
NOTES:
The Write State Machine Status Bit must first be checked
to determine program or erase completion, before the
Program or Erase Status bits are checked for success.
If the Program AND Erase Status bits are set to ‘‘1s’’ during an erase attempt, an improper command sequence
was entered. Attempt the operation again.
If VPP low status is detected, the Status Register must be
cleared before another program or erase operation is attempted.
The VPP Status bit, unlike an A/D converter, does not
provide continuous indication of VPP level. The WSM interrogates the VPP level only after the program or erase
command sequences have been entered and informs the
system if VPP has not been switched on. The VPP Status
bit is not guaranteed to report accurate feedback between VPPL and VPPH.
SR.2 – SR.0 e RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use and should be
masked out when polling the Status Register.
Erase Setup/Erase Confirm
Commands
Erase is executed one block at a time, initiated by a
two-cycle command sequence. An Erase Setup
command (20H) is first written to the Command
Register, followed by the Erase Confirm command
(D0H). These commands require both appropriate
command data and an address within the block to
be erased. Block preconditioning, erase and verify
are all handled internally by the Write State Machine,
invisible to the system. After receiving the two-command erase sequence, the 28F001BX automatically
outputs Status Register data when read (see Figure
10; Block Erase Flowchart). The CPU can detect the
completion of the erase event by checking the WSM
Status bit of the Status Register (SR.7).
When the Status Register indicates that erase is
complete, the Erase Status bit should be checked. If
erase error is detected, the Status Register should
be cleared. The Command Register remains in Read
Status Register Mode until further commands are issued to it.
This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, block erasure can only occur
when VPP e VPPH. In the absence of this high voltage, memory contents are protected against erasure. If block erase is attempted while VPP e VPPL,
10
the VPP Status bit will be set to ‘‘1’’. Erase attempts
while VPPL k VPP k VPPH produce spurious results
and should not be attempted.
Erase Suspend/Erase Resume
Commands
The Erase Suspend Command allows erase sequence interruption in order to read data from another block of memory. Once the erase sequence is
started, writing the Erase Suspend command (B0H)
to the Command Register requests that the WSM
suspend the erase sequence at a predetermined
point in the erase algorithm. The 28F001BX continues to output Status Register data when read, after
the Erase Suspend command is written to it. Polling
the WSM Status and Erase Suspend Status bits will
determine when the erase operation has been suspended (both will be set to ‘‘1s’’).
At this point, a Read Array command can be written
to the Command Register to read data from blocks
other than that which is suspended. The only other valid commands at this time are Read Status Register (70H) and Erase Resume (D0H), at which time
the WSM will continue with the erase sequence. The
Erase Suspend Status and WSM Status bits of the
Status Register will be cleared. After the Erase Resume command is written to it, the 28F001BX automatically outputs Status Register data when read
(see Figure 11; Erase Suspend/Resume Flowchart).
28F001BX-T/28F001BX-B
Program Setup/Program Commands
Programming is executed by a two-write sequence.
The program Setup command (40H) is written to the
Command Register, followed by a second write
specifying the address and data (latched on the rising edge of WEÝ) to be programmed. The WSM
then takes over, controlling the program and verify
algorithms internally. After the two-command program sequence is written to it, the 28F001BX automatically outputs Status Register data when read
(see Figure 9; Byte Program Flowchart). The CPU
can detect the completion of the program event by
analyzing the WSM Status bit of the Status Register.
Only the Read Status Register command is valid
while programming is active.
When the Status Register indicates that programming is complete, the Program Status bit should be
checked. If program error is detected, the Status
Register should be cleared. The internal WSM verify
only detects errors for ‘‘1s’’ that do not successfully
program to ‘‘0s’’. The Command Register remains in
Read Status Register mode until further commands
are issued to it. If byte program is attempted while
VPP e VPPL, the VPP Status bit will be set to ‘‘1’’.
Program attempts while VPPL k VPP k VPPH produce spurious results and should not be attempted.
The 28F001BX-B and 28F001BX-T are capable of
100,000 program/erase cycles on each parameter
block, main block and boot block.
ON-CHIP PROGRAMMING
ALGORITHM
The 28F001BX integrates the Quick Pulse programming algorithm of prior Intel Flash Memory devices
on-chip, using the Command Register, Status Register and Write State Machine (WSM). On-chip integration dramatically simplifies system software and
provides processor-like interface timings to the
Command and Status Registers. WSM operation, internal program verify and VPP high voltage presence
are monitored and reported via appropriate Status
Register bits. Figure 9 shows a system software
flowchart for device programming. The entire sequence is performed with VPP at VPPH. Program
abort occurs when RPÝ transitions to VIL, or VPP
drops to VPPL. Although the WSM is halted, byte
data is partially programmed at the location where
programming was aborted. Block erasure or a repeat of byte programming will initialize this data to a
known value.
ON-CHIP ERASE ALGORITHM
EXTENDED ERASE/PROGRAM
CYCLING
EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubled; an
expensive solution.
Intel has designed extended cycling capability into
its ETOX flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electrical field is onetenth that of common EEPROMs, minimizing the
probability of oxide defects in the region. Finally, the
peak electric field during erasure is approximately 2
Mv/cm lower than EEPROM. The lower electric field
greatly reduces oxide stress and the probability of
failure.
As above, the Quick Erase algorithm of prior Intel
Flash Memory devices is now implemented internally, including all preconditioning of block data. WSM
operation, erase success and VPP high voltage presence are monitored and reported through the Status
Register. Additionally, if a command other than
Erase Confirm is written to the device after Erase
Setup has been written, both the Erase Status and
Program Status bits will be set to ‘‘1’’. When issuing
the Erase Setup and Erase Confirm commands, they
should be written to an address within the address
range of the block to be erased. Figure 10 shows a
system software flowchart for block erase.
Erase typically takes 1 – 4 seconds per block. The
Erase Suspend/Erase Resume command sequence
allows interrupt of this erase operation to read data
from a block other than that in which erase is
being performed. A system software flowchart is
shown in Figure 11.
The entire sequence is performed with VPP at VPPH.
Abort occurs when RPÝ transitions to VIL or VPP
falls to VPPL, while erase is in progress. Block data is
partially erased by this operation, and a repeat of
erase is required to obtain a fully erased block.
11
28F001BX-T/28F001BX-B
BOOT BLOCK PROGRAM AND
ERASE
The boot block is intended to contain secure code
which will minimally bring up a system and control
programming and erase of other blocks of the device, if needed. Therefore, additional ‘‘lockout’’ protection is provided to guarantee data integrity. Boot
block program and erase operations are enabled
through high voltage VHH on either RPÝ or OEÝ,
and the normal program and erase command sequences are used. Reference the AC Waveforms for
Program/Erase.
If boot block program or erase is attempted while
RPÝ is at VIH, either the Program Status or Erase
Status bit will be set to ‘‘1’’, reflective of the opera-
tion being attempted and indicating boot block lock.
Program/erase attempts while VIH k RPÝ k VHH
produce spurious results and should not be attempted.
In-System Operation
For on-board programming, the RPÝ pin is the most
convenient means of altering the boot block. Before
issuing Program or Erase confirms commands, RPÝ
must transition to VHH. Hold RPÝ at this high voltage throughout the program or erase interval (until
after Status Register confirm of successful completion). At this time, it can return to VIH or VIL.
Bus
Operation
Command
Comments
Write
Program
Setup
Data e 40H
Address e Byte to be
Programmed
Write
Program
Data to be programmed
Address e Byte to be
Programmed
Read
Status Register Data.
Toggle OEÝ or CEÝ to
update Status Register
Check SR.7
1 e Ready, 0 e Busy
Standby
Repeat for subsequent bytes.
Full status check can be done after each byte or after a
sequence of bytes.
Write FFH after the last byte programming operation to
reset the device to Read Array Mode.
Bus
Operation
Command
Comments
Standby
Check SR.3
1 e VPP Low Detect
Standby
Check SR.4
1 e Byte Program Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290406 – 7
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple bytes are
programmed before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 9. 28F001BX Byte Programming Flowchart
12
28F001BX-T/28F001BX-B
Bus
Operation
Command
Comments
Write
Erase
Setup
Data e 20H
Address e Within Block to be erased
Write
Erase
Data e D0H
Address e Within Block to be erased
Read
Status Register Data.
Toggle OEÝ or CEÝ to update Status
Register
Standby
Check SR.7
1 e Ready, 0 e Busy
Repeat for subsequent blocks.
Full status check can be done after each block or after a sequence of
blocks.
Write FFH after the last block erase operation to reset the device to
Read Array Mode.
Bus
Operation
Command
Comments
Standby
Check SR.3
1 e VPP Low Detect
Standby
Check SR.4, 5
Both 1 e Command Sequence Error
Standby
Check SR.5
1 e Block Erase Error
SR.3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
290406 – 8
SR.5 is only cleared by the Clear Status Register Command, in cases
where multiple blocks are erased before full status is checked.
If error is detected, clear the Status Register before attempting retry or
other error recovery.
Figure 10. 28F001BX Block Erase Flowchart
13
28F001BX-T/28F001BX-B
Bus
Operation
Command
Comments
Write
Erase
Suspend
Data e B0H
Write
Erase
Status Register
Data e 70H
Standby/
Read
Read Status Register
Check SR.7
1 e Ready, 0 e Busy
Toggle OEÝ or CEÝ to
Update Status Register
Standby
Check SR.6
1 e Suspended
Write
Read Array
Read
Write
Data e FFH
Read array data from
block other than that
being erased.
Erase Resume
Data e D0H
290406 – 9
Figure 11. 28F001BX Erase Suspend/Resume Flowchart
Programming Equipment
For PROM programming equipment that cannot
bring RPÝ to high voltage, OEÝ provides an alternate boot block access mechanism. OEÝ must transition to VHH a minimum of 480 ns before the initial
program/erase setup command and held at VHH at
least 480 ns after program or erase confirm commands are issued to the device. After this interval,
OEÝ can return to normal TTL levels.
DESIGN CONSIDERATIONS
Three-Line Output Control
Flash memories are often used in larger memory arrays. Intel provides three control inputs to accommo14
date multiple memory connections. Three-line control provides for:
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will
not occur
To efficiently use these control inputs, an address
decoder should enable CEÝ, while OEÝ should be
connected to all memory devices and the system’s
READÝ control line. This assures that only selected
memory devices have active outputs while deselected memory devices are in Standby Mode. RPÝ
should be connected to the system POWERGOOD
signal to prevent unintended writes during system
power transitions. POWERGOOD should also toggle
during system reset.
28F001BX-T/28F001BX-B
Power Supply Decoupling
Flash memory power switching characteristics require careful device coupling. System designers are
interested in 3 supply current issues; standby current
levels (ISB), active current levels (ICC) and transient
peaks producted by falling and rising edges of CEÝ.
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress transient voltage peaks. Each device
should have a 0.1 mF ceramic capacitor connected
between its VCC and GND, and between its VPP and
GND. These high frequency, low inherent-inductance capacitors should be placed as close as possible to the device. Additionally, for every 8 devices,
a 4.7 mF electrolytic capacitor should be placed at
the array’s power supply connection between VCC
and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductances.
VPP Trace on Printed Circuit Boards
Programming flash memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for programming. Use similar trace widths and
layout considerations given to the VCC power bus.
Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots.
VCC, VPP, RPÝ Transitions and the
Command/Status Registers
Programming and erase completion are not guaranteed if VPP drops below VPPH. If the VPP Status bit of
the Status Register (SR.3) is set to ‘‘1’’, a Clear
Status Register command MUST be issued before
further program/erase attempts are allowed by the
WSM. Otherwise, the Program (SR.4) or Erase
(SR.5) Status bits of the Status Register will be set
to ‘‘1’’ if error is detected. RPÝ transitions to VIL
during program and erase also abort the operations.
Data is partially altered in either case, and the command sequence must be repeated after normal operation is restored. Device poweroff, or RPÝ transitions to VIL, clear the Status Register to initial value 80H.
The Command Register latches commands as issued by system software and is not altered by VPP
or CEÝ transitions or WSM actions. Its state upon
powerup, after exit from Deep-Powerdown or after
VCC transitions below VLKO, is FFH, or Read Array
Mode.
After program or erase is complete, even after VPP
transitions down to VPPL, the Command Register
must be reset to read array mode via the Read Array
command if access to the memory array is desired.
Power Up/Down Protection
The 28F001BX is designed to offer protection
against accidental erasure or programming during
power transitions. Upon power-up, the 28F001BX is
indifferent as to which power supply, VPP or VCC,
powers up first. Power supply sequencing is not required. Internal circuitry in the 28F001BX ensures
that the Command Register is reset to Read Array
mode on power up.
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is
active. Since both WEÝ and CEÝ must be low for a
command write, driving either to VIH will inhibit
writes. The Command Register architecture provides
an added level of protection since alteration of memory contents only occurs after successful completion
of the two-step command sequences.
Finally, the device is disabled, until RPÝ is brought
to VIH, regardless of the state of its control inputs.
This provides an additional level of protection.
28F001BX Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases usable battery life because the 28F001BX does not
consume any power to retain code or data when the
system is off.
In addition, the 28F001BX’s Deep-Powerdown mode
ensures extremely low power dissipation even when
system power is applied. For example, laptop and
other PC applications, after copying BIOS to DRAM,
can lower RPÝ to VIL, producing negligible power
consumption. If access to the boot code is again
needed, as in case of a system RESETÝ, the part
can again be accessed, following the tPHAV wakeup
cycle required after RPÝ is first raised back to VIH.
The first address presented to the device while in
powerdown requires time tPHAV, after RPÝ transitions high, before outputs are valid. Further accesses follow normal timing. See AC CharacteristicsÐRead-Only Operations and Figure 12 for more
information.
15
28F001BX-T/28F001BX-B
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Operating Temperature
During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0§ C to 70§ C(1)
During Erase/Program ÀÀÀÀÀÀÀÀÀÀÀ0§ C to 70§ C(1)
Operating Temperature
During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 40§ C to a 85§ C(2)
During Erase/Program ÀÀÀÀÀÀ b 40§ C to a 85§ C(2)
Temperature under Bias ÀÀÀÀÀÀÀÀÀ b 10§ C to 80§ C(1)
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
Temperature under Bias ÀÀÀÀÀÀÀ b 20§ C to a 90§ C(2)
Storage TemperatureÀÀÀÀÀÀÀÀÀÀÀÀÀ b 65§ C to 125§ C
Voltage on Any Pin
(except A9, RPÝ, OEÝ, VCC and VPP)
with Respect to GND ÀÀÀÀÀÀÀÀÀÀ b 2.0V to 7.0V(3)
Voltage on A9, RPÝ, and OEÝ
with Respect to GND ÀÀÀÀÀÀÀ b 2.0V to 13.5V(3, 4)
VPP Program Voltage
with Respect to GND
During Erase/Program ÀÀÀÀÀÀ b 2.0V to 14.0V(3, 4)
VCC Supply Voltage
with Respect to GND ÀÀÀÀÀÀÀÀÀÀ b 2.0V to 7.0V(3)
Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA(5)
OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
0
70
§C
b 40
85
§C
5.50
V
TA
Operating Temperature(1)
TA
Operating Temperature(2)
VCC
Supply Voltage
4.50
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Operating temperature is for extended temperature product defined by this specification.
3. Minimum DC voltage is b0.5V on input/output pins. During transitions, this level may undershoot to b2.0V for periods
k 20 ns. Maximum DC voltage on input/output pins is VCC a 0.5V which, during transitions, may overshoot to VCC a 2.0V
for periods k20 ns.
4. Maximum DC voltage on A9 or VPP may overshoot to a 14.0V for periods k20 ns.
5. Output shorted for no more than one second. No more than one output shorted at a time.
DC CHARACTERISTICS
VCC e 5.0V g 10%, TA e 0§ C to a 70§ C
Symbol
Parameter
Notes Min
Typ
Max
Unit
Test Conditions
IIL
Input Load Current
1
g 1.0
mA
VCC e VCC Max
VIN e VCC or GND
ILO
Output Leakage Current
1
g 10
mA
VCC e VCC Max
VOUT e VCC or GND
ICCS
VCC Standby Current
1.2
2.0
mA
VCC e VCC Max
CEÝ e RPÝ e VIH
30
100
mA
VCC e VCC Max
CEÝ e RPÝ e VCC g 0.2V
0.05
1.0
mA
RPÝ e GND g 0.2V
ICCD
16
VCC Deep Power-Down Current
1
28F001BX-T/28F001BX-B
DC CHARACTERISTICS (Continued)
VCC e 5.0V g 10%, TA e 0§ C to a 70§ C
Symbol
Parameter
Notes Min Typ
Max
Unit
Test Conditions
ICCR
VCC Read Current
1
13
30
mA VCC e VCC Max, CEÝ e VIL
f e 8 MHz, IOUT e 0 mA
ICCP
VCC Programming Current
1
5
20
mA Programming in Progress
ICCE
VCC Erase Current
1
6
20
mA Erase in Progress
ICCES
VCC Erase Suspend Current
1, 2
5
10
mA Erase Suspended
CEÝ e VIH
IPPS
VPP Standby Current
1
g1
g 10
mA VPP s VCC
90
200
mA VPP l VCC
IPPD
VPP Deep Power-Down Current
1
0.80
1.0
mA RPÝ e GND g 0.2V
IPPP
VPP Programming Current
1
6
30
mA VPP e VPPH
Programming in Progress
IPPE
VPP Erase Current
1
6
30
mA VPP e VPPH
Erase in Progress
IPPES
VPP Erase Suspend Current
1
90
300
mA VPP e VPPH
Erase Suspended
IID
A9 Intelligent Identifier Current
1
90
500
mA A9 e VID
VIL
Input Low Voltage
b 0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
VID
A9 Intelligent Identifier Voltage
VPPL
VPP during Normal Operations
VPPH
VLKO
VHH
0.8
V
VCC a 0.5
V
0.45
V
VCC e VCC Min
IOL e 5.8 mA
V
VCC e VCC Min
IOH e 2.5 mA
2.4
11.5
13.0
V
0.0
6.5
V
VPP during Prog/Erase Operations
11.4 12.0
12.6
VCC Erase/Write Lock Voltage
2.5
RPÝ, OEÝ Unlock Voltage
11.4
3
V
V
12.6
V
Boot Block Prog/Erase
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC e 5.0V, VPP e 12.0V, TA e 25§ C. These currents
are valid for all product versions (packages and speeds).
2. ICCES is specified with the device deselected. If the 28F001BX is read while in Erase Suspend mode, current draw is the
sum of ICCES and ICCR.
3. Erase/Programs are inhibited when VPP e VPPL and not guaranteed in the range between VPPH and VPPL.
17
28F001BX-T/28F001BX-B
DC CHARACTERISTICS
VCC e 5.0V g 10%, TA e b 40§ C to a 85§ C
Symbol
Parameter
Notes
Min
Typ
Max
Unit
Test Conditions
IIL
Input Load Current
1
g 1.0
mA VCC e VCC Max
VIN e VCC or GND
ILO
Output Leakage Current
1
g 10
mA VCC e VCC Max
VOUT e VCC or GND
ICCS
VCC Standby Current
1.2
2.0
mA VCC e VCC Max
CEÝ e RPÝ e VIH
30
150
mA VCC e VCC Max
CEÝ e RPÝ e VCC g 0.2V
ICCD
VCC Deep Power-Down Current
1
0.05
2.0
mA RPÝ e GND g 0.2V
ICCR
VCC Read Current
1
13
35
mA VCC e VCC Max, CEÝ e VIL
f e 8 MHz, IOUT e 0 mA
ICCP
VCC Programming Current
1
5
20
mA Programming in Progress
ICCE
VCC Erase Current
ICCES
VCC Erase Suspend Current
IPPS
VPP Standby Current
1
6
20
mA Erase in Progress
1, 2
5
10
mA Erase Suspended
CEÝ e VIH
1
g1
g 15
mA VPP s VCC
90
400
mA VPP l VCC
IPPD
VPP Deep Power-Down Current
1
0.80
1.0
mA RPÝ e GND g 0.2V
IPPP
VPP Programming Current
1
6
30
mA VPP e VPPH
Programming in Progress
IPPE
VPP Erase Current
1
6
30
mA VPP e VPPH
Erase in Progress
IPPES
VPP Erase Suspend Current
1
90
400
mA VPP e VPPH
Erase Suspended
IID
A9 Intelligent Identifier Current
1
90
500
mA A9 e VID
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH1
Output High Voltage (TTL)
VOH2
Output High Voltage (CMOS)
b 0.5
2.0
V VCC e VCC Min
IOL e 5.8 mA
2.4
V VCC e VCC Min
IOH e 2.5 mA
0.85 VCC
V VCC e VCC Min
IOH e b 2.5 mA
VCC b 0.4
VCC e VCC Min
IOH e b 100 mA
A9 Intelligent Identifier Voltage
VPPL
VPP during Normal Operations
VPPH
VPP during Prog/Erase Operations
11.4
VLKO
VCC Erase/Write Lock Voltage
2.5
VHH
RPÝ, OEÝ Unlock Voltage
11.4
3
V
VCC a 0.5 V
0.45
VID
18
0.8
11.5
13.0
V
0.0
6.5
V
12.6
V
12.0
V
12.6
V Boot Block Prog/Erase
28F001BX-T/28F001BX-B
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC e 5.0V, VPP e 12.0V, TA e 25§ C. These currents
are valid for all product versions (packages and speeds).
2. ICCES is specified with the device deselected. If the 28F001BX is read while in Erase Suspend mode, current draw is the
sum of ICCES and ICCR.
3. Erase/Programs are inhibited when VPP e VPPL and not guaranteed in the range between VPPH and VPPL.
CAPACITANCE(1)
Symbol
TA e 25§ C, f e 1 MHz
Parameter
Max
Unit
Conditions
CIN
Input Capacitance
8
pF
VIN e 0V
COUT
Output Capacitance
12
pF
VOUT e 0V
NOTE:
1. Sampled, not 100% tested.
AC INPUT/OUTPUT REFERENCE WAVEFORM
290406 – 10
A.C. test inputs are driven at VOH (2.4 VTTL) for a Logic ‘‘1’’ and VOL (0.45 VTTL) for a Logic ‘‘0’’. Input timing begins at
VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) k 10 ns.
STANDARD TEST CONFIGURATION
AC TESTING LOAD CIRCUIT
HIGH SPEED TEST CONFIGURATION
AC TESTING LOAD CIRCUIT
290406 – 11
CL e 100 pF
CL Includes Jig Capacitance
RL e 3.3 kX
290406 – 23
CL e 30 pF
CL Includes Jig Capacitance
RL e 3.3 kX
19
28F001BX-T/28F001BX-B
AC CHARACTERISTICSÐRead-Only Operations(1)
28F001BX-70
Symbol
Parameter
Notes
VCC e 5V
g 5%
30 pF
Min
tAVAV
tRC Read Cycle Time
70
tAVQV tACC Address to Output Delay
tELQV
tCE CEÝ to Output Delay
2
tGLQV tOE OEÝ to Output Delay
2
tELQX
tLZ CEÝ to Output in Low Z
3
tEHQZ tHZ CEÝ to Output in High Z
3
tGLQX tOLZ OEÝ to Output in Low Z
3
tOH Output Hold from
Address CEÝ, or OEÝ
Change, Whichever
Occurs First
VCC e 5V
g 10%
100 pF
Min
Units
Max
90
ns
90
ns
70
75
90
ns
600
600
ns
35
ns
30
0
55
0
0
55
0
30
ns
35
0
30
0
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OEÝ may be delayed up to tCE – tOE after the falling edge of CEÝ without impact on tCE.
3. Sampled, but not 100% tested.
4. See High Speed Test Configuration.
5. See Standard Test Configuration.
20
Min
75
27
0
VCC e 5V
g 10%
100 pF
600
0
3
3
Max
75
70
tPHQV tPWH RPÝ to Output Delay
tGHQZ tDF OEÝ to Output in High Z
Max
28F001BX-90
ns
30
0
ns
ns
ns
28F001BX-T/28F001BX-B
AC CHARACTERISTICSÐRead-Only Operations(1)
Versions(2)
Symbol
VCC g 10%
Parameter
Notes
tAVAV
tRC
Read Cycle Time
tAVQV
tACC
Address to Output Delay
tELQV
tCE
CEÝ to Output Delay
tPHQV
tPWH
RPÝ High to Output Delay
tGLQV
tOE
OEÝ to Output Delay
3
tELQX
tLZ
CEÝ to Output Low Z
4
tEHQZ
tHZ
CEÝ High to Output High Z
4
tGLQX
tOLZ
OEÝ to Output Low Z
4
tGHQZ
tDF
OEÝ High to Output High Z
4
tOH
Output Hold from
Addresses, CEÝ or OEÝ
Change, Whichever is First
4
E28F001BX-120
N28F001BX-120
P28F001BX-120
E28F001BX-150
TE28F001BX-150
N28F001BX-150
TN28F001BX-150
P28F001BX-150
Min
Min
Max
120
3
Max
150
ns
120
150
ns
120
150
ns
600
600
ns
50
55
ns
0
0
55
0
ns
55
0
30
0
Unit
ns
30
0
ns
ns
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. Model Number Prefixes: E e TSOP (Standard Pinout), N e PLCC, P e PDIP, T e Extended Temperature. Refer to
standard test configuration.
3. OEÝ may be delayed up to tCE – tOE after the falling edge of CEÝ without impact on tCE.
4. Sampled, not 100% tested.
21
290406– 12
28F001BX-T/28F001BX-B
Figure 12. AC Waveform for Read Operations
22
28F001BX-T/28F001BX-B
AC CHARACTERISTICSÐWrite/Erase/Program Operations(1, 9)
28F001BX-70
Symbol
tAVAV
tPHWL
Parameter
tWC
Write Cycle Time
tPS
RPÝ High Recovery to WEÝ
Notes
2
28F001BX-90
VCC e 5V
g 5%(10)
30 pF
VCC e 5V
g 10%(11)
100 pF
Min
Min
Max
Max
VCC e 5V
g 10%(11)
100 pF
Min
Units
Max
70
75
90
ns
480
480
480
ns
Going Low
tELWL
tCS
CEÝ Setup to WEÝ Going Low
10
10
10
ns
tWLWH
tWP
WEÝ Pulse Width
35
40
40
ns
2
100
100
100
ns
tPHHWH tPHS RPÝ VHH Setup to WEÝ Going
High
tVPWH
tVPS VPP Setup to WEÝ Going High
2
100
100
100
ns
tAVWH
tAS
Address Setup to WEÝ Going
High
3
35
40
40
ns
tDVWH
tDS
Data Setup to WEÝ Going High
4
tWHDX
tDH
Data Hold from WEÝ High
tWHAX
tAH
Address Hold from WEÝ High
10
10
10
ns
tWHEH
tCH
CEÝ Hold from WEÝ High
10
10
10
ns
tWHWL
tWPH WEÝ Pulse Width High
35
40
40
ns
10
10
10
ns
35
35
35
ns
tWHQV1
Duration of Programming
Operation
5, 6, 7
15
15
15
ms
tWHQV2
Duration of Erase Operation
(Boot)
5, 6, 7
1.3
1.3
1.3
sec
tWHQV3
Duration of Erase Operation
(Parameter)
5, 6, 7
1.3
1.3
1.3
sec
tWHQV4
Duration of Erase Operation
(Main)
5, 6, 7
3.0
3.0
3.0
sec
tWHGL
0
0
0
ms
tQVVL
tVPH VPP Hold from Valid SRD
Write Recovery before Read
2, 6
0
0
0
ns
tQVPH
tPHH RPÝ VHH Hold from Valid SRD
2, 7
0
0
0
ns
tPHBR
Boot-Block Relock Delay
2
100
100
100
ns
NOTES:
1. Read timing characteristics during erase and program operations are the same as during read-only operations. Refer to
AC Characteristics for Read-Only Operations.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN for byte programming or block erasure.
4. Refer to Table 3 for valid DIN for byte programming or block erasure.
5. The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel
Flash Memory, including byte program and verify (programming) and block precondition, precondition verify, erase and erase
verify (erasing).
6. Program and erase durations are measured to completion (SR.7 e 1). VPP should be held at VPPH until determination of
program/erase success (SR.3/4/5 e 0).
7. For boot block programming and erasure, RPÝ should be held at VHH until determination of program/erase success
(SR.3/4/5 e 0).
8. Alternate boot block access method.
9. Erase/Program Cycles on extended temperature products is 10,000 cycles.
10. See high speed test configuration.
11. See standard test configuration.
23
28F001BX-T/28F001BX-B
AC CHARACTERISTICSÐWrite/Erase/Program Operations(1, 9)
VCC g 10%(10)
Versions
Symbol
Parameter
28F001BX-120
Notes
tAVAV
tWC
Write Cycle Time
tPHWL
tPS
RPÝ High Recovery to WEÝ Going Low
tELWL
tCS
CEÝ Setup to WEÝ Going Low
tWLWH
tWP
WEÝ Pulse Width
2
Min
Max
28F001BX-150
Min
Max
Unit
120
150
ns
480
480
ns
10
10
ns
50
50
ns
2
100
100
ns
VPP Setup to WEÝ Going High
2
100
100
ns
Address Setup to WEÝ Going High
3
50
50
ns
tDS
Data Setup to WEÝ Going High
4
50
50
ns
tDH
Data Hold from WEÝ High
10
10
ns
tWHAX
tAH
Address Hold from WEÝ High
10
10
ns
tWHEH
tCH
CEÝ Hold from WEÝ High
10
10
ns
tWHWL
tWPH WEÝ Pulse Width High
tPHHWH tPHS
RPÝ VHH Setup to WEÝ Going High
tVPWH
tVPS
tAVWH
tAS
tDVWH
tWHDX
50
50
ns
tWHQV1
Duration of Programming Operation
5, 6, 7
15
15
ms
tWHQV2
Duration of Erase Operation (Boot)
5, 6, 7
1.3
1.3
sec
tWHQV3
Duration of Erase Operation (Parameter)
5, 6, 7
1.3
1.3
sec
tWHQV4
Duration of Erase Operation (Main)
5, 6, 7
3.0
3.0
sec
tWHGL
Write Recovery before Read
0
0
ms
tQVVL
tVPH
VPP Hold from Valid SRD
2, 6
0
0
ns
tQVPH
tPHH
RPÝ VHH Hold from Valid SRD
2, 7
0
0
ns
tPHBR
Boot-Block Relock Delay
2
100
100
ns
PROM Programmer Specifications
Versions
Symbol
VCC g 10%
Parameter
28F001BX-120
Notes
Min
Max
28F001BX-150
Min
Max
Unit
tGHHWL
OEÝ VHH Setup to WEÝ Going Low
2, 8
480
480
ns
tWHGH
OEÝ VHH Hold from WEÝ High
2, 8
480
480
ns
NOTES:
1. Read timing characteristics during erase and program operations are the same as during read-only operations. Refer to
AC Characteristics for Read-Only Operations.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN for byte programming or block erasure.
4. Refer to Table 3 for valid DIN for byte programming or block erasure.
5. The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel
Flash Memory, including byte program and verify (programming) and block precondition, precondition verify, erase and erase
verify (erasing).
6. Program and erase durations are measured to completion (SR.7 e 1). VPP should be held at VPPH until determination of
program/erase success (SR.3/4/5 e 0).
7. For boot block programming and erasure, RPÝ should be held at VHH until determination of program/erase success
(SR.3/4/5 e 0).
8. Alternate boot block access method.
9. Erase/Program Cycles on extended temperature products is 10,000 cycles.
10. See standard test configuration.
24
28F001BX-T/28F001BX-B
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Boot Block Erase Time
Notes
2
28F001BX-120
Min
28F001BX-150
Typ(1)
Max
2.10
14.9
Min
Typ(1)
Max
2.10
14.9
Unit
Sec
Boot Block Program Time
2
0.15
0.52
0.15
0.52
Sec
Parameter Block Erase Time
2
2.10
14.6
2.10
14.6
Sec
Parameter Block Program Time
2
0.07
0.26
0.07
0.26
Sec
Main Block Erase Time
2
3.80
20.9
3.80
20.9
Sec
Main Block Program Time
2
2.10
7.34
2.10
7.34
Sec
Chip Erase Time
2
10.10
65
10.10
65
Sec
Chip Program Time
2
2.39
8.38
2.39
8.38
Sec
NOTES:
1. 25§ C, 12.0 VPP.
2. Excludes System-Level Overhead.
25
28F001BX-T/28F001BX-B
290406 – 19
Figure 13. 28F001BX Typical
Programming Capability
290406 – 21
Figure 15. 28F001BX Typical Erase Capability
26
290406 – 20
Figure 14. 28F001BX Typical
Programming Time at 12V
290406 – 22
Figure 16. 28F001BX Typical Erase Time at 12V
290406– 13
28F001BX-T/28F001BX-B
Figure 17. AC Waveform for Write Operations
27
28F001BX-T/28F001BX-B
290406 – 15
Figure 18. Alternate Boot Block Access Method Using OEÝ
28
28F001BX-T/28F001BX-B
AC CHARACTERISTICS FOR CEÝ-CONTROLLED WRITES(1)
28F001BX-70
Symbol
Parameter
tAVAV
tWC
Write Cycle Time
tPHEL
tPS
RPÝ High Recovery to CEÝ
Going Low
tWLEL
tWS
WEÝ Setup to CEÝ Going Low
tCP
CEÝ Pulse Width
tELEH
Notes
2
28F001BX-90
VCC e 5V
g 5%(8)
30 pF
VCC e 5V
g 10%(9)
100 pF
Min
Min
Max
Max
VCC e 5V
g 10%(9)
100 pF
Min
Units
Max
70
75
90
ns
480
480
480
ns
0
0
0
ns
50
55
55
ns
tPHHEH tPHS RPÝ VHH Setup to CEÝ Going
High
2
100
100
100
ns
tVPEH
tVPS VPP Setup to CEÝ Going High
2
100
100
100
ns
tAVEH
tAS
Address Setup to CEÝ Going
High
3
35
40
40
ns
tDVEH
tDS
Data Setup to CEÝ Going High
4
35
40
40
ns
tEHDX
tDH
Data Hold from CEÝ High
10
10
10
ns
tEHAX
tAH
Address Hold from CEÝ High
10
10
10
ns
0
0
0
ns
tEHWH tWH WEÝ Hold from CEÝ High
tEHEL
20
20
20
ns
tEHQV1
tEPH CEÝ Pulse Width High
Duration of Programming
Operation
5, 6
15
15
15
ms
tEHQV2
Duration of Erase Operation
(Boot)
5, 6
1.3
1.3
1.3
sec
tEHQV3
Duration of Erase Operation
(Parameter)
5, 6
1.3
1.3
1.3
sec
tEHQV4
Duration of Erase Operation
(Main)
5, 6
3.0
3.0
3.0
sec
tEHGL
Write Recovery before Read
0
0
0
ms
tQVVL
tVPH VPP Hold from Valid SRD
2, 5
0
0
0
ns
tQVPH
tPHH RPÝ VHH Hold from Valid SRD
2, 6
0
0
0
ns
tPHBR
Boot-Block Relock Delay
2
100
100
100
ns
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CEÝ and WEÝ. In systems where
CEÝ defines the write pulse width (within a longer WEÝ timing waveform), all set-up, hold and inactive WEÝ times should
be measured relative to the CEÝ waveform.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN for byte programming or block erasure.
4. Refer to Table 3 for valid DIN for byte programming or block erasure.
5. Program and erase durations are measured to completion (SR.7 e 1). VPP should be held at VPPH until determination of
program/erase success (SR.3/4/5 e 0).
6. For boot block programming and erasure, RPÝ should be held at VHH until determination of program/erase success
(SR.3/4/5 e 0).
7. Alternate boot block access method.
8. See high speed test configuration.
9. See standard text configuration.
29
28F001BX-T/28F001BX-B
AC CHARACTERISTICS FOR CEÝ-CONTROLLED WRITES(1)
Versions
Symbol
VCC g 10%
Parameter
28F001BX-120
Notes
Min
28F001BX-150
Max
Min
Max
Unit
tAVAV
tWC
Write Cycle Time
tPHEL
tPS
RPÝ High Recovery to CEÝ Going Low
tWLEL
tWS
WEÝ Setup to CEÝ Going Low
tELEH
tCP
CEÝ Pulse Width
tPHHEH
tPHS RPÝ VHH Setup to CEÝ Going High
2
tVPEH
tVPS VPP Setup to CEÝ Going High
2
tAVEH
tAS
Address Setup to CEÝ Going High
3
tDVEH
tDS
Data Setup to CEÝ Going High
4
50
50
ns
tEHDX
tDH
Data Hold from CEÝ High
10
10
ns
tEHAX
tAH
Address Hold from CEÝ High
15
15
ns
tEHWH
tWH
WEÝ Hold from CEÝ High
0
0
ns
tEHEL
tEPH CEÝ Pulse Width High
2
120
150
ns
480
480
ns
0
0
ns
70
70
ns
100
100
ns
100
100
ns
50
50
ns
25
25
ns
tEHQV1
Duration of Programming Operation
5, 6
15
15
ms
tEHQV2
Duration of Erase Operation (Boot)
5, 6
1.3
1.3
sec
tEHQV3
Duration of Erase Operation (Parameter)
5, 6
1.3
1.3
sec
tEHQV4
Duration of Erase Operation (Main)
5, 6
3.0
3.0
sec
tEHGL
Write Recovery before Read
0
0
ms
tQVVL
tVPH VPP Hold from Valid SRD
2, 5
0
0
ns
tQVPH
tPHH RPÝ VHH Hold from Valid SRD
2, 6
0
0
ns
tPHBR
Boot-Block Relock Delay
2
100
100
ns
PROM Programmer Specifications
Versions
VCC g 10%
28F001BX-120
Notes
Min
Max
28F001BX-150
Min
Max
Unit
Symbol
Parameter
tGHHEL
OEÝ VHH Setup to CEÝ Going Low
2, 7
480
480
ns
tEHGH
OEÝ VHH Hold from CEÝ High
2, 7
480
480
ns
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CEÝ and WEÝ. In systems where
CEÝ defines the write pulse width (within a longer WEÝ timing waveform), all set-up, hold and inactive WEÝ times should
be measured relative to the CEÝ waveform.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN for byte programming or block erasure.
4. Refer to Table 3 for valid DIN for byte programming or block erasure.
5. Program and erase durations are measured to completion (SR.7 e 1). VPP should be held at VPPH until determination of
program/erase success (SR.3/4/5 e 0).
6. For boot block programming and erasure, RPÝ should be held at VHH until determination of program/erase success
(SR.3/4/5 e 0).
7. Alternate boot block access method.
30
290406– 16
28F001BX-T/28F001BX-B
Figure 19. Alternate AC Waveform for Write Operations
31
28F001BX-T/28F001BX-B
ORDERING INFORMATION
290406 – 18
VALID COMBINATIONS:
Commercial
Extended
32-Lead TSOP
32-Lead PLCC
E28F001BX-T70
N28F001BX-T70
P28F001BX-T70
32-Pin PDIP
E28F001BX-T90
N28F001BX-T90
P28F001BX-T90
E28F001BX-T120
N28F001BX-T120
P28F001BX-T120
E28F001BX-T150
N28F001BX-T150
P28F001BX-T150
E28F001BX-B70
N28F001BX-B70
P28F001BX-B70
E28F001BX-B90
N28F001BX-B90
P28F001BX-B90
E28F001BX-B120
N28F001BX-B120
P28F001BX-B120
E28F001BX-B150
N28F001BX-B150
P28F001BX-B150
TE28F001BX-T90
TN28F001BX-T90
TP28F001BX-T90
TE28F001BX-T150
TN28F001BX-T150
TP28F001BX-B90
TE28F001BX-B90
TN28F001BX-B90
TE28F001BX-B150
TN28F001BX-B150
ADDITIONAL INFORMATION
References
Order Number
32
Document
292046
AP-316
‘‘Using Flash Memory for In-System Reprogrammable Nonvolatile Storage’’
292077
AP-341
‘‘Designing an Updateable BIOS Using Flash Memory’’
292161
AP-608
‘‘Implementing a Plug and Play BIOS Using Intel’s Boot Block Flash Memory’’
292178
AP-623
‘‘Multi-Site Layout Planning Using Intel’s Boot Block Flash Memory’’
294005
ER-20
‘‘ETOX II Flash Memory Technology’’
28F001BX-T/28F001BX-B
Revision History
Number
-004
Description
Removed Preliminary classification.
Latched address A16 in Figure 5.
Updated Boot Block Program and Erase section: ‘‘If boot block program or erase is attempted
while RPÝ is at VIH, either the Program Status or Erase Status bit will be set to ‘‘1’’,
reflective of the operation being attempted and indicating boot block lock.’’
Updated Figure 11, 28F001BX Erase Suspend/Resume Flowchart
Added DC Characteristics typical current values
Combined VPP Standby current and VPP Read current into one VPP Standby current spec with
two test conditions (DC Characteristics table)
Added maximum program/erase times to Erase and Programming Performance table.
Added Figures 13–16
Added Extended Temperature proliferations
-005
PWD changed to RPÝ for JEDEC standardization compatibility
Revised symbols, i.e.; CE, OE, etc. to CEÝ, OEÝ, etc.
-006
Added specifications for -90 and -70 product versions.
Added VOH CMOS Specification.
-007
Added reference to 28F001BN.
33