Databook.fxp 1/13/99 2:09 PM Page x x 01/99 IFPA300, IFPA301 Monolithic JFET Preamplifier Absolute maximum ratings at TA = 25°C Description & Features The IFPA300 series is an inverting transimpedance amplifier featuring extremely low noise and a wide gain-bandwidth suitable as a charge-sensitive preamplifier for a broad range of applications. All pins (except Input) referenced to Bias 3 The monolithic IFPA300 series contain 8 n-channel epitaxial-channel diffused-gate JFETs to achieve optimally low 1/f noise performance over a wide temperature range (120K-300K). Operating Temperature DC open loop gain The 300/301 Series gives more flexibility with respect to output transistor drain. 85 dB GBW 200 MHz e¯ N @ 10 Hz Input to Bias 3 ØV Power Dissipation 225 mW Derating Factor 1.8 mW/°C 150°C At this time, there are two units in this family. 3.0 nV/√Hz The 310/311 Series ties the output transistor drain to the VDD line. <100 mW Simplified Schematic Circuit General Specifications Power Dissipation at VDD = 12 V Input Leakage Current (T = 300 K) 10 pA Input-Referred Noise Voltage (f = 10 kHz) 0.6 nV/√Hz Input-Referred Noise Voltage (f = 10 Hz) 3.0 nV/√Hz Output Range at VDD = 12 V 85 dB VDD J4 4.0 V (5.0 V Max) J7 Designed to drive 50Ω load. Substrate J3 Charge Sensitive Preamplifier Specifications The IFPA300 Series is actually tailored to detector capacitance in the 100 Ð 1000 pF range. Input Open-Loop Capacitance 60 pF Rise Time (CD = 500 pF, Cf = 33 pF) 20 ns Equivalent Noise Charge (Measured with semigaussian shaping, peaking time = tp) J8 Bias 1 J2 Open Drain Output J6 Open Source Output Bias 2 Input J1 Bias 3 J5 VSS 4200 e– rms at CD @ 500 pF, tp = 0.2 µm 3200 e– rms at CD @ 500 pF, tp = 1.0 µm Packages & Test Circuit Overside 4200 e– rms at CD @ 500 pF, tp = 4.0 µm 1000 N. Shiloh Road, Garland, TX 75042 (972) 487-1287 FAX (972) 276-3375 www.interfet.com Databook.fxp 1/13/99 2:09 PM Page xi xi 01/99 IFPA300, IFPA301 Monolithic JFET Preamplifier Input FET J1 selected to the following elecrical parameters. Parameter Conditions Min BVGSS Vds = 0, Ig = 1 µA – 25 IGSS Vds = 0, Vgs = – 10 V IDSS Vds = 0, Vgs = 10 V VGS(OFF) Vds = 0, Id = 1 µA GM Vgs = 0, Vds = 10 V VGSF Id = 1 µA Max VDD = +12 V DUT Units Volts 2 nA 40 500 mA 1 2 Volts 50 mM 0.35 0.65 VDD J4 Substrate J7 120K J3 J8 Bias 1 J2 Volts J6 Parameter Conditions Min Max Units VDCout Vdd = 12 V, – VS = – 6 V Test pt #1 6 10 V Vin Vdd = 12 V, – VS = – 6 V Test pt #2 – 0.6 – 1.6 V VACout Vdd = 12 V, – VS = – 6 V t = O µsec VACout Vdd = 12 V, – VS = – 6 V t = 100 µsec Input 20K J1 J5 Bias 3 50 mV 20 mV VSS Test Point #2 2MΩ 10pF AC Input Test Point # Open Source Output Bias 2 Test Circuit Reference Open Drain Output 1MΩ 10KΩ 10pF – Vsupply = – 6 V 0.165 (4.19) 0.185 (4.70) 0.335 (8.51) 0.370 (9.40) 0.305 (7.75) 0.335 (8.51) 0.010 (0.25) 0.040 (1.02) 8 Leads - Dia. 0.016 (0.41) 0.021 (0.53) 0.029 (0.74) 0.045 (1.14) 0.200 (5.08) Basic 5 6 8 7 6 5 Top 1 2 3 4 7 0.050 (1.27) 4 45° 0.010 (0.25) 0.040 (1.02) 8 3 Standoff 0.110 (2.79) 0.160 (4.06) 0.500 (12.70) 0.244 (6.20) 0.158 (4.01) 0.228 (5.79) 0.150 (3.81) 0.028 (0.71) 0.024 (0.61) 1 0.022 (0.56) 0.018 (0.046 0.018 (0.46 0.014 (0.36) 0.049 (1.24) 0.059 (1.50) 0.015 (0.37) Min. 0.069 (1.75) 0.053 (1.35) 2 0.028 (0.71) Bottom View 0.034 (0.86) 0.197 (5.00) 0.188 (4.78) 45° 0.009 (0.23) 0.007 (0.18) IFPA300 uses TO-99 Package IFPA301 uses SOIC-8 Package Dimensions in Inches (mm) Dimensions in Inches (mm) Pin Configuration Pin Configuration 1 Bias 3, 2 VSS, 3 Bias 1, 4 VDD /Substrate 5 Open Drain Output, 6 Open Source Output, 7 Bias 2, 8 Input 1 Bias 2, 2 Input, 3 Bias 3, 4 VSS, 5 Bias 1, 6 VDD/Substrate 7 Open Drain Output, 8 Open Source Output www.interfet.com 1000 N. Shiloh Road, Garland, TX 75042 (972) 487-1287 FAX (972) 276-3375