UC1856 UC2856 UC3856 Improved Current Mode PWM Controller FEATURES DESCRIPTION • Pin-for-Pin Compatible With the UC3846 • 65ns Typical Delay From Shutdown to Outputs, and 50ns Typical Delay From Sync to Outputs • Improved Current Sense Amplifier With Reduced Noise Sensitivity The UC3856 is a high performance version of the popular UC3846 series of current mode controllers, and is intended for both design upgrades and new applications where speed and accuracy are important. All input to output delays have been minimized, and the current sense output is slew rate limited to reduce noise sensitivity. Fast 1.5A peak output stages have been added to allow rapid switching of power FETs. • Differential Current Sense with 3V Common Mode Range A low impedance TTL compatible sync output has been implemented with a tri-state function when used as a sync input. • Trimmed Oscillator Discharge Current for Accurate Deadband Control • Accurate 1V Shutdown Threshold Internal chip grounding has been improved to minimize internal “noise” caused when driving large capacitive loads. This, in conjunction with the improved differential current sense amplifier results in enhanced noise immunity. • High Current Dual Totem Pole Outputs (1.5A peak) • TTL Compatible Oscillator SYNC Pin Thresholds • 4kV ESD Protection Other features include a trimmed oscillator current (8%) for accurate frequency and dead time control; a 1V, 5% shutdown threshold; and 4kV minimum ESD protection on all pins. BLOCK DIAGRAM UDG-96176 9/96 UC1856 UC2856 UC3856 ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAMS Supply Voltage ....................................................................+40V Collector Supply Voltage .....................................................+40V Output Current, Source or Sink DC...................................................................................0.5A Pulse (0.5µs)...................................................................2.0A Error Amp Inputs....................................................−0.3V to +VIN Shutdown Input.....................................................−0.3V to +10V Current Sense Inputs..............................................−0.3V to +3V SYNC Output Current ......................................................±10mA Error Amplifier Output Current ...........................................−5mA Soft Start Sink Current.......................................................50mA Oscillator Charging Current .................................................5mA Power Dissipation at TA = 25°C (Note 2).......................1000mW Power Dissipation at TC = 25°C (Note 2) ......................2000mW Junction Temperature .......................................−55°C to +150°C Storage Temperature Range ............................−65°C to +150°C Lead Temperature (Soldering, 10 sec.) ...........................+300°C All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal. Consult packaging section of databook for thermal limitations and considerations of package. DIL–16, SOIC-16 (Top View) J or N, DW PACKAGE PLCC-20 (Top View) Q PACKAGE PLCC-28 (Top View) QP PACKAGE ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = −55°C to +125°C for UC1856; − 40°C to +85°C for the UC2856; and 0°C to +70°C for the UC3856, VIN = 15V, RT = 10k, CT = 1nF, TA = TJ. PARAMETER Reference Section Output Voltage Line Regulation Load Regulation Total Output Variation Output Noise Voltage Long Term Stability Short Circuit Current Oscillator Section Initial Accuracy UC1856/UC2856 MIN TYP MAX MIN TJ = 25°C, Io = 1mA VIN = 8V to 40V Io = −1mA to −10mA Line, Load, and Temperature 10Hz < f < 10kHz, TJ = 25°C TJ = 125°C, 1000 Hrs (Note 2) VREF = 0V 5.05 5.00 TJ = 25°C Over Operating Range 180 170 TEST CONDITIONS 2 5.10 5.00 −25 50 5 −45 200 5.15 20 15 5.20 UC3856 TYP MAX UNITS 5.10 4.95 25 −65 −25 220 230 180 170 50 5 −45 200 5.20 20 15 5.25 25 −65 V mV mV V µV mV mA 220 230 kHz kHz UC1856 UC2856 UC3856 ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise stated, these specifications apply for TA = −55°C to +125°C for UC1856; − 40°C to +85°C for the UC2856; and 0°C to +70°C for the UC3856, VIN = 15V, RT = 10k, CT = 1nF, TA = TJ. PARAMETER Oscillator Section (cont.) Voltage Stability Discharge Current UC1856/UC2856 MIN TYP MAX TEST CONDITIONS Sync Output High Level Sync Output Low Level VIN = 8V to 40V TJ = 25°C, VCT = 2V VCT = 2V Io = −1mA Io = +1mA 7.5 6.7 2.4 Sync Input High Level CT = 0V, RT = VREF 2.0 Sync Input Low Level Sync Input Current CT = 0V, RT = VREF CT = 0V, RT = VREF VSYNC = 5V CT = 0V, RT = VREF VSYNC = 0.8V to 2V Sync Delay to Outputs Error Amplifier Section Input Offset Voltage Input Bias Current Input Offset Current Common Mode Range Open Loop Gain Unity Gain Bandwidth CMRR PSRR Output Sink Current Output Source Current Output High Level Output Low Level VIN = 8V to 40V Vo = 1.2V to 3V TJ = 25°C VCM = 0V to 38V, VIN = 40V VIN = 8V to 40V VID = −15mV, VcOMP = 1.2V VID = 15mV, VCOMP = 2.5V VID = 50mV, RL (COMP) = 15k VID = −50mV, RL (COMP) = 15k 0 80 1 75 80 5 −0.4 4.3 Current Sense Amplifier Section Amplifier Gain VCS− = 0V, CL SS Open (Notes 3,4) Maximum Differential CL SS Open (Note 3) Input Signal (VCS+ − Vcs-) RL (COMP) = 15k Input Offset Voltage VCL SS = 0.5V COMP Open (Note 3) VCM = 0V to 3V VIN = 8V to 40V VCL SS = 0.5V, COMP Open (Note 3) VCL SS = 0.5V, COMP Open (Note 3) CMRR PSRR Input Bias Current Input Offset Current Input Common Mode Range Delay to Outputs 8.0 8.0 3.6 0.2 2 8.8 8.8 7.5 6.7 2.4 0.4 1.5 2.0 UC3856 TYP MAX UNITS 8.0 8.0 3.6 0.2 2 8.8 8.8 0.4 1.5 % mA mA V V V 1.5 1 0.8 10 1.5 1 0.8 10 V µA 50 100 50 100 ns 10 −1 500 VIN − 2 VCM = 2V 5 −1 500 VIN − 2 100 1.5 100 100 10 −0.5 4.6 0.7 4.9 1 2.5 2.75 3.0 1.1 1.2 5 120 −1 1 3 250 0.5 0.57 −10 −30 1.00 1.05 5 0 100 1.5 100 100 10 −0.5 4.6 0.7 4.9 1 mV µA nA V dB MHz dB dB mA mA V V 2.5 2.75 3.0 V/V 1.1 1.2 0 80 1 75 80 5 −0.4 4.3 35 60 60 VEA+ = VREF, EA− = 0V MIN 5 60 60 −3 V 35 mV 120 −3 1 3 250 dB dB µA mA V ns 0.5 0.57 V −10 −30 µA 1.00 1.05 5 V V −1 0 CS+ − CS− = 0V to 1.5V Current Limit Adjust Section Current Limit Offset Input Bias Current Shutdown Terminal Section Threshold Voltage Input Voltage Range VCS- = 0V VCS+ = 0V, COMP = Open (Note 3) VEA+ = VREF, VEA− = 0V 0.43 0.95 0 3 0.43 0.95 0 UC1856 UC2856 UC3856 ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise stated, these specifications apply for TA = −55°C to +125°C for UC1856; − 40°C to +85°C for the UC2856; and 0°C to +70°C for the UC3856, VIN = 15V, RT = 10k, CT = 1nF, TA = TJ. UC1856/UC2856 MIN TYP MAX PARAMETER TEST CONDITIONS Shutdown Terminal Section (cont.) Minimum Latching (Note 5) Current (ICL SS) 3 1.5 MIN 3 UC3856 TYP MAX UNITS 1.5 mA Maximum Non-Latching (Note 6) 1.5 0.8 1.5 0.8 mA Current (ICL SS) Delay to Outputs VSHUTDOWN = 0 to 1.3V 65 110 65 110 ns 250 0.5 2.6 µA V V V V ns ns V Output Section Collector-Emitter Voltage Off-State Bias Current Output Low Level Output High Level 40 VC = 40V IOUT = 20mA IOUT = 200mA IOUT = −20mA IOUT = −200mA C1 = 1nF C1 = 1nF VIN = 0V, IOUT = 20mA 12.5 12 40 0.1 0.5 13.2 13.1 40 40 0.8 250 0.5 2.6 12.5 12 V 0.1 0.5 13.2 13.1 40 40 0.8 Rise Time 80 80 Fall Time 80 80 UVLO Low Saturation 1.5 1.5 PWM Section Maximum Duty Cycle 45 47 50 45 47 50 Minimum Duty Cycle 0 0 Undervoltage Lockout Section Startup Threshold 7.7 8.0 7.7 8.0 Threshold Hysterisis 0.7 0.7 Total Standby Current Supply Current 18 23 18 23 Note 1: All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Note 2: This parameter, although guaranteed over the recommended operating conditions is not 100% tested in production. Note 3: Parameter measured at trip point of latch with VEA+ = VREF, VEA- = 0V. Note 4: Amplifier gain defined as: ∆VCOMP G= ; ∆VCS− = 0V to 1.0V ∆VCS+ Note 5: Current into CL SS guaranteed to latch circuit into shutdown state. Note 6: Current into CL SS guaranteed not to latch circuit into shutdown state. 4 % % V V mA UC1856 UC2856 UC3856 APPLICATIONS INFORMATION Oscillator Circuit 2CT Output deadtime is determined by size of the external capacitor, CT, according to the formula: Td = 3.6 8mA −........ For large values of RT: Td = 250CT RT 2 Oscillator frequency is approximated by the formula: fT = RT CT UDG-96177 Error Amplifier Gain and Phase vs Frequency VIN=20V o TJ =25 80 60 40 20 OPEN-LOOP PHASE OPEN-LOOP VOLTAGE GAIN (dB) Error Amplifier Output Configuration 0o 0 -90o o 100 1k Error Amplifier can source up to 0.5mA. 10k -180 UDG-96179 Error Amplifier Open-Loop D.C. Gain vs Load Resistance OPEN-LOOP VOLTAGE GAIN (dB) 1M FREQUENCY (Hz) UDG-96178 110 VIN=20V o TJ =25 100 90 80 70 0 100k 10 20 30 40 50 60 70 80 90 100 OUTPUT LOAD RESISTANCE RL (k-OHMS) UDG-96180 5 UC1856 UC2856 UC3856 APPLICATIONS INFORMATION (cont.) Parallel Operation Slaving allows parallel operation of two or more units with equal current sharing. UDG-96181 Pulse by Pulse Current Limiting R2 V −0.5 ( R1 + R2 ) REF Peak current (IS) is determined by the formula: IS = 3RS UDG-96182 6 UC1856 UC2856 UC3856 APPLICATIONS DATA (cont.) UDG-96183 UDG-96184 VREF < 0.8mA, the shutdown latch will commutate R1 when ISS = 0.8mA and a restart cycle will be initiated. If VREF < 3mA, the device will latch off until power is R1 recycled. If Current Sense Amplifier Connections A small RC filter may be required in some applications to reduce switch transients. Differential input allows remote, noise sensing. 7 UDG-96185 UC1856 UC2856 UC3856 APPLICATIONS INFORMATION (cont.) UC1856 Open Loop Test Circuit - BYPASS CAPS SHOULD BE LOW ESR & ESL TYPE - SHORT E/A- & COMP FOR UNITY GAIN TESTING THE USE OF A GROUND PLANE IS HIGHLY RECOMMENDED UDG-96186 UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. 603-424-2410 • FAX 603-424-3460 8 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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