SN74CBT16232 SYNCHRONOUS 16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS009J – MAY 1995 – REVISED MAY 1999 D D D DGG OR DL PACKAGE (TOP VIEW) 5-Ω Switch Connection Between Two Ports TTL-Compatible Input and Output Levels Package Options Include Plastic Thin Shrink Small-Outline (DGG) and 300-mil Shrink Small-Outline (DL) Packages 1A 2B1 2B2 3A 4B1 4B2 5A 6B1 6B2 7A 8B1 8B2 GND VCC 9A 10B1 10B2 11A 12B1 12B2 13A 14B1 14B2 15A 16B1 16B2 CLK CLKEN description The SN74CBT16232 is a synchronous 16-bit 1-of-2 FET multiplexer/demultiplexer used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single path. Two select (S0 and S1) inputs control the data flow. A clock (CLK) and a clock enable (CLKEN) synchronize the device operation. When CLKEN is high, the bus switch remains in the last clocked function. The SN74CBT16232 is characterized operation from –40°C to 85°C. for 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1B1 1B2 2A 3B1 3B2 4A 5B1 5B2 6A 7B1 7B2 8A GND VCC 9B1 9B2 10A 11B1 11B2 12A 13B1 13B2 14A 15B1 15B2 16A S0 S1 FUNCTION TABLE INPUTS S1 S0 CLK CLKEN X X X H FUNCTION Last state L L ↑ L Disconnect L H ↑ L A = B1 and A = B2 H L ↑ L A = B1 H H ↑ L A = B2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74CBT16232 SYNCHRONOUS 16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS009J – MAY 1995 – REVISED MAY 1999 logic diagram (positive logic) 56 1 55 1A 1B1 1B2 25 16B1 28 CLKEN 16A 31 26 16B2 27 CLK 30 S0 D CE CLK S1 29 D CE CLK absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) MIN MAX VCC VIH Supply voltage 4 5.5 High-level control input voltage 2 VIL TA Low-level control input voltage Operating free-air temperature –40 UNIT V V 0.8 V 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBT16232 SYNCHRONOUS 16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS009J – MAY 1995 – REVISED MAY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK II VCC = 4.5 V, VCC = 5.5 V, II = –18 mA VI = 5.5 V or GND ICC ∆ICC‡ Control inputs VCC = 5.5 V, VCC = 5.5 V, IO = 0, One input at 3.4 V, Ci Control inputs VI = 3 V or 0 Cio(OFF) i (OFF) A port B port MIN TYP† VI = VCC or GND Other inputs at VCC or GND MAX UNIT –1.2 V ±1 µA 3 µA 2.5 mA 4.5 pF 6.5 VO = 3 V or 0 0, 0 CLKEN = 0, 0 S0 = 0, VCC = 4 V, TYP at VCC = 4 V VI = 2.4 V, II = 15 mA 14 20 VI = 0 II = 64 mA II = 30 mA 5 7 5 7 ron§ VCC = 4.5 V S1 = 0 pF 4 Ω VI = 2.4 V, II = 15 mA 10 15 † All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. ‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. § Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fclock tw VCC = 4 V VCC = 5 V ± 0.5 V MIN MIN Clock frequency 150 Pulse duration tsu Setup time th Hold time MAX 150 CLK high or low 3.3 3.3 S0, S1 before CLK↑ 2.2 1.9 CLKEN before CLK↑ 2.4 1.9 S0, S1 after CLK↑ 0.5 1 CLKEN after CLK↑ 1.9 1.8 UNIT MAX MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tpd¶ tpd ten VCC = 4 V VCC = 5 V ± 0.5 V MIN MIN FROM (INPUT) TO (OUTPUT) A or B B or A 0.35 MAX 150 CLK CLK UNIT MAX 150 MHz 0.25 ns ns A or B 6.1 2 5.8 A, B1, B2 6.8 1.8 6.2 B1 and B2 8.5 3.1 7.9 ns tdis A or B 5.8 1.9 6.2 ns CLK ¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74CBT16232 SYNCHRONOUS 16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS009J – MAY 1995 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V Output Control (low-level enabling) LOAD CIRCUIT 1.5 V 0V tPZL 3V Input 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V VOL 3.5 V Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ 1.5 V tPZH VOH Output Output Waveform 1 S1 at 7 V (see Note B) tPHL 1.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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