TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com 2.5-V to 18-V High-Efficiency Hot-Swap Controller Check for Samples: TPS24700, TPS24701 FEATURES APPLICATIONS • • • • • • • • • • • • • 1 • • • 2.5-V to 18-V Operation Accurate Current Limiting for Starup Accurate 25-mV Current Sense Threshold Timed Overcurrent Breaker Power-Good Output Fast Breaker for Short-Circuit Protection Latch Off (TPS24700) and Retry Versions (TPS24701) Programmable UV Threshold Drop-In Upgrade for LTC4211 – No Layout Changes Small MSOP-8 Package Server Backplanes Storage Area Networks (SAN) Medical Systems Plug-In Modules Base Stations Consumer Electronics DESCRIPTION The TPS24700/1 is an easy-to-use, 2.5 V to 18 V, hot-swap controller that drives an external N-channel MOSFET. The programmable current limit and fault time protect the supply and load from excessive current at startup. After startup, currents above the user-selected limit are allowed to flow until programmed timeout – except in extreme overload events when load is immediately disconnected from source. The low, 25-mV current sense threshold is highly accurate and allows use of smaller, more-efficient sense resistors, yielding lower power loss and smaller footprint. A power-good output is provided for status monitoring and downstream load control. TPS24700/1 replaces the LTC4211 in existing designs with no PCB board changes and only minor external component changes – yielding a more accurate, efficient solution. Text for Spacing TYPICAL APPLICATION OF TPS24700/1 (12 V AT 10 A) RSENSE 2 mΩ VIN M1 CSD16403Q5 COUT 470 μF RGATE 10 Ω 3V VCC SENSE GATE OUT EN R2 18.7 kΩ TPS2470x DGK Package (Top View) VOUT C1 0.1 μF R1 130 kΩ Text for Spacing PINOUT PGb 1 8 VCC EN 2 7 SENSE TIMER 3 6 GATE GND 4 5 OUT R4 3.01 kΩ PGb TIMER GND CT 56 nF VUVLO = 10.8 V ILMT = 12 A tFAULT = 7.56 ms 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEVICE INFORMATION TA PACKAGE –40ºC to 85ºC (1) PART NUMBER (1) FUNCTION MARKING TPS24700 Latched 24700 TPS24701 Retry 24701 MSOP-8 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range, all voltages referred to GND (unless otherwise noted) VALUE Input voltage range EN, GATE, OUT, PGb (1), SENSE, VCC –0.3 to 30 SENSE to VCC –0.3 to 0.3 ESD rating Temperature (1) V –0.3 to 5 TIMER Sink current UNIT PGb 5 All pins except PGb Human-body model mA 2 PGb 0.5 Charged-device model 0.5 Maximum junction, TJ Internally limited kV °C Do not apply voltages directly to these pins. THERMAL INFORMATION THERMAL METRIC (1) TPS24700/01 MSOP (8) PINS UNIT θJA Junction-to-ambient thermal resistance 57.2 °C/W θJCtop Junction-to-case (top) thermal resistance 110.5 °C/W θJB Junction-to-board thermal resistance 60.7 °C/W ψJT Junction-to-top characterization parameter 7.8 °C/W ψJB Junction-to-board characterization parameter 24 °C/W θJCbot Junction-to-case (bottom) thermal resistance 14.3 °C/W (1) 2 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN Input voltage range Sink current External capacitance SENSE, VCC MAX 2.5 18 EN, PGb, OUT 0 18 PGb 0 2 TIMER 1 GATE UNIT V mA nF (1) –40 Operating junction temperature range, TJ (1) NOM 1 µF 125 °C External capacitance tied to GATE should be in series with a resistor no less than 1 kΩ. ELECTRICAL CHARACTERISTICS –40°C ≤ TJ ≤ 125°C, VCC = 12 V, and VEN = 3 V. All voltages referenced to GND, unless otherwise noted. PARAMETER CONDITIONS MIN NOM MAX UNIT UVLO threshold, rising 2.2 2.32 2.45 V UVLO threshold, falling 2.1 2.22 2.35 V 1.4 mA VCC UVLO hysteresis (1) Supply current 0.1 Enabled ― IOUT + IVCC + ISENSE 1 Disabled ― EN = 0 V, IOUT + IVCC + ISENSE V 0.45 mA EN Threshold voltage, falling Hysteresis 1.2 (1) 1.3 1.4 50 V mV Input leakage current 0 V ≤ VEN ≤ 30 V –1 0 1 µA Turnoff time EN ↓ to VGATE < 1 V, CGATE = 33 nF 20 60 150 µs Deglitch time EN ↑ 8 14 18 µs Disable delay EN ↓ to GATE ↓, CGATE = 0, tpff50–90, See Figure 1 0.1 0.4 1 µs V(SENSE–OUT) rising, PGb going high 140 240 340 PGb Threshold Hysteresis (1) Measured V(SENSE–OUT) falling, PGb going low Output low voltage Sinking 2 mA Input leakage current VPGb = 0 V, 30 V Delay (deglitch) time 70 mV 0.11 0.25 V –1 0 1 µA Rising or falling edge 2 3.4 6 ms VTIMER = 0 V 8 10 12 µA VTIMER = 2 V 8 10 12 µA VEN = 0 V, VTIMER = 2 V 2 4.5 7 mA Upper threshold voltage 1.3 1.35 1.4 V Lower threshold voltage 0.33 0.35 0.37 V TIMER Sourcing current Sinking current Timer activation voltage Raise GATE until ITIMER sinking, measure V(GATE–VCC), VCC = 12 V Bleed-down resistance VTIMER = 2 V 5 5.9 7 V 70 104 130 kΩ 16 30 µA 23.5 25.8 28 V OUT Input bias current VOUT = 12 V GATE Output voltage VOUT = 12 V Clamp voltage Inject 10 µA into GATE, measure V(GATE–VCC) 12 13.9 15.5 V Sourcing current VGATE = 12 V 20 30 40 µA (1) These parameters are provided for reference only and do not constitute part of TI’s published device specifications for purposes of TI’s product warranty. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 3 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) –40°C ≤ TJ ≤ 125°C, VCC = 12 V, and VEN = 3 V. All voltages referenced to GND, unless otherwise noted. PARAMETER CONDITIONS MIN Fast turnoff, VGATE = 14 V Sinking current Sustained, VGATE = 4 V to 23 V NOM MAX UNIT 0.5 1 1.4 A 6 11 20 mA In inrush current limit, VGATE = 4 V–23 V 20 30 40 µA Pulldown resistance Thermal shutdown 14 20 26 kΩ Turnon delay VCC rising to GATE sourcing, tprr50-50, See Figure 2 100 250 µs 30 40 µA 22.5 25 27.5 mV 52 60 68 mV 8 13.5 18 µs SENSE Input bias current VSENSE = 12 V, sinking current Current limit threshold VOUT = 12 V Fast-trip threshold Fast-turnoff duration Fast-turnoff delay V(VCC–VSENSE) = 80 mV, CGATE = 0 pF, tprf50–50, See Figure 3 200 ns 140 °C 10 °C OTSD Threshold, rising 130 Hysteresis (1) VGATE IGATE 90% 50% VVCC VEN 50% 50% 0 0 Time Time t(prr50-50) t(pff50-90) T0494-01 T0492-01 Figure 1. tpff50–90 Timing Definition Figure 2. tprr50–50 Timing Definition VGATE 50% VVCC – VSENSE 50% 0 Time t(prf50-50) T0495-01 Figure 3. tprf50–50 Timing Definition 4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM M1 VIN RSENSE SENSE RGATE GATE OUT 6 7 5 60 mV DC + Charge Pump – RSET VCC – Servo Amplifier Fast Comparator Summing Point Inrush Latch + 30 µA + 8 Gate Comparator – VCC 6V 11 mA 1-shot S Q R Q + – 0~60 µA RIMON + 675 mV – Main Opamp in Inrush Limit Becomes Comparator After Inrush Limit Complete 2.32 V 2.22 V EN 2 ms + UVLO + DC – 240 mV 170 mV – 20 kΩ 1 PGb 4 GND PG Comparator + 2 1.35 V 1.3 V – 14 µs 10 µA Fault Logic + 1.5 V POR – TSD 10 µA 3 TIMER CT B0438-03 Figure 4. Block Diagram of the TPS24700/1 PIN FUNCTIONS NAME TPS24700/1 I/O DESCRIPTION EN 2 I Active-high enable input. Logic input. Connects to resistor divider GATE 6 O Gate driver output for external MOSFET GND 4 – Ground OUT 5 I Output voltage sensor for monitoring MOSFET power PGb 1 O Active-low, open-drain power good indicator. Status is determined by the voltage across the MOSFET. SENSE 7 I Current sensing input for resistor shunt from VCC to SENSE TIMER 3 I/O VCC 8 I A capacitor connected from this pin to GND provides a fault timing function. Input-voltage sense and power supply Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 5 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com DETAILED PIN DESCRIPTIONS The following description relies on the typical application diagram shown on the front page of this data sheet, as well as the functional block diagram of Figure 4. EN: Applying a voltage of 1.35 V or more to this pin enables the gate driver. The addition of an external resistor divider allows the EN pin to serve as an undervoltage monitor. Cycling EN low and then back high resets a TPS24700 that has latched off due to a fault condition. This pin should not be left floating. GATE: This pin provides gate drive to the external MOSFET. A charge pump sources 30 µA to enhance the external MOSFET. A 13.9-V clamp between GATE and VCC limits the gate-to-source voltage, because VVCC is very close to VOUT in normal operation. During start-up, a transconductance amplifier regulates the gate voltage of M1 to provide inrush current limiting. The TIMER pin charges timer capacitor CT during the inrush. Inrush current limiting continues until the V(GATE–VCC) exceeds the Timer Activation Voltage (6 V for VVCC = 12 V). Then the TPS24700/1 enters into circuit-breaker mode. The Timer Activation Voltage is defined as a threshold voltage. When V(GATE-VCC) exceeds this threshold voltage, the inrush operation is finished and the TIMER stops sourcing current and begins sinking current. In the circuit-breaker mode, the current flowing in RSENSE is compared with the current-limit threshold derived from Equation 1. If the current flowing in RSENSE exceeds the current limit threshold, then MOSFET M1 is turned off. The GATE pin is disabled by the following three mechanisms: 1. GATE is pulled down by an 11-mA current source when – The fault timer expires during an overload current fault (VSENSE > 25 mV) – VEN is below its falling threshold – VVCC drops below the UVLO threshold 2. GATE is pulled down by a 1-A current source for 13.5 µs when a hard output short circuit occurs and V(VCC–SENSE) is greater than 60 mV, i.e., the fast-trip shutdown threshold. After fast-trip shutdown is complete, an 11-mA sustaining current ensures that the external MOSFET remains off. 3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising threshold. GATE remains low in latch mode (TPS24700) and attempts a restart periodically in retry mode (TPS24701). If used, any capacitor connecting GATE and GND should not exceed 1 μF and it should be connected in series with a resistor of no less than 1 kΩ. No external resistor should be directly connected from GATE to GND or from GATE to OUT. GND: This pin is connected to system ground. OUT: This pin allows the controller to measure the drain-to-source voltage across the external MOSFET M1. The power-good indicator (PGb) relies on this information. The OUT pin should be protected from negative voltage transients by a clamping diode or sufficient capacitors. A Schottky diode of 3 A / 40 V in an SMC package is recommended as a clamping diode for high-power applications. The OUT pin should be bypassed to GND with a low-impedance ceramic capacitor in the range of 10 nF to 1 μF. PGb: This active-low, open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits. PGb pulls low after the drain-to-source voltage of the FET has fallen below 170 mV and a 3.4-ms deglitch delay has elapsed. It goes open-drain when VDS exceeds 240 mV. PGb assumes high-impedance status after a 3.4-ms deglitch delay once VDS of M1 rises up, resulting from GATE being pulled to GND at any of the following conditions: • An overload current fault occurs (VSENSE > 25 mV). • A hard output short circuit occurs, leading to V(VCC–SENSE) greater than 60 mV, i.e., the fast-trip shutdown threshold has been exceeded. • VEN is below its falling threshold. • VVCC drops below the UVLO threshold. • Die temperature exceeds the OTSD threshold. SENSE: This pin connects to the negative terminal of RSENSE. It provides a means of sensing the voltage across this resistor, as well as a way to monitor the drain-to-source voltage across the external FET. The current limit ILIM is set by Equation 1. ILIM = 25 mV RSENSE (1) 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com A fast-trip shutdown occurs when V(VCC–VSENSE) exceeds 60 mV. TIMER: A capacitor CT connected from the TIMER pin to GND determines the overload fault timing. TIMER sources 10 μA when an overload is present, and discharges CT at 10 μA otherwise. M1 is turned off when VTIMER reaches 1.35 V. In an application implementing auto-retry after a fault, this capacitor also determines the period before the external MOSFET is re-enabled. A minimum timing capacitance of 1 nF is recommended to ensure proper operation of the fault timer. The value of CT can be calculated from the desired fault time tFLT, using Equation 2. 10 μA CT = ´ tFLT 1.35 V (2) The latch mode (TPS24700) or the retry mode (TPS24701) occurs if the load current exceeds the current limit threshold or the fast-trip shutdown threshold. While in latch mode, the TIMER pin continues to charge and discharge the attached capacitor periodically. In retry mode, the external MOSFET is disabled for sixteen cycles of TIMER charging and discharging. The TIMER pin is pulled to GND by a 2-mA current source at the end of the 16th cycle of charging and discharging. The external MOSFET is then re-enabled. The TIMER pin capacitor, CT, can also be discharged to GND during latch mode or retry mode by a 2-mA current source whenever any of the following occurs: • VEN is below its falling threshold. • VVCC drops below the UVLO threshold. VCC: This pin performs three functions. First, it provides biasing power to the integrated circuit. Second, it serves as an input to the power-on reset (POR) and undervoltage lockout (UVLO) functions. The VCC trace from the integrated circuit should connect directly to the positive terminal of RSENSE to minimize the voltage sensing error. Bypass capacitor C1, shown in the typical application diagram on the front page, should be connected to the positive terminal of RSENSE. A capacitance of at least 10 nF is recommended. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 7 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS 1200 5 T = 125°C T = 25°C Supply Current (µA) Supply Current (µA) 1000 4 T = 125°C 800 T = –40°C T = 25°C 3 2 T = –40°C 600 1 400 0 4 2 6 8 10 12 14 Input Voltage, VVCC (V) 16 18 0 20 Figure 5. Supply Current vs Input Voltage at Normal Operation (EN = High) 4 2 6 8 10 12 14 Input Voltage, VVCC (V) 16 18 20 Figure 6. Supply Current vs Input Voltage at Shutdown (EN = 0 V) 40 26.5 26 VVCC = 2.5 V 25.5 25 24.5 Gate Current at Current Limiting VVCC Voltage = 12 V 32 VVCC = 12 V MOSFET Gate Current (µA) Voltage, V(VCC – SENSE) (V) 0 VVCC = 18 V 24 24 16 T = 25°C 8 0 T = 125°C –8 –16 T = –40°C –24 –32 –40 –20 10 40 70 Temperature (°C) 100 0 130 Figure 7. Voltage Across RSENSE in Inrush Current Limiting vs Temperature T = 25°C 0.15 0.1 1.2 0.05 1 0.8 0 V(VCC – SENSE) T = 125°C 0.6 –0.05 0.4 –0.1 0.2 –0.15 0.05 0.3 T = 125°C –0.05 0.1 –0.1 0 –0.2 –10 –0.15 –0.2 VVCC = 3.3 V 0 Time (µs) 10 20 30 40 –0.25 Time (µs) Figure 9. Gate Current During Fast Trip, VVCC = VGATE = 12 V 8 0 V(VCC – SENSE) 0.2 –0.25 40 0.1 0.4 –0.2 –10 30 0.15 T = 25°C 0.5 –0.1 20 55 0.2 T = –40°C –0.2 10 50 0.7 0 0 45 0.25 0.6 Gate Current (A) Gate Current (A) 0.2 T = –40°C 1.4 15 20 25 30 35 40 Voltage, V(VCC – SENSE) (mV) 0.9 Voltage, V(VCC – SENSE) (V) 1.6 VVCC = 12 V 10 Figure 8. Gate Current vs Voltage Across RSENSE During Inrush Current Limiting 0.25 1.8 5 Voltage, V(VCC – SENSE) (V) 23.5 –50 Figure 10. Gate Current During Fast Trip, VVCC = VGATE = 3.3 V Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com 7 32 TIMER Activation Voltage Threshold (V) Gate Voltage Referenced to GND, VGATE (V) TYPICAL CHARACTERISTICS (continued) T = 25°C 28 T = 125°C 24 20 T = –40°C 16 12 8 4 0 8 12 Input Voltage, VVCC (V) 16 T = 125°C 6 T = –40°C 5 4 3 20 Figure 11. Gate Voltage With Zero Gate Current vs VVCC 8 12 Input Voltage, VVCC (V) 16 20 2.36 VVCC = 12 V VVCC = 12 V EN Upper Threshold 1.6 UVLO Threshold Voltage (V) EN Threshold Voltage (V) 4 0 Figure 12. TIMER Activation Voltage Threshold vs VVCC at Various Temperatures 2 1.2 0.8 0.4 0 –50 –20 –10 10 30 50 70 Temperature (°C) 90 110 2.28 UVLO Lower Threshold 2.24 –20 10 40 70 Temperature (°C) 100 130 Figure 14. UVLO Threshold Voltages vs Temperature 240 64 Fast-Trip Threshold Voltage (mV) PGb Rising 220 200 180 PGb Falling 160 140 –50 UVLO Upper Threshold 2.32 2.20 –50 130 Figure 13. EN Threshold Voltage vs Temperature V(SENSE – OUT) Threshold Voltage (mV) T = 25°C –20 10 40 70 Temperature (°C) 100 130 Figure 15. Threshold of VDS vs Temperature, PGb Rising and Falling 63.5 VVCC = 12 V 63 VVCC = 2.5 V 62.5 62 61.5 61 VVCC = 18 V 60.5 60 –50 –20 10 40 70 Temperature (°C) 100 130 Figure 16. Fast-Trip Threshold vs Temperature Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 9 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com 160 0.7 VEN = 0 V 140 120 VVCC = 18 V VVCC = 2.5 V 100 80 60 –50 –20 10 40 70 Temperature (°C) 100 0.2 130 T = –40°C 4 0 8 12 Input Voltage, VVCC (V) 16 20 Figure 18. Supply Current vs VVCC and Temperature When EN Pulled Low 0.365 Timer Lower Threshold Voltage (V) Timer Upper Threshold Voltage (V) 0.4 0.3 1.344 1.342 VVCC = 18 V VVCC = 12 V 1.34 1.338 VVCC = 2.5 V 1.336 1.334 –50 –20 10 40 70 Temperature (°C) 100 VVCC = 18 V 0.362 VVCC = 12 V 0.36 VVCC = 2.5 V 0.357 –50 130 Figure 19. Timer Upper Threshold vs VVCC and Temperature –20 10 40 70 Temperature (°C) 100 130 Figure 20. Timer Lower Threshold vs VVCC and Temperature 10.2 10.4 10.1 10.3 VVCC = 18 V 10 Timer Sinking Current (µA) Timer Sourcing Current (µA) T = 25°C 0.5 VVCC = 12 V Figure 17. PGb Open-Drain Output Voltage in Low State VVCC = 12 V 9.9 9.8 9.7 VVCC = 2.5 V 9.6 VVCC = 18 V VVCC = 12 V 10.2 10.1 10 VVCC = 2.5 V 9.9 9.8 9.5 –50 –20 10 40 70 Temperature (°C) 100 130 Figure 21. Timer Sourcing Current vs VVCC and Temperature 10 T = 125°C 0.6 Supply Current (µA) Low-State Open-Drain Output Voltage (mV) TYPICAL CHARACTERISTICS (continued) 9.7 –50 –20 10 40 70 Temperature (°C) 100 130 Figure 22. Timer Sinking Current vs VVCC and Temperature Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com SYSTEM OPERATION INTRODUCTION The TPS24700/1 provides all the features needed for a positive hot-swap controller. These features include: • Undervoltage lockout • Adjustable (system-level) enable • Turn-on inrush limiting • High-side gate drive for an external N-channel MOSFET • Adjustable overload timeout — also called an electronic circuit breaker • Charge-complete indicator for downstream converter coordination • A choice of latch (TPS24700) or automatic restart mode (TPS24701) The typical application circuit, shown on the front page of this datasheet, and oscilloscope plots, shown in Figure 23 through Figure 24 and Figure 26 through Figure 28, demonstrate many of the functions described previously. BOARD PLUG IN Figure 23 illustrates the inrush current that flows when a hot-swap board under the control of the TPS24700/1 is plugged into an input power bus. Only the bypass capacitor charge current and small bias currents are evident when a board is first plugged in. The TPS24700/1 is held inactive for a short period while internal voltages stabilize. In this short period, GATE and TIMER are held low and PGb is held open-drain. When the voltage on the internal VCC rail exceeds approximately 1.5 V, the power-on reset (POR) circuit initializes the TPS24700/1 and a start-up cycle is ready to take place. GATE, TIMER, and PGb are released after the internal voltages have stabilized and the external EN (enable) threshold has been exceeded. The part begins sourcing current from the GATE pin to turn on MOSFET M1. The TPS24700/1 monitors the drain current passing through MOSFET M1 by measuring the voltage V(VCC - SENSE). Based on the measurement, the TPS24700/1 limits the drain current in the MOSFET to be no more than the current limit ILIM, so as to alleviate the charging impact of the downstream bulk storage capacitors. Figure 23. Inrush Mode at Hot-Swap Circuit Insertion Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 11 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com INRUSH OPERATION When the TPS2470/1 activates MOSFET M1, a current flows into the downstream bulk storage capacitors. When this current exceeds the limit threshold set by Equation 1, the gate of the MOSFET is regulated by a feedback loop to make the MOSFET current stay at a current level no more than the current limit threshold. This limits the inrush current charging capacitance. The TIMER pin begins to charge the timing capacitor CT with a current of approximately 10 μA. The TIMER pin continues to charge CT until V(GATE–VCC) reaches the timer activation voltage (6 V for VVCC = 12 V). The TIMER then begins to discharge CT with a current of approximately 10 μA. This indicates that the inrush mode is finished. If the TIMER exceeds its upper threshold of 1.35 V before V(GATE–VCC) reaches the timer activation voltage, the GATE pin is pulled to GND and the hot-swap circuit enters either latch mode (TPS24700) or auto-retry mode (TPS24701). The current limit feature is disabled once the inrush operation is finished and the hot-swap circuit becomes a circuit breaker. The TPS24700/1 turns off the MOSFET, M1, after a fault timer period once the load exceeds the current limit threshold. CIRCUIT BREAKER AND FAST TRIP The TPS24700/1 monitors load current by sensing the voltage across RSENSE. The TPS24700/1 incorporates two distinct thresholds: a current-limit threshold and a fast-trip threshold. Figure 24 shows the behavior of the TPS24700/1 when a fault in the output load causes the current passing through RSENSE to increase to a value above the current limit but less than the fast-trip threshold. When the current exceeds the current-limit threshold, a current of approximately 10 μA begins to charge timing capacitor CT. If the voltage on CT reaches 1.35 V, then the external MOSFET is turned off. The TPS24700 latches off and the TPS24701 commences a restart cycle. Overload between the current limit and the fast-trip threshold is permitted for this period. This shutdown scheme is sometimes called an electronic circuit breaker. The fast-trip threshold protects the system against a severe overload or a dead short circuit. When the voltage across the sense resistor RSENSE exceeds the 60-mV fast-trip threshold, the GATE pin immediately pulls the external MOSFET gate to ground with approximately 1 A of current. This extremely rapid shutdown may generate disruptive transients in the system, in which case a low-value resistor inserted between the GATE pin and the MOSFET gate can be used to moderate the turnoff current. The fast-trip circuit holds the MOSFET off for only a few microseconds, after which the TPS24700/1 turns back on slowly, allowing the current-limit feedback loop to take over the gate control of M1. Then the hot-swap circuit goes into either latch mode (TPS24700) or auto-retry mode (TPS24701). Figure 26 and Figure 27 illustrate the behavior of the system when the current exceeds the fast-trip threshold. The functions of circuit breaker and fast-trip turnoff are shown in Figure 24 through Figure 27. 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com Figure 24. Circuit-Breaker Mode During Overload Condition M1 ILIMIT RSENSE RGATE VCC 8 RSET SENSE GATE 7 6 + 60 mV + A1 – – Server Amplifier Fast Trip Comparator 60 μA + 675 mV 30 μA VCP A2 – Current Limit Amp RIMON B0439-03 Figure 25. Partial Diagram of the TPS24700/1 With Selected External Components Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 13 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com Figure 26. Current Limit During Output Load Short-Circuit Condition (Overview) Figure 27. Current Limit During Output-Load Short-Circuit Condition (Onset) AUTOMATIC RESTART The TPS24701 automatically initiates a restart after a fault has caused it to turn off the external MOSFET M1. 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com Internal control circuits use CT to count 16 cycles before re-enabling M1 as shown in Figure 28. This sequence repeats if the fault persists. The timer has a 1 : 1 charge-to-discharge current ratio. For the very first cycle, the TIMER pin starts from 0 V and rises to the upper threshold of 1.35 V and subsequently falls to 0.35 V before restarting. For the following 16 cycles, 0.35 V is used as the lower threshold. This small duty cycle often reduces the average short-circuit power dissipation to levels associated with normal operation and eliminates special thermal considerations for surviving a prolonged output short. Figure 28. Auto-Restart Cycle Timing Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 15 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com Figure 29. Latch After Overload Fault PGb AND TIMER OPERATIONS The open-drain PGb output provides a deglitched end-of-inrush indication based on the voltage across M1. PGb is useful for preventing a downstream dc/dc converter from starting while its input capacitor COUT is still charging. PGb goes active-low about 3.4 ms after COUT is charged. This delay allows M1 to fully turn on and any transients in the power circuits to end before the converter starts up. This type of sequencing prevents the downstream converter from demanding full current before the current-limit engine allows the MOSFET to conduct the full current set by the current limit ILIM. Failure to observe this precaution may prevent the system from starting. The pullup resistor shown on the PGb pin in the typical application diagram (front page) is illustrative only; the actual connection to the converter depends on the application. The PGb pin may indicate that inrush has ended before the MOSFET is fully enhanced, but the downstream capacitor will have been charged to substantially its full operating voltage. Care should be taken to ensure that the MOSFET on-resistance is sufficiently small to ensure that the voltage drop across this transistor is less than the minimum power-good threshold of 140 mV. After the hot-swap circuit successfully starts up, the PGb pin can return to a high-impedance status whenever the drain-to-source voltage of MOSFET M1 exceeds its upper threshold of 340 mV, which presents the downstream converters a warning flag. This flag may occur as a result of overload fault, output short fault, high die temperature, or the GATE shutdown by UVLO and EN. The fault-timer defines an allowed period during which the load current can exceed the programmed current limit (but not the fast-trip threshold). The fault timer starts when a current of approximately 10 μA begins to flow into the external capacitor, CT, and ends when the voltage of CT reaches TIMER upper threshold, i.e., 1.35 V. The fault-timer state requires an external capacitor CT connected between the TIMER pin and GND pin. The length of the fault timer is the charging time of CT from 0 V to its upper threshold of 1.35 V. The fault timer begins to count under any of the following three conditions: • In the inrush mode, TIMER begins to source current to the timer capacitor, CT, when MOSFET M1 is enabled. TIMER begins to sink current from the timer capacitor, CT when V(GATE–VCC) exceeds the timer activation voltage (see the Inrush Operation section). If V(GATE–VCC) does not reach the timer activation voltage before TIMER reaches 1.35 V, then the TPS24700/1 disables the external MOSFET M1. After the MOSFET turns off, the timer goes into either latch mode (TPS24700) or retry mode (TPS24701). 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com • • In an overload fault, TIMER begins to source current to the timer capacitor, CT, when the load current exceeds the programmed current limits. When the timer capacitor voltage reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode (TPS24700) or retry mode (TPS24701). In output short-circuit fault, TIMER begins to source current to the timer capacitor, CT, when the load current exceeds the current-limit threshold following a fast-trip shutdown of M1. When the timer capacitor voltage reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode (TPS24700) or retry mode (TPS24701). If the fault current drops below the current limit falling threshold within the fault timer period, VTIMER decreases and the pass MOSFET, M1, remains enabled. The behaviors of TIMER are different in the latch mode (TPS24700) and retry mode (TPS24701). If the timer capacitor reaches the upper threshold of 1.35 V, then: • In latch mode, the TIMER pin continues to charge and discharge the attached capacitor periodically until TPS24700 is disabled by UVLO or EN as shown in Figure 29. • In retry mode, TIMER charges and discharges CT between the lower threshold of 0.35 V and the upper threshold of 1.35 V for sixteen cycles before the TPS24701 attempts to restart. The TIMER pin is pulled to GND at the end of the 16th cycle of charging and discharging and then ramps from 0 V to 1.35 V for the initial half-cycle in which the GATE pin sources current. This periodic pattern is stopped once the overload fault is removed or the TPS24701 is disabled by UVLO or EN. OVERTEMPERATURE SHUTDOWN The TPS24700/1 includes a built-in overtemperature shutdown circuit designed to disable the gate driver if the die temperature exceeds approximately 140°C. An overtemperature condition also causes the PGb pin to go to the high-impedance state. Normal operation resumes once the die temperature has fallen approximately 10°C. START-UP OF HOT-SWAP CIRCUIT BY VCC OR EN The connection and disconnection between a load and the input power bus are controlled by turning on and turning off the MOSFET, M1. The TPS24700/1 has two ways to turn on MOSFET M1: • Increasing VVCC above the UVLO upper threshold while EN is already higher than its upper threshold sources current to the GATE pin. After an inrush period, the TPS24700/1 fully turns on MOSFET M1. • Increasing EN above its upper threshold while VVCC is already higher than the UVLO upper threshold sources current to the GATE pin. After an inrush period, TPS24700/1 fully turns on MOSFET M1. The EN pin can be used to start up the TPS24700/1 at a selected input voltage VVCC. To isolate the load from the input power bus, the GATE pin sinks current and pulls the gate of MOSFET M1 low. The MOSFET can be disabled by any of the following conditions: UVLO, EN, load current above current limit threshold, hard short at load, or OTSD. Three separate mechanisms pull down the GATE pin: 1. GATE is pulled down by an 11-mA current source when any of the following occurs. – The fault timer expires during an overload current fault (VSENSE > 25 mV). – VEN is below its falling threshold. – VVCC drops below the UVLO falling threshold. 2. GATE is pulled down by a 1-A current source for 13.5 μs when a hard output short circuit occurs and V(VCC–SENSE) is greater than 60 mV, i.e., the fast-trip shutdown threshold. After fast-trip shutdown is complete, an 11-mA sustaining current ensures that the external MOSFET remains off. 3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising threshold. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 17 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com DESIGN EXAMPLE: CURRENT-LIMITED START-UP This design example assumes a 12-V system voltage with an operating tolerance of ±2 V. The rated load current is 10 A, corresponding to a dc load of 1.2 Ω. If the current exceeds 12 A, then the controller should shut down and then attempt to restart. Ambient temperatures may range from 20°C to 50°C. The load has a minimum input capacitance of 470 μF. Figure 30 shows a simplified system block diagram of the proposed application. This design procedure seeks to control the junction temperature of MOSFET M1 under both static and transient conditions by proper selection of package, cooling, rDS(on), current limit, fault timeout, and power limit. The design procedure further assumes that a unit running at full load and maximum ambient temperature experiences a brief input power interruption sufficient to discharge COUT, but short enough to keep M1 from cooling. A full COUT recharge then takes place. Adjust this procedure to fit your application and design criteria. PROTECTION RSENSE LOAD M1 0.1 μF 0.1 μF RGATE OUT GATE COUT 470 μF TPS2470x GND Specifications (at Output): Peak Current Limit = 12 A Nominal Current = 10 A SENSE VCC 12-V Main Bus Supply RLOAD 1.2 W TIMER CT B0440-03 Figure 30. Simplified Block Diagram of the System Constructed in the Design Example STEP 1. Choose RSENSE From the TPS24700/1 electrical specifications, the typical current-limit threshold voltage, V(VCC–SENSE), is 25 mV. A resistance of 2 mΩ is selected for the peak current limit of 12 A, while dissipating only 200 mW at the rated 10-A current (see Equation 3). This represents a 0.17% power loss. V(VCC - SENSE ) RSENSE = , ILIM therefore, RSENSE = 25 mV » 2 mW 12 A (3) STEP 2. Choose MOSFET M1 The next design step is to select M1. The TPS24700/1 is designed to use an N-channel MOSFET with a gate-to-source voltage rating of 20 V. Devices with lower gate-to-source voltage ratings can be used if a Zener diode is connected to limit the maximum gate-to-source voltage across the transistor. The next factor to consider is the drain-to-source voltage rating, VDS(MAX), of the MOSFET. Although the MOSFET only sees 12 V dc, it may experience much higher transient voltages during extreme conditions, such as the abrupt shutoff that occurs during a fast trip. A TVS may be required to limit inductive transients under such conditions. A transistor with a VDS(MAX) rating of at least twice nominal input power supply voltage is recommended regardless of whether a TVS is used or not. 18 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com Next select the on resistance of the transistor, rDS(on). The maximum on-resistance must not generate a voltage greater then the minimum power-good threshold voltage of 140 mV. Assuming a current limit of 12 A, a maximum rDS(on) of 11.67 mΩ is required. Also consider the effect of rDS(on) upon the maximum operating temperature TJ(MAX) of the MOSFET. Equation 4 computes the value of rDS(on)(MAX) at a junction temperature of TJ(MAX). Most manufacturers list rDS(on)(MAX) at 25°C and provide a derating curve from which values at other temperatures can be derived. Compute the maximum allowable on-resistance, rDS(on)(MAX), using Equation 4. TJ(MAX) - TA(MAX) rDS(on)(MAX) = , IMAX2 ´ RqJA therefore, rDS(on)(MAX) = 150°C - 50°C (12 A )2 ´ 51°C / W = 13.6 mW (4) Taking these factors into consideration, the TI CSD16403Q5 was selected for this example. This transistor has a VGS(MAX) rating of 16 V, a VDS(MAX) rating of 25 V, and a maximum rDS(on) of 2.8 mΩ at room temperature. During normal circuit operation, the MOSFET can have up to 10 A flowing through it. The power dissipation of the MOSFET equates to 0.24 W and a 9.6°C rise in junction temperature. This is well within the data sheet limits for the MOSFET. The power dissipated during a fault (e.g., output short) is far larger than the steady-state power. The power handling capability of the MOSFET must be checked during fault conditions. STEP 3. Choose Output Voltage Rising Time, tON, CT The maximum output voltage rise time, tON, set by the timer capacitor CT must suffice to fully charge the load capacitance COUT without triggering the fault circuitry. Equation 5 defines tON, where VCC(MAX) is the maximum input power bus voltage value and ILIM is the current limit value. COUT ´ VVCC(MAX) t ON = if PLIM > ILIM ´ VVCC(MAX) ILIM therefore, t ON = 470 μF ´ 12 V = 0.47 ms 12 A (5) The next step is to determine the minimum fault-timer period. In Equation 5, the output rise time, tON, is the amount of time it takes to charge the output capacitor up to the final output voltage. However, the fault timer uses the difference between the input voltage and the gate voltage to determine if the TPS24700/1 is still in inrush limit. The fault timer continues to run until VGATE rises 6 V above the input voltage (for VVCC = 12 V). Some additional time must be added to the total time to account for this additional gate voltage rising. The minimum fault time can be calculated using Equation 6, 6 V ´ CISS tFLT = t ON + , IGATE therefore, tFLT = 0.47 ms + 6 V ´ 2040 pF = 1.08 ms 20 μA (6) where CISS is the MOSFET input capacitance and IGATE is the minimum gate sourcing current of TPS24700, or 20 μA. Using the example parameters in Equation 6 and the CSD16403Q5 data sheet leads to a minimum fault time of 1.08 ms. This time is derived considering the tolerances of COUT, CISS, ILIM, IGATE, COUT, and VVCC. The fault timer must be set to a value higher than 1.08 ms to avoid turning off during start-up, but lower than any maximum fault time limit determined by the device SOA curve. There is a maximum time limit set by the SOA curve of the MOSFET. Referring to Figure 31, which shows the Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 19 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com CSD16403Q5 SOA curve at TJ = 25°C, the MOSFET can tolerate 12 A with 12 V across it for approximately 20 ms. If the junction temperature TJ is other than 25°C, then the pulse time should be scaled by a factor of (150°C – TJ) / (150°C – 25°C). Therefore, the fault timer should be set between 1.08 ms and 20 ms. For this example, we will select 7 ms to allow for variation of system parameters such as temperature, load, component tolerance, and input voltage. The timing capacitor is calculated in Equation 2 as 52 nF. Selecting the next-highest standard value, 56 nF, yields a 7.56-ms fault time (see Equation 7). 10 μA CT = ´ tFLT , 1.35 V therefore, CT = 10 μA ´ 7 ms = 52 nF 1.35 V (7) IDS – Drain-to-Source Current – A 1k 100 1ms 10 10ms 100ms Area Limited by RDS(on) 1 1s 0.1 Single Pulse RθJA = 94ºC/W (min Cu) 0.01 0.01 0.1 DC 1 10 100 VDS – Drain-to-Source Voltage – V G009 Figure 31. CSD16403Q5 SOA Curve STEP 4. Calculate the Retry-Mode Duty Ratio In retry mode, the TPS24701 is on for one charging cycle and off for 16 charge/discharge cycles, as can be seen in Figure 28. The first CT charging cycle is from 0 V to 1.35 V, which gives 7.56 ms. The first CT discharging cycle is from 1.35 V to 0.35 V, which gives 5.6 ms. Therefore, the total time is 7.56 ms + 33 × 5.6 ms = 192.36 ms. As a result, the retry mode duty ratio is 7.56 ms/192.36 ms = 3.93%. STEP 5. Select R1 and R2 for UV Next, select the values of the UV resistors, R1 and R2, as shown in the application diagram on the front page. From the TPS24700/1 electrical specifications, VENTHRESH = 1.35 V. The VUV is the undervoltage trip voltage, which for this example equals 10.8 V. R2 VENTHRESH = ´ VVCC R1 + R2 (8) Assume R1 is 130 kΩ and use Equation 8 to solve for the R2 value of 18.7 kΩ. STEP 6. Choose RGATE, R4 and C1 In the application diagram on the front page, the gate resistor, RGATE, is intended to suppress high-frequency oscillations. A resistor of 10 Ω serves for most applications, but if M1 has a CISS below 200 pF, then 33 Ω is recommended. Applications with larger MOSFETs and very short wiring may not require RGATE. R4 is required only if PGb is used; this resistor serves as a pullup for the open-drain output driver. The current sunk by PGb pin should not exceed 2 mA. C1 is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise while in the disabled state. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended. ALTERNATIVE DESIGN EXAMPLE: GATE CAPACITOR (dV/dt) CONTROL IN INRUSH MODE 20 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com The TPS24700/1 can be used in applications that expect a constant inrush current. This current is controlled by a capacitor connected from the GATE terminal to GND. A resistor of 1 kΩ placed in series with this capacitor prevents it from slowing a fast-turnoff event. In this mode of operation, M1 operates as a source follower, and the slew rate of the output voltage approximately equals the slew rate of the gate voltage (see Figure 32). To implement a constant-inrush-current circuit, choose the time to charge, ∆t, using Equation 9, C ´ VVCC Dt = OUT ICHG (9) where COUT is the output capacitance, VVCC is the input voltage, and ICHG is the desired COUT charge current. To select the gate capacitance use Equation 10. æ Dt ö CGATE = ç IGATE ´ ÷ - CISS VVCC ø è (10) M1 To Load From Source RGATE Part of TPS2470x CGATE GATE IGATE 30 μA 1 kΩ GND S0509-03 Figure 32. Gate Capacitor (dV/dt) Control Inrush Mode ADDITIONAL DESIGN CONSIDERATIONS Use of PGb Use the PGb pin to control and coordinate a downstream dc/dc converter. If this is not done, then a long time delay is needed to allow COUT to fully charge before the converter starts. An undesirable latch-up condition can be created between the TPS24700/1 output characteristic and the dc/dc converter input characteristic if the converter starts while COUT is still charging; the PGb pin is one way to avoid this. Output Clamp Diode Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during a current-limit event. The OUT pin ratings can be satisfied by connecting a diode from OUT to GND. The diode should be selected to control the negative voltage at the full short-circuit current. Schottky diodes are generally recommended for this application. Gate Clamp Diode The TPS24700/1 has a relatively well-regulated gate voltage of 12 V to 15.5 V with a supply voltage VVCC higher than 4 V. A small clamp Zener from gate to source of M1 is recommended. A series resistance of several hundred ohms or a series silicon diode is recommended to prevent the output capacitance from discharging through the gate driver to ground. High-Gate-Capacitance Applications Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 21 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com Gate voltage overstress and abnormally large fault current spikes can be caused by large gate capacitance. An external gate clamp Zener diode is recommended to assist the internal Zener if the total gate capacitance of M1 exceeds about 4000 pF. When gate capacitor dV/dt control is used, a 1-kΩ resistor in series with CG is recommended. If the series R-C combination is used for MOSFETs with CISS less than 3000 pF, then a Zener is not necessary. Bypass Capacitors It is a good practice to provide low-impedance ceramic capacitor bypassing of the VCC and OUT pins. Values in the range of 10 nF to 1 μF are recommended. Some system topologies are insensitive to the values of these capacitors; however, some are not and require minimization of the value of the bypass capacitor. Input capacitance on a plug-in board may cause a large inrush current as the capacitor charges through the low-impedance power bus when inserted. This stresses the connector contacts and causes a brief voltage sag on the input bus. Small amounts of capacitance (e.g., 10 nF to 0.1 μF) are often tolerable in these systems. Output Short-Circuit Measurements Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads, circuit layout and component selection, output shorting method, relative location of the short, and instrumentation all contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do not expect to see waveforms exactly like those in the data sheet; every setup differs. Layout Considerations TPS24700/1 applications require careful attention to layout to ensure proper performance and to minimize susceptibility to transients and noise. In general, all traces should be as short as possible, but the following list deserves first consideration: • Decoupling capacitors on VCC pin should have minimal trace lengths to the pin and to GND. • Traces to VCC and SENSE must be short and run side-by-side to maximize common-mode rejection. Kelvin connections should be used at the points of contact with RSENSE. (see Figure 33). • Power path connections should be as short as possible and sized to carry at least twice the full load current, more if possible. • The device dissipates low power, so soldering the thermal pad to the board is not a requirement. However, doing so improves thermal performance and reduces susceptibility to noise. • Protection devices such as snubbers, TVS, capacitors, or diodes should be placed physically close to the device they are intended to protect, and routed with short traces to reduce inductance. For example, the protection Schottky diode shown in the application diagram on the front page of the data sheet should be physically close to the OUT pin. 22 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com LOAD CURRENT PATH LOAD CURRENT PATH SENSE VCC SENSE VCC RSENSE TPS2470x TPS2470x Method 1 Method 2 M0217-03 Figure 33. Recommended RSENSE Layout Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 23 TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com REVISION HISTORY Changes from Revision Original (April 2011) to Revision A • Revised voltage values shown in the block diagram ............................................................................................................ 5 Changes from Revision A (April 2011) to Revision B • 24 Page Page Changed in DETAILED PIN DESCRIPTIONS - PGb: from 140mV / 340mV to 170mV / 240 mV ...................................... 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24700 TPS24701 PACKAGE OPTION ADDENDUM www.ti.com 14-May-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TPS24700DGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS24700DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS24701DGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS24701DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS24700DGKR MSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS24701DGKR MSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS24700DGKR MSOP DGK 8 2500 358.0 335.0 35.0 TPS24701DGKR MSOP DGK 8 2500 358.0 335.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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