TPS2492 TPS2493 www.ti.com SLUSA65A – JULY 2010 – REVISED AUGUST 2010 Positive High-Voltage Power-Limiting Hotswap Controller With Analog Current Monitor Output Check for Samples: TPS2492 , TPS2493 FEATURES 1 • • • • • • • • • • • DESCRIPTION 9-V to 80-V Operation High-Side Drive for External N-FET Programmable FET Power Limit Programmable Load Current Limit Programmable Fault Timer Load Current Monitor Output Power Good and Fault Outputs Enable/UV, OV Inputs Latch or Auto Restart After Fault EVM Available SLUU425 Calculation Tool Available SLVC033 The TPS2492 and TPS2493 are easy-to-use, positive high voltage, 14-pin Hotswap Controllers that safely drive an external N-channel FET to control load current. The programmable power foldback protection ensures that the external FET operates inside its safe operating area (SOA) during overload conditions by controlling of power dissipation. The programmable current limit and fault timer ensure the supply, external FET, and load are not harmed by overcurrent. Features include inrush current limiting, controlled load turn-on, interfacing to down-stream DC-to-DC converters, and power feed protection. The analog current monitor output provides a signal ready for sampling with an external A/D converter. APPLICATIONS • • • • • Additional features include programmable overvoltage and undervoltage shutdown, power-good for coordinating loads with inrush, and a fault indicator to indicate an over-current shutdown. Server Backplanes Storage Area Networks (SAN) Medical Systems Plug-in Modules Base Stations Typical Application Circuit RSENSE 0.01 W DRAIN-TO-SOURCE CURRENT vs DRAIN-TO-SOURCE VOLTAGE M1 VIN VOUT co RGATE 10 W 13 VCC SENSE 12 11 Operation in the gray area is limited by RDS(on) 470 kW GATE OUT FLT 9 1 PG 8 IMON GND TIMER 6 TPS2492/93 UVEN OV PROG VREF 5 3 2 R4 41.2 kW R3 7 4 CT 0.068 mF R5 8.25 kW PLIM = 34 W ILIM = 5 A Timeout = 10 ms ID - Drain-to-Source Current - A 14 C1 R2 1000 470 kW R1 D1 VLOGIC 100 100 ms 10 1 ms 1 10 ms Programmed SOA 10 ms 0.1 1 10 100 VDS - Drain-to-Source Voltage - V 1000 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS2492 TPS2493 SLUSA65A – JULY 2010 – REVISED AUGUST 2010 www.ti.com PRODUCT INFORMATION (1) TEMPERATURE FUNCTION Latched -40°C to 85°C (1) Retry PACKAGE PART NUMBER TPS2492PW PW14 TPS2493PW For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over recommended TJ and voltages with respect to GND (unless otherwise noted) VALUE VCC, SENSE, UVEN, OUT PROG, OV VCC – SENSE TIMER, VREF, IMON PG, FLT -0.3 to 6 -1.5 to 1.5 VREF Output voltage range -0.3 to 6 10 2 Source current HBM mA 2 2 ESD rating CDM V -0.3 to 100 Sink current PROG (1) Input voltage range Differential voltage GATE, PG, FLT UNIT -0.3 to 100 kV 0.5 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. THERMAL INFORMATION THERMAL METRIC (1) VALUE (2) qJA Junction-to-ambient thermal resistance qJB Junction-to-board thermal resistance (3) 53.8 yJT Junction-to-top characterization parameter (4) 1.4 yJB Junction-to-board characterization parameter (5) 58.8 (1) (2) (3) (4) (5) UNITS 116.4 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7). RECOMMENDED OPERATING CONDITIONS over recommended TJ and voltages with respect to GND (unless otherwise noted) MIN VCC PROG VREF Input voltage range MAX UNIT 80 0.4 4 V Sourcing current 0 1 mA capacitive loading 0 1000 pF 1.9 mA -40 125 °C IMON Sourcing current TJ Junction operating temperature 2 NOM 9 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 TPS2492 TPS2493 www.ti.com SLUSA65A – JULY 2010 – REVISED AUGUST 2010 ELECTRICAL CHARACTERISTICS 9 V ≤ VVCC ≤ 80 V, -40°C ≤ TJ ≤ 125°C, VTIMER = 0 V and all outputs unloaded. Typical specification are at TJ = 25°C, VVCC = 48 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply Current (VCC) IVCC Enabled VUVEN = Hi, VSENSE = VOUT = VVCC 665 1000 IVCC Disabled VUVEN = Lo, VSENSE = VVCC, VOUT = 0 120 250 µA Input Supply UVLO (VCC) VVCC turn on Rising Hysteresis 50 8.4 8.8 V 100 150 mV 7.5 20 µA 4 4.1 V 5 µA 375 600 Ω Current Sense Input (SENSE) ISENSE Input bias current VSENSE = VOUT = VVCC Reference Voltage Output (VREF) VREF Reference voltage 0 ≤ IVREF ≤ 1 mA 3.9 Power Limiting Input (PROG) IPROG Input bias current; device enabled; sourcing or sinking 0.4 ≤ VPROG ≤ 4 V VUVEN = 48 V RPROG Pull down resistance; device disabled IPROG = 200 µA; VUVEN = 0 V Power Limiting and Current Limiting (SENSE) Current limit threshold V(VCC-SENSE) with power limiting trip tF_TRIP VPROG = 2.4 V; VOUT = 0 V; VVCC = 48 V 17 25 33 VPROG = 0.9 V; VOUT = 30 V; VVCC = 48 V 17 25 33 mV Current limit threshold V(VCC-SENSE) without power limiting trip VPROG = 4 V; VSENSE = VOUT Large overload response time to GATE low VPROG = 4 V; VOUT = VSENSE; V(VCC-SENSE): 0 rising to 200 mV; C(GATE-OUT) = 2 nF; V(GATE-OUT) = 1 V 45 50 55 1.2 µs TIMER Operation (TIMER) ISOURCE ISINK VTIMER DRETRY TIMER source current TIMER sink current VTIMER = 0 V 17 27 36 VTIMER = 0 V; TJ = 25°C 22 27 32 VTIMER = 5 V 1.5 2.7 3.7 VTIMER = 5 V; TJ = 25°C 2.1 2.7 3.1 TIMER upper threshold 3.9 40 4.1 TIMER lower reset threshold TPS2492 only 0.96 1.00 1.04 Fault retry duty cycle TPS2493 only 0.5 0.75 1 IFLT = 2 mA 0.1 0.25 IFLT = 4 mA 0.25 0.5 µA V % Fault Indicator Output (FLT) Low voltage (sinking) ILEAKAGE Leakage current FLT high impedance 10 V µA Under-Voltage and Enable Input (UVEN) VUVEN_H Threshold voltage Leakage current UVEN rising Hysteresis VUVEN = 48 V 1.31 1.35 1.39 V 80 100 120 mV 1 µA Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 3 TPS2492 TPS2493 SLUSA65A – JULY 2010 – REVISED AUGUST 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) 9 V ≤ VVCC ≤ 80 V, -40°C ≤ TJ ≤ 125°C, VTIMER = 0 V and all outputs unloaded. Typical specification are at TJ = 25°C, VVCC = 48 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Gate Drive Output (GATE) GATE sourcing current IGATE GATE sinking current VSENSE = VVCC; V(GATE-OUT) = 7 V; VUVEN = Hi 15 22 35 VUVEN = Lo; VGATE = VVCC 1.8 2.4 2.8 VUVEN = Hi; VGATE = VVCC; VVCC- VSENSE = 200 mV 75 125 250 12 VGATE GATE output VUVEN = Hi, VCC = SENSE = OUT, measure VGATE -VOUT tD_ON Propagation delay: UVEN going high to GATE output high VUVEN = 0 → 2.5 V, 50% of VUVEN to 50% of VGATE, VOUT = VVCC, R(GATE-OUT) = 1 MΩ 25 40 tD_OFF Propagation delay: UVEN going low to GATE output low VUVEN = 2.5 V → 0 V, 50% of VUVEN to 50% of VGATE, VOUT = VVCC, R(GATE-OUT) = 1 MΩ, tFALL < 0.1 µs 0.5 1 tD_FAULT V : 0 → 5 V, tRISE < 0.1 µs. 50% of Propagation delay: TIMER expires TIMER VTIMER to 50% of VGATE, VOUT = VCC , to GATE output low R(GATE-OUT) = 1 MΩ, 0.8 1 IPG = 2 mA 0.1 0.25 IPG = 4 mA 0.25 0.5 1.25 1.7 16 µA mA V µs Power Good Output (PG) Low voltage (sinking) PG threshold voltage; VOUT rising; VSENSE = VVCC; measure V(VCC-OUT) PG goes low 0.8 PG threshold voltage; VOUT falling; PG goes open drain VSENSE = VVCC; measure V(VCC-OUT) 2.2 PG threshold hysteresis voltage; V(SENSE-OUT) VSENSE = VVCC tDPG PG deglitch delay; detection to output; rising and falling edges VSENSE = VVCC ILEAKAGE Leakage current; PG false open drain V 2.7 3.2 1.4 5 9 15 ms 10 µA Overvoltage Input (OV) VOV_H Threshold voltage OV rising Hysteresis 1.31 1.35 1.39 V 70 90 110 mV µA ILEAKAGE Leakage current (sinking) VOV = 5 V 1 tOFF Turn off time VOV = 0 → 2.5 V to VGS < 1 V, CGATE = 2 nF 2 Maximum duration of OV strong pull down Gate pull down 40 100 220 µs Output Voltage Feedback (OUT) IOUT Bias current VOUT = VVCC, VUVEN = Hi; sinking VOUT = GND; VUVEN = Lo; sourcing 8 20 18 40 2.8 3 µA Load Current Monitor (IMON) Output Maximum output voltage ISOURCE Source current ISINK Sink current VCC – VSENSE = 200 mV 1.9 Offset voltage Linearity (1) Error relative to curve fit, 5 mV < (VCC – VSENSE ) Output Ripple (1) (1) 4 V mA 60 Gain (VIMON/V(VCC-SENSE)) VOFFSET 2.6 µA 46 48 50 V/V -50 -5 30 mV 0.3% 8 mVPP These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 TPS2492 TPS2493 www.ti.com SLUSA65A – JULY 2010 – REVISED AUGUST 2010 DEVICE INFORMATION Functional Block Diagram VCC 14 4 V REF 2 VREF 22 mA Charge Pump ENABLE 50 mV 12 GATE 14 V PROG 3 Constant Power Engine + S SENSE 13 2 mA + 11 OUT AV = 48 + S 6 IMON 8 PG 9 FLT 4 TIMER 9-ms Deglitch + 2.7 V 1.25 V GND 7 UVLO + 8.4 V 8.3 V ENABLE 25 mA UVEN 1 + Fault Logic 1.35 V 1.25 V 1.35 V 1.26 V OV + 4V 1V 2.5 mA + 5 POR Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 5 TPS2492 TPS2493 SLUSA65A – JULY 2010 – REVISED AUGUST 2010 www.ti.com PW PACKAGE (top view) UVEN 1 14 VCC VREF 2 13 SENSE PROG 3 12 GATE TIMER 4 11 OUT OV 5 10 NC IMON 6 9 FLT GND 7 8 PG TERMINAL FUNCTIONS TERMINAL 6 I/O DESCRIPTION NAME NO. UVEN 1 I A low input inhibits GATE. A logic input can drive this pin as an enable. VREF 2 O 4-V reference voltage used to set the power threshold on PROG pin. PROG 3 I FET power-limit programming pin TIMER 4 I/O OV 5 I Overvoltage sensing input. A high input inhibits GATE. IMON 6 O Current monitor output, nominally VIMON = 48 x (VVCC-SENSE). GND 7 PWR PG 8 O Active low power good output. This is driven by VVCC-SENSE. FLT 9 O Active low fault indicator output. FLT indicates the fault timer has expired. FLT is reset by UVEN, UVLO, or automatic restart. NC 10 OUT 11 I FET source voltage (output) sensing pin. Gate is clamped to a diode drop below OUT. GATE 12 O Gate driver output for external FET. SENSE 13 I Current sensed as VVCC-SENSE and the FET VDS as VSENSE-OUT. For low FET VDS, current limits at 50mV. VCC 14 I Input supply and current sense positive input A capacitor from TIMER to ground sets the fault timer period. Ground No connect Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 TPS2492 TPS2493 www.ti.com SLUSA65A – JULY 2010 – REVISED AUGUST 2010 DETAILED PIN DESCRIPTION The following description relies on the Typical Application Diagram shown on page 1, and the Functional Block Diagram. VCC: This pin is associated with three functions: 1. Biasing power to the integrated circuit, 2. Input to power on reset (POR) and under-voltage lockout (UVLO) functions, and 3. Voltage sense at one terminal of RSENSE for M1 current measurement. The voltage must exceed the POR (about 6 V for roughly 400 µs) and the internal UVLO (about 8 V) before normal operation (driving the GATE) may begin. Connections to VCC should be designed to minimize RSENSE voltage sensing errors and to maximize the effect of C1 and D1; place C1 at RSENSE rather than at the device pin to eliminate transient sensing errors. GATE, PROG, and TIMER are held low when either UVLO or POR are active. PG and FLT are open drain when either UVLO or POR are active. SENSE: Monitors the voltage at the drain of M1, and the downstream side of RSENSE providing the constant power limit engine with feedback of both M1 current (ID) and voltage (VDS). Voltage is determined by the difference between SENSE and OUT, while the current analog is the voltage difference between VCC and SENSE. The constant power engine uses VDS to compute the allowed ID and is clamped to 50 mV, acting like a traditional current limit at low VDS. The current limit is set by the following equation: ILIM = 50mV RSENSE (1) Design the connections to SENSE to minimize RSENSE voltage sensing errors. Don't drive SENSE to a large voltage difference from VCC because it is internally clamped to VCC. The current limit function can be disabled by connecting SENSE to VCC. GATE: Provides the high side (above VCC) gate drive for external N-channel FET. It is controlled by the internal gate drive amplifier, which provides a pull-up of 22 µA from an internal charge pump and both strong (125 mA) and weak (2 mA) pull-downs to ground. The strong pull down is triggered by an overvoltage on the OV pin or large overcurrent to the load. The strong pull-down current is a non-linear function of the gate amplifier overdrive; it provides small drive for small overloads, but large overdrive for fast reaction to an output short. There is a separate pull-down of 2 mA to shut the MOSFET off when UVEN or UVLO cause this to happen. If an output short causes the VCC to fall below the UVLO, the turnoff speed will be limited by the 2mA turnoff current. An internal clamp protects the gate of the FET (to OUT). OUT: This input pin is used by the constant power engine and the PG comparator to measure VDS of M1 as V(SENSE-OUT). Internal protection circuits leak a small current from this pin when it is low. If the load circuit can drive OUT below ground, connect a clamp (or freewheel) diode from OUT (cathode) to GND (anode). The diode should clamp the output above -1 V during the transient. UVEN: The positive threshold of UVEN must be exceeded before the GATE driver is enabled. If the UVEN pin drops below the UVEN negative threshold while the GATE driver is enabled, the GATE driver will be pulled to GND by the 2-mA pull down. UVEN can be used as a logic control input, an analog input voltage monitor as illustrated by R1, R2 and R3 in the Typical Application Circuit, or it can be tied to VCC to always enable the TPS2492/3. The hysteresis associated with the internal comparator makes this a stable method of detecting a low input condition and shutting the downstream circuits off. A TPS2492 that has latched off can be reset by cycling UVEN below its negative threshold and back high. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 7 TPS2492 TPS2493 SLUSA65A – JULY 2010 – REVISED AUGUST 2010 www.ti.com VREF: Provides a 4.0-V reference voltage for use in conjunction with R4/R5 of the Typical Application Circuit to set the voltage on the PROG pin. The reference voltage is available once the internal POR and UVLO thresholds have been met. It is not designed as a supply voltage for other circuitry, therefore ensure that no more than 1 mA is drawn. Bypass capacitance is not required, but if a special application requires one, less than 1000 pF can be placed on this pin. This limit maintains VREG regulator stability. PROG: The voltage applied to this pin (0.4 V minimum) programs the power limit used by the constant power engine. Normally, a resistor divider R4/R5 is connected from VREF to PROG to set the power limit according to the following equation: VPROG = PLIM 10 ´ ILIM (2) where PLIM is the desired power limit of M1 and ILIM is the current limit set point (see SENSE). PLIM is determined by the desired thermal stress on M1: PLIM < TJ(MAX) - TS(MAX) RQJC(MAX) (3) where TJ(MAX) is the maximum desired transient junction temperature of M1 and TS(MAX) is the maximum case temperature prior to a start or restart. VPROG is used in conjunction with VDS to compute the (scaled) current, ID_ALLOWED, by the constant power engine. ID_ALLOWED is compared by the gate amplifier to the actual ID, and used to generate a gate drive. If ID < ID_ALLOWED, the amplifier turns the gate of M1 full on because there is no overload condition; otherwise GATE is regulated to maintain the ID = ID_ALLOWED relationship. A capacitor may be tied from PROG to ground to alter the natural constant power inrush current shape. If properly designed, the effect is to cause the leading step of current in Figure 13 to look like a ramp. It is not recommended that this mechanism be used to achieve a long and low ramp inrush current because the power limiting accuracy is lower at VPROG < 0.4 V. PROG is internally pulled to ground whenever UVEN, POR, or UVLO are not satisfied or the TPS2492 is latched off. This feature serves to discharge any capacitance connected to the pin. Do not apply voltages greater than 4 V to PROG. If the constant power limit is not used, PROG should be tied to VREF through a 47-kΩ resistor. TIMER: An integrating capacitor, CT, connected to the TIMER pin sets the fault-time for both versions and the restart interval for the TPS2493. The timer charges at 27 µA whenever the TPS2492/3 is in power limit or current limit and discharges at 2.7 µA otherwise. The charge-to-discharge current ratio is constant with temperature even though there is a positive temperature coefficient to both. If VTIMER reaches 4 V, the TPS2492/3 pulls GATE to ground (with the strong pull down), and discharges CT. The TPS2492 latches off when the fault timer expires. The TPS2493 holds GATE at ground when the timer expires before it attempts to restart (re-enable GATE) after a timing sequence consisting of discharging TIMER down to 1 V followed by 15 more charge and discharge cycles. Design for the TPS2393 TIMER period must assume a 3-V rise in VTIMER rather than a 4-V rise to accommodate a restart. The TPS2492 can be reset by either cycling the UVEN pin or the UVLO (e.g. power cycling). TIMER discharges when UVEN is low or the internal UVLO or POR are active. The TIMER pin should be tied to ground if this feature is not used. 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 TPS2492 TPS2493 www.ti.com SLUSA65A – JULY 2010 – REVISED AUGUST 2010 PG: The power good output is an active low, open-drain output intended to interface to downstream DC-to-DC converters or monitoring circuits. PG goes low after VDS of M1 has fallen to about 1.25 V and a 9-ms deglitch time period has elapsed. PG is open drain whenever UVEN is low, VDS of M1 is above 2.7 V, or UVLO is active. PG can also be viewed as having an output voltage monitor function. The 9-ms deglitch circuit operates to filter short events that could cause PG to go inactive (open drain) such as a momentary overload or input voltage step. VPG can be greater than VVCC because it’s ESD protection is only with respect to ground. PG may be left open or tied to GND if not used. GND: This pin is connected to system ground. IMON: This current monitor output has a voltage equal to 48 times the voltage across RSENSE (VVCC-SENSE). IMON is clamped at 2.7 V to prevent damage to downstream A/D circuits. IMON is a voltage output and does not require a pull up or pull down. IMON will have a small amount of superimposed ripple at 2.5 kHz that is an artifact of the monitoring circuit. The error due to the ripple does not significantly effect accuracy for signals on the order of 1 V, but better accuracy may be achieved for small signals with an external R-C filter. The IMON pull up source is stronger than the pull down. A resistor pull down can be used to improve transient response in designs with large filter capacitors. Leave IMON open if not used. A curve of Linearity (%) versus VVCC-SENSE is provided in the Typical Characteristics, providing an indication of error versus signal level. This curve is constructed by first performing a first order curve fit to VIMON versus VVCC-SENSE, yielding Gain and Offset terms for the linear fit. The Linearity (%) plot is calculated as: Linearity(%) = VIMON - éë(Gain ´ VVCC - SENSE ) + Offset ùû éë(Gain ´ VVCC - SENSE ) + Offset ùû ´ 100 (4) FLT: This active low, open drain output asserts (goes low) when the fault timer expires after a prolonged over current or an OV is detected. FLT is open drain whenever UVEN, POR, or UVLO are not satisfied. FLT is latched in the TPS2492, clearing when the latch is reset. FLT clears automatically in the TPS2493 when a power-up retry occurs. VFLT can be greater than VVCC because it's ESD protection is only with respect to ground. FLT may be left open or tied to GND when not used. OV: The over-voltage monitoring pin is programed with a resistor divider such as R1 - R3 in the Typical Application Circuit. This function forces GATE and FLT low while the OV condition exists. While VOV exceeds its threshold, the strong GATE pull down (125 mA) is applied for up to 100 µs, followed by the 2 mA pull down. The GATE pull down and FLT are released as soon as the OV condition is cleared. Tie OV to GND if not used. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 9 TPS2492 TPS2493 SLUSA65A – JULY 2010 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE CURRENT LIMIT TRIP vs SUPPLY VOLTAGE 55 900 − Current Limit Trip − mV V( VCC − Sense) TJ = 125°C 800 ICC - Supply Current - mA 700 600 500 TJ = -40°C TJ = 25°C 400 300 200 100 54 53 52 TJ = −405C 51 50 TJ = 255C 49 48 TJ = 1255C 47 46 45 9 0 9 19 29 49 39 59 VCC - Supply Voltage - V 69 79 69 Figure 2. GATE PULL UP CURRENT vs SUPPLY VOLTAGE GATE PULL DOWN CURRENT(UVEN = 0 V) vs SUPPLY VOLTAGE 79 2.6 I Gate − Gate Pullup Current (EN = OV) − mA 33 31 29 27 TJ = 1255C 25 23 TJ = 255C 21 19 TJ = −405C 17 TJ = 1255C 2.5 TJ = 255C 2.4 2.3 TJ = −405C 2.2 2.1 2 15 9 19 29 39 49 59 VCC − Supply Voltage − V 69 79 9 19 Figure 3. 10 29 39 49 59 VCC − Supply Voltage − V Figure 1. 35 I Gate − Gate Pullup Current − mA 19 29 39 49 59 69 79 VCC − Supply Voltage − V Figure 4. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 TPS2492 TPS2493 www.ti.com SLUSA65A – JULY 2010 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) GATE PULL DOWN CURRENT vs SUPPLY VOLTAGE (UVEN = 4 V, V(VCC – SENSE) = 200 mV) CURRENT LIMIT RESPONSE TIME vs SUPPLY VOLTAGE (UVEN = 4 V, V(VCC – SENSE) = 200 mV) 215 1200 195 T − Current Limit Response Time − nS I Gate − Gate Pulldown Current − mA TJ = 1255C TJ = −405C 175 TJ = 255C 155 135 115 TJ = 1255C 95 75 9 19 29 39 49 59 VCC − Supply Voltage − V 69 1000 TJ = 255C 800 600 TJ = −405C 400 200 0 79 9 14 19 24 29 34 39 VCC − Supply Voltage − V Figure 5. Figure 6. GATE OUTPUT VOLTAGE vs SUPPLY VOLTAGE TIMER PULL UP CURRENT vs SUPPLY VOLTAGE 44 49 13.9 32 TJ = 1255C I Timer − Timer Pullup Current − µ A VGATE - Output Voltage - V 13.8 TJ = 125°C 13.7 13.6 TJ = 25°C 13.5 13.4 TJ = -40°C 13.3 30 28 TJ = 255C 26 24 TJ = −405C 22 20 18 9 13.2 9 19 39 59 29 49 VCC - Supply Voltage - V 69 19 79 Figure 7. 29 39 49 59 69 79 VCC − Supply Voltage − V Figure 8. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 11 TPS2492 TPS2493 SLUSA65A – JULY 2010 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) TIMER CHARGE/DISCHARGE RATIO vs SUPPLY VOLTAGE AND TEMPERATURE UVEN AND OV THRESHOLD VOLTAGE (falling) vs SUPPLY VOLTAGE 1.255 VUVEN - UVEN Threshold Voltage (Falling) - V ITimer − Charge/Discharge Ratio 9.80 9.75 TJ = 255C TJ = −405C 9.70 TJ = 1255C 9.65 1.254 TJ = 125°C 1.253 1.252 1.251 1.250 1.249 1.248 1.247 TJ = 25°C TJ = -40°C 1.246 9.60 9 19 29 39 49 59 VCC − Supply Voltage − V 69 79 1.245 9 Figure 10. UVEN AND OV THRESHOLD VOLTAGE (rising) vs SUPPLY VOLTAGE LINEARITY vs SUPPLY VOLTAGE 69 79 0.8 TJ = 125°C TJ = -40°C 0.7 1.350 0.6 TJ = 25°C 0.5 Linearity - % 1.349 1.348 0.4 0.3 TJ = 25°C 0.2 1.347 0.1 TJ = 125°C 0 TJ = -40°C 1.346 -0.1 1.345 -0.2 9 19 29 39 49 59 VCC - Supply Voltage - V 69 79 0 10 Figure 11. 12 29 49 39 59 VCC - Supply Voltage - V Figure 9. 1.351 VUVEN - UVEN Threshold Voltage (Rising) - V 19 30 40 20 50 VCC-VSENSE - Supply Voltage - mV 60 Figure 12. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 TPS2492 TPS2493 www.ti.com SLUSA65A – JULY 2010 – REVISED AUGUST 2010 APPLICATION INFORMATION Basic Operation The TPS2492/93 features include: 1. Adjustable under-voltage and over-voltage lockout; 2. Turn-on inrush limit; 3. High-side gate drive for an external N-channel FET; 4. FET protection (power limit and current limit); 5. Adjustable overload timeout; 6. Output current monitor; 7. Status output; 8. Charge-complete indicator for downstream converter sequencing; and 9. Optional automatic restart mode. The TPS2492/93 features power-limiting FET protection that allows independent control of current limit (to set maximum full-load current), power limit (to keep FET in its safe operating area), and overload time (to control temperature rise). The power limiting feature controls the V and I across the FET to protect it, and does not control load power. This protection is a specialized form of foldback output limiting. Given a constant power dissipation, computation of peak junction temperature is straight forward. The TPS2393 provides a small operating duty cycle into a short, reducing the average temperature rise of the FET to levels similar to normal operation in many systems. This prevents overheating and failure with prolonged exposure to an output short. The typical application circuit, and oscilloscope plots of Figure 13 and Figure 17 demonstrate many of the functions described above. Board Plug-In (Figure 13) Only the bypass capacitor charge current and small bias currents are evident when a board is first plugged in as seen in Figure 13. The TPS2492/93 is held inactive with GATE, PROG, and TIMER held low, and with PG and FLT open drain, for less than 1 ms while internal voltages stabilize. Then GATE, PROG, TIMER, FLT and PG are released and the part begins sourcing current to the GATE pin because UVEN is high and OV is low. The external FET begins to turn on while the voltage across it, V(SENSE-OUT), and current through it, V(VCC-SENSE)/RSENSE, are monitored. Current initially rises to the value which satisfies the power limit engine (PLIM/ VVCC) since the output capacitor was discharged. The shape of the input current waveform shows the operation of the FET power limit. In this case, the 5-A current limit is never reached as the output reaches full charge. This is likely due to the limited gate slew rate. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 13 TPS2492 TPS2493 SLUSA65A – JULY 2010 – REVISED AUGUST 2010 www.ti.com TIMER and PG Operation (Figure 13) The TIMER pin charges CT as long as limiting action continues, and discharges at a 1/10 charge rate when limiting stops. If the voltage on CT reaches 4 V before the output is charged, the external FET is turned off and either a latch-off or restart cycle commences, depending on the part type. The open-drain PG output provides a deglitched end-of-charge indication which is based on the voltage across the external FET. PG is useful for preventing a downstream DC-to-DC converter from starting while CO is still charging. PG goes active (low) about 9 ms after CO is charged. This delay allows the external FET to fully turn on and any transients in the power circuits to end before the converter starts up. The resistor pull-up shown on pin PG in the Typical Application Circuit only demonstrates operation; the actual connection to the converter depends on the application. Timing can appear to terminate early in some designs if operation transitions out of the power limit mode into a gate charge-rate limited mode at low VDS values. This effect sometimes occurs because gate capacitances, CGD and CGS, are nonlinear with applied voltage, getting larger at smaller voltage. This can be seen in Figure 13. Figure 13. Basic Board Insertion 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 TPS2492 TPS2493 www.ti.com SLUSA65A – JULY 2010 – REVISED AUGUST 2010 Action of the Constant Power Engine (Figure 14) The calculated power dissipated in the external FET, VDS x ID, is computed under the same startup conditions as Figure 13. The current of the external FET, labeled IIN, initially rises to the value that satisfies the constant power engine; in this case it is 25 W / 48 V = 0.52 A. The 25-W value is programmed into the engine by setting the PROG voltage using R4 and R5. VDS of the external FET, which is calculated as V(SENSE-OUT), falls as CO charges, thus allowing the external FET drain current to increase. This is the result of the internal constant power engine adjusting the current limit reference to the GATE amplifier as CO charges and VDS falls. The calculated device power in Figure 14, labeled POWER, is seen to be reasonably constant within the limitations of circuit tolerance and acquisition noise. A fixed current limit is implemented by clamping the constant power engine output to 50 mV when VDS is low. This protection technique can be viewed as a specialized form of foldback limiting; the benefit over linear foldback is that it yields the maximum output current from a device over the full range of VDS while still protecting the device. Figure 14. Computation of the External FET Stress During Startup Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 15 TPS2492 TPS2493 SLUSA65A – JULY 2010 – REVISED AUGUST 2010 www.ti.com Response to a Hard Output Short (Figure 15, Figure 16, and Figure 17) Figure 15 shows the short circuit response over the full time-out period. An output short is applied, causing the voltage to fall, limiter action begin, and the fault timer to start. The external FET current is actively controlled by the power limiting engine and gate amplifier circuit while the TIMER pin charges CT to the 4-V threshold. Once this threshold is reached, the TPS2492/93 turns off the external FET. The TPS2492 latches off until either the input voltage drops below the UVLO threshold or UVEN cycles through the false (low) state. The TPS2493 will attempt a restart after going through a timing cycle. Figure 16 demonstrates the operation of FLT during a short circuit. FLT remains false (open drain) until the TIMER has expired. Figure 15. Current Limit Overview 16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 TPS2492 TPS2493 www.ti.com SLUSA65A – JULY 2010 – REVISED AUGUST 2010 Figure 16. FLT Operation Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 17 TPS2492 TPS2493 SLUSA65A – JULY 2010 – REVISED AUGUST 2010 www.ti.com The TPS2492/93 responds rapidly to a short circuit as seen in Figure 17. The falling OUT voltage is the result of the external FET and CO currents through the short circuit impedance. The internal GATE clamp causes the GATE voltage to follow the output voltage down and subsequently limits the negative VGS. The IIN waveform includes current into an input 47 µF capacitor. M1 drain current has a peak value in excess of the waveform, and terminates when VGATE approaches VOUT. The rapidly rising fault current overdrives the GATE amplifier causing it to overshoot and rapidly turn the external FET off by sinking current to ground. At a time beyond the extent of Figure 17, but within the scope of Figure 15, the FET will be slowly turned back on as the GATE amplifier recovers. The operating point will settle to the current or power limit, and finally the TIMER will expire and the FET will turn off. Limited input voltage overshoot appears in Figure 17 because a local 47-mF bypass capacitor and 1000 mF distribution capacitor were used. The input voltage overshoots as the input current abruptly drops due to the stored energy in the input wiring inductance. The exact waveforms seen in an application depend upon many factors including parasitics of the voltage distribution, circuit layout, and the short itself. Figure 17. Current Limit Onset 18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 TPS2492 TPS2493 www.ti.com SLUSA65A – JULY 2010 – REVISED AUGUST 2010 Automatic Restart (Figure 18) The TPS2493 automatically initiates a restart after a fault has caused it to turn off the external FET. Internal control circuits use CT to count 16 cycles before re-enabling the external FET. This sequence repeats if the fault persists. TIMER has a 1:10 charge-to-discharge current ratio, and uses a 1-V lower threshold. The fault-retry duty cycle specification in the Electrical Characteristics Table quantifies this behavior. This small duty cycle often reduces the average short-circuit power dissipation to levels associated with normal operation and reduces the need for additional measures such as oversized heatsinking. Figure 18 demonstrates that the initial timing cycle starts with VTIMER at zero V, subsequent cycles start with VTIMER at 1 V, and a succesful restart occurs after a 16 cycle delay. Figure 18. TPS2492/93 Restart Cycle Timing Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 19 TPS2492 TPS2493 SLUSA65A – JULY 2010 – REVISED AUGUST 2010 www.ti.com Application Design Example The following example illustrates the design and component selection process for a TPS2492/93 application. Figure 19 shows the application circuit for this design example. The requirements of this design are: • • • • • • • • • Nominal System Voltage: 12 V Maximum Operating System Voltage: 13.5 V Overvoltage Threshold: 14.5 V Undervoltage Threshold: 9.5 V Steady-state Load Current: 40 A Load Capacitance: 1000 µF Maximum Ambient Temperature: 50°C Maximum Static Junction Temperature 125°C Maximum Transient Junction Temperature: 150°C M1 RSENSE VIN VOUT R1 CO TPS2492 D1 1 UVEN VCC 14 D2 RG 2 VREF SENSE 13 3 PROG GATE 12 4 TIMER OUT 11 5 OV 6 IMON R4 R2 CG NC 10 CT FLT 9 R5 Optional Startup Method C1 7 R3 GND PG 8 RCG R6 IMON C2 Optional IMON Filter Figure 19. TPS2492/93 Design Example Schematic 20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 TPS2492 TPS2493 www.ti.com SLUSA65A – JULY 2010 – REVISED AUGUST 2010 1. Choose RSENSE Calculate RSENSE using a multiplier factor of 1.2 (20%) for VSENSE and RSENSE tolerance along with some additional margin. RSENSE = VSENSE 50mV = = 1.042mΩ 1.2 ´ ILIMIT 1.2 ´ 40A (5) Choose RSENSE = 1 mΩ, resulting in a nominal 50 A current limit. VSENSE( MAX ) ILIMIT(MAX) = RSENSE 2 LIMIT(MAX) PRSENSE = I = 55mV = 55 A 1mΩ (6) 2 ´ RSENSE = 55 A ´ 1mW = 3.025W (7) Multiple sense resistors in parallel should be considered. 2. Choose M1 Select the M1 VDS rating allowing for maximum input voltage and transients. Then select an operating RDSON, package, and cooling to control the operating temperature. Most manufacturers list RDSON(MAX) at 25°C and provide a typical characteristics curve from which values at other temperatures can be derived. The next equation can be used to estimate desired RDSON(MAX) at the maximum operating junction temperature of TJ(MAX). (usually 125°C). TA(MAX) is the maximum expected ambient temperature. Assume that a thermal resistance, RqJA of 10 °C/W can be achieved by reinforcing the typical 40°C/W for a 12 inch copper pad with copper on multiple layers and some airflow. RDSON(MAX) = TJ(MAX) - TA(MAX) 2 LIMIT(NOM) Rq JA ´ I = 125°C - 50°C = 3mΩ at TJ = 125°C °C 2 10 ´ (50A) W (8) Assume that we are able to find a suitable FET with an RDSON of 0.74 mΩ at 25°C and 1.18 mΩ at 125°C. These devices are in a package such as a D2PAK with a large copper base and very low RqJC. The junction-to-ambient thermal resistance, RqJA, depends upon the package style chosen and the details of heat-sinking and cooling including the PCB layout. Actual “in-system” temperature measurements will be required to validate thermal performance. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 21 TPS2492 TPS2493 SLUSA65A – JULY 2010 – REVISED AUGUST 2010 www.ti.com 3. Choose the Power Limit PLIM and the PROG Resistors, R4 and R5 M1 dissipates large amounts of power during power-up or output short circuit. Power limit, PLIM should be set to prevent the M1 die temperature from exceeding a short term maximum temperature, TJ(MAX2). Short term TJ(MAX2) may be set as high as 150°C (specified on FET datasheet) while still leaving ample margin for the typical manufacturer's rating of 175°C. The R4 and R5 resistors set VPROG, programming the FET power dissipation. Assume that RqJA is 10 °C/W, RqJC is 0.2 °C/W, and RqCA is 9.8 °C/W for the device we chose above. PLIM can be estimated as follows: PLIM = ( ) 2 0.7 ´ ëéTJ(MAX2) - Rq CA ´ ILIMIT(NOM) ´ RDSON - TA(MAX) ûù = 249W Rq JC (9) Where RqCA is the M1 plus PCB case-to-ambient thermal resistance, RqJC is M1 junction-to-case thermal resistance, RDSON is M1 channel resistance at the maximum operating temperature, and the factor of 0.7 accounts for the tolerance of the constant power engine. In this case we know that power limit is less than ILIMIT x VIN and that power limit will control operation during a short circuit. It is often advantageous to use a transient value of RqJC to get a usable solution, that is a VPROG within the recommended range. If a current/power limited startup is used, transient RqJC should be based on the TIMER period (see below). FET manufacturers typically provide transient thermal resistance in graphic format on their datasheet. Additional information can be found in SLVA158. The following equations calculate VPROG and R4 using an assumed R5 = 20 kΩ. VPROG = PLIM 249 = = 0.498V 10 ´ ILIM 10 ´ 50 (10) V R 4 = R5 ´ ( REF - 1) = 140.6kΩ VPROG (11) Choose R4 = 140 kΩ. The recommended minimum VPROG is 0.4 V. This is based on tolerance and accuracy of the constant power engine making very low power-limited designs highly variable. Some suggestions to get larger PLIM values are to start with a low static operating junction temperature, and to utilize the transient thermal impedance (energy absorbing nature) of the package. The output I vs. VOUT curve for this configuration is shown in Figure 20. OUTPUT CURRENT vs OUTPUT VOLTAGE (V VCC = 12 V) 60 IOUT - Output Current - A 50 40 30 20 10 0 12 10 8 4 6 VOUT - Output Voltage - V 2 0 Figure 20. TPS2492/93 Power and Current Limit Curve 22 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 TPS2492 TPS2493 www.ti.com SLUSA65A – JULY 2010 – REVISED AUGUST 2010 4. Choose the TIMER Capacitor, CT and Turn-On Time The turn on time tON, represents the time it takes the circuit to charge up the output capacitance CO and load. CT programs the fault time and should be chosen so that the fault timer does not terminate prior to completion of start up. The turn on time is a function of the type of control; current limit, power limit, or dV/dt control. The following equations calculates tON for the power limit and current limit cases, and assume that only CO draws current during startup. For PLIM < VVCC(MAX) ´ ILIMIT(NOM) : tON = For PLIM ³ VVCC(MAX) ´ ILIMIT(NOM) : tON = tON = 2 VCC(MAX) C ´V CO ´ PLIM + O 2 2 ´ ILIMIT(NOM) 2 ´ PLIM CO ´ PLIM(ACT) 2 2 ´ ILIMIT(NOM) + CO ´ VVCC(MAX) ILIMIT(NOM) 2 CO ´ VVCC(MAX) 2 ´ PLIM(ACT) (Power Limit ) (12) (Current Limit Only ) (13) 2 = 1000 m F ´ 249W 1000 m F ´ 13.5V + = 416 m s 2 ´ 502 A 2 ´ 249W (14) The next equation computes CT for a TPS2492 application. TPS2492/93 TIMER current source and capacitor tolerances are accounted for. CT = CT = ISOURCE(MAX) VTMR-TH(MAX) ´ tON ´ ( 1 + CO-TOL + CT-TOL ) (15) 36 m A ´ 416 m s ´ ( 1 + 0.2 + 0.1) = 4.75nF 4.1V (16) Choose CT = 6.8 nF assuming a 20% output capacitor tolerance and a 10% timing capacitor tolerance. Equation 16 is written around startup for a TPS2492, however during a restart (after a fault) of a TPS2493, CT charges from 1 V to 4.1 V, requiring a VTMR-TH(MAX) value of 3.1V. The maximum TIMER period may be calculated using the minimum TIMER charge current and maximum value of CT. Use this period to determine the transient RqJC in step 3. While this is beyond the scope of this example, it may lead to some iteration. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 23 TPS2492 TPS2493 SLUSA65A – JULY 2010 – REVISED AUGUST 2010 www.ti.com 5. Choose the Turn-On and Over-voltage Divider, R1 - R3 Per our system design requirements above, both over-voltage shutdown and under-voltage shutdown are desired. Equations for calculating the thresholds are: VOV _ H = VOV ´ R3 (R1+R2+R3 ) VUVEN _ H = (17) VUV ´ (R2+R3 ) (R1+R2+R3 ) (18) Assume R3 is 1 kΩ and use the following procedure to determine R1 and R2. R1+R2 = R2+R3 = R3 ´ (VOV -VOV_H ) 1k W ´ (14.5V - 1.35V ) = = 9.7407k W 1.35V (VUV_H ) (19) VUVEN_H ´ ((R1 + R 2 ) + R 3 ) 1.25V ´ (9.7407k W + 1k W ) = = 1.4133k W 9.5V (VUV ) (20) R2= (R2+R3 ) - R3 = 1.4133k W - 1k W = 0.4133k W (21) R1= (R1+R2 ) - R2 = 9.7407k W - 0.4133k W = 9.3275k W (22) Selecting standard 1% values and scaling up by a factor of 10 to reduce power loss results in (R1 = 93.1 kΩ), (R2 = 4.12 kΩ), and (R3 = 10 kΩ). Alternative Inrush Designs Gate Capacitor (dV/dt) Control The TPS2492/93 can be used with applications that require constant turn-on currents. The current is controlled by a single capacitor from the GATE terminal to ground with a series resistor. M1 appears to operate as a source follower (following the gate voltage) in this implementation. Again assuming that the output capacitor charges without additional loading, choose a time to charge, tON, based on the load capacitor, CO input voltage VI, and desired charge current ICHARGE. When power limiting is used (VPROG < VREF) choose ICHARGE to be less than PLIM /VVCC to prevent the fault timer from starting. The fault timer starts only if power or current limit is invoked. tON = CO ´ VVCC ICHARGE (23) Use the following equation to select the gate capacitance, CG. It has been assumed that the external added (linear) capacitor is much larger than the FET capacitance. CGD is the gate capacitance of M1, and IGATE is the TPS2492/93 nominal gate charge current. CGD is non-linear with applied VDG. An averaged estimate may be made using the FET VGS vs QG curve. Divide the charge accumulated during the plateau region by the plateau VGS to get CGD. As shown in Figure 19, a series resistor of about 1 kΩ should be used in series with CG to avoid slowing the turnoff. CG = IGATE ´ tON - CGD VVCC (24) If neither power nor current limit faults are invoked during turn on, CT can be chosen for fast transient turnoff response. Considerations are junction temperature rise (as above), anticipated system noise, and possible peak overloads due to input voltage or load transients. Generally the period should be much less than the tON of step 4 above. 24 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 TPS2492 TPS2493 www.ti.com SLUSA65A – JULY 2010 – REVISED AUGUST 2010 Additional Design Considerations Calculation Tool SLVC033 The calculation tool for the TPS2490/91, SLVC033, may be used with the TPS2492/93. For accurate results, the timer current constants need to be updated. This may be accomplished using the Excel Tools / Protection command along with the password provided in the tool (spreadsheet). Use of PG to Control Downstream Converters Use the PG pin to control and sequence a downstream DC/DC converter. If this is not done a long time delay may be needed to allow CO to fully charge before the converter starts. This practice will avoid having the converter attempt to operate at a low input voltage, drawing large currents. This mode of converter operation has the potential to form a stable operating point with the hotswap output I-V characteristic, preventing the system from starting. IMON Filtering The internal monitoring circuits leave a small amount of residual noise at about 2.5 kHz on the IMON output. While this does not contribute significant error at output voltages on the order of 1 V, better accuracy at low outputs will benefit from an R-C filter. Figure 19 demonstrates this filtering with elements R6 and C2. An example solution is a 1 kΩ resistor and a 1.5 nF capacitor. A buffer (e.g. unity-gain opamp) may be required if the output is used by a circuit that draws significant current. Output Clamp Diode Inductive loads or wiring inductance on the output may drive the OUT pin below GND when the circuit is unplugged or during current limit. The OUT pin can be protected by D2 (see Figure 19) between the TPS2492/93 OUT to GND pins. The OUT pin can withstand a short transient to -1 V. Input Clamp TVS Energy stored in the inductance of input wiring has the capability to drive the input voltage up if the (load) current is abruptly decreased. An example is a hard short on OUT rapidly raising the input current above the current limit threshold, which is then abruptly driven to zero when the current limit gains control after several microseconds. Combinations of input capacitance and transient voltage suppressor diodes (TVS - a type of Zener Diode) can aid in controlling the voltage overshoot. This is demonstrated by D1 and C1 of Figure 19. While a small bypass capacitor is recommended, the TVS is better able to control the voltage without the drawback of large input capacitance. Gate Clamp Diode The TPS2492/93 has a relatively well-regulated gate voltage of 12 V to 16 V, even at low supply voltages. A small clamp Zener from gate to source of M1, such as a BZX84C7V5, is recommended if VGS of M1 is rated below this. Input Bypass Capacitance The input bypass capacitor, C1 per Figure 19 should be used to provide a low impedance local source of current and control the supply dv/dt on the VCC pin. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 25 TPS2492 TPS2493 SLUSA65A – JULY 2010 – REVISED AUGUST 2010 www.ti.com Adding External GATE-OUT Capacitance Avoid directly placing ceramic capacitors directly across M1 gate to source when bypassing for ESD or noise is desired. Add some small resistance in series with the capacitor if absolutely required. If the resistance is not present, the added phase shift may encourage high frequency oscillation of the combined input and output L-C circuits during startup conditions. High Gate Capacitance Applications If OUT falls very rapidly during a fault, the FET VGS can be driven high by the CGD - CGS voltage divider of (VSENSE - VOUT). Given enough capacitance and dv/dt, the internal 14-V GATE to OUT clamp may not have the capability to fully control the voltage. An external gate clamp Zener diode may be required to protect the FET if this is the case. When gate capacitor dV/dT control is used, a 1-kΩ resistor in series with CG is recommended, as shown in Figure 19. Output Short Circuit Measurements Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads, circuit layout and component selection, output shorting method, relative location of the short, and instrumentation all contribute to varying results. The actual short itself exhibits a certain degree of randomness as it microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do not expect to see waveforms exactly like those in the data sheet since every setup differs. Applications Using the Retry Feature (TPS2493) Applications using the retry feature may want to estimate fault retry time. The TPS2493 will retry (enable M1 to attempt turn on) once for every 16 timer charge/discharge cycles (15 cycles between 1 V and 4 V, 1 cycle between 0 V and 4 V). TRETRY =CT ´ 19.6 ´ 106 (25) M1 Selection Use of a power FET in the linear region places large, long term stresses on the distributed junction. FETs whose safe operating area (SOA) curves display multiple slopes on the same line (e.g. a line whose time parameter is a constant) in the region of high voltage and low current generally are susceptible to secondary breakdown and are not strong candidates for this application. An example of a good choice is found in the Typical Application Circuit where the line at 10 ms shows no breaks in slope. The best device for the application is not always the lowest RDSON device. Layout Considerations Good layout practice places the power devices D1, RSENSE, M1, and CO so power flows in a sequential, linear fashion. A ground plane under the power and the TPS2492/93 is desirable. The TPS2492/93 should be placed close to the sense resistor and FET using a Kelvin type connection to achieve accurate current sensing across RSENSE. A low-impedance GND connection is required because the TPS2492/93 can momentarily sink upwards of 100 mA from the gate of M1. The GATE amplifier has high bandwidth while active, so keep the GATE trace length short. The PROG, TIMER, OV, and UVEN pins have high input impedances, therefore keep their input leads short. Oversize power traces and power device connections to assure low voltage drop and good thermal performance. 26 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 TPS2492 TPS2493 www.ti.com SLUSA65A – JULY 2010 – REVISED AUGUST 2010 REVISION HISTORY Changes from Original (July 2010) to Revision A • Page Changed marketing status .................................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2492 TPS2493 27 PACKAGE OPTION ADDENDUM www.ti.com 27-Aug-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS2492PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples TPS2492PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples TPS2493PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples TPS2493PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Aug-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2492PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TPS2493PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Aug-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2492PWR TSSOP PW 14 2000 346.0 346.0 29.0 TPS2493PWR TSSOP PW 14 2000 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. 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