TI 74ALVTH16374GRE4

SN54ALVTH16374,, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
www.ti.com
FEATURES
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State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus™ Design for 2.5-V
and 3.3-V Operation and Low Static Power
Dissipation
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With 2.3-V to
3.6-V VCC)
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
High Drive (–24/24 mA at 2.5-V VCC and –32/64
mA at 3.3-V )
Power Off Disables Outputs, Permitting Live
Insertion
High-Impedance State During Power Up and
Power Down Prevents Driver Conflict
Uses Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to Prevent
the Bus From Floating
Auto3-State Eliminates Bus Current Loading
When Output Exceeds VCC + 0.5 V
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection
– Exceeds 2000 V Per MIL-STD-883, Method
3015
– Exceeds 200 V Using Machine Model
– Exceeds 1000 V Using Charged-Device
Model, Robotic Method
Flow-Through Architecture Facilitates Printed
Circuit Board Layout
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink Small-Outline
(DGG), Thin Very Small-Outline (DGV)
Packages, and 380-mil Fine-Pitch Ceramic Flat
(WD) Package
SCES068G – JUNE 1996 – REVISED NOVEMBER 2006
SN54ALVTH16374...WD PACKAGE
SN74ALVTH16374...DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK
DESCRIPTION/ORDERING INFORMATION
The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V or
3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These
devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and
working registers.
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CLK), the flip-flops store the logic levels set up at the data (D) inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1996–2006, Texas Instruments Incorporated
SN54ALVTH16374,, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
www.ti.com
SCES068G – JUNE 1996 – REVISED NOVEMBER 2006
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ALVTH16374 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ALVTH16374 is characterized for operation from –40°C to 85°C.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE PART NUMBER
TSSOP – DGG
Reel of 2000
TVSOP – DGV
Reel of 2000
–40°C to 85°C
Tube of 25
SSOP – DL
Reel of 1000
2
74ALVTH16374GRE4
SN74ALVTH16374GR
74ALVTH16374VRE4
SN74ALVTH16374VR
74ALVTH16374DL
SN74ALVTH16374DLG4
SN74ALVTH16374DLR
SN74ALVTH16374DLRG4
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TOP-SIDE MARKING
SN54ALVTH16374,, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
www.ti.com
SCES068G – JUNE 1996 – REVISED NOVEMBER 2006
ZQL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
TERMINAL ASSIGNMENTS (1)
(1)
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
1CLK
B
1Q2
1Q1
GND
GND
1D1
1D2
C
1Q4
1Q3
VCC
VCC
1D3
1D4
D
1Q6
1Q5
GND
GND
1D5
1D6
E
1Q8
1Q7
1D7
1D8
F
2Q1
2Q2
2D2
2D1
G
2Q3
2Q4
GND
GND
2D4
2D3
H
2Q5
2Q6
VCC
VCC
2D6
2D5
J
2Q7
2Q8
GND
GND
2D8
2D7
K
2OE
NC
NC
NC
NC
2CLK
NC – No internal connection
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
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SN54ALVTH16374,, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
www.ti.com
SCES068G – JUNE 1996 – REVISED NOVEMBER 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
1OE
1CLK
1D1
1
2OE
48
2CLK
C1
47
2
1D
1Q1
24
25
C1
2D1
36
To Seven Other Channels
13
1D
2Q1
To Seven Other Channels
Pin numbers shown are for the DGG, DL, and WD packages.
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
7
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
7
V
7
V
VO
Voltage range applied to any output in the high
IO
Output current in the low state
IO
Output current in the high state
IIK
IOK
θJA
Package thermal impedance (4)
state (2)
–0.5
SN54ALVTH16374 (3)
(2)
(3)
(4)
4
mA
SN74ALVTH16374
128
SN54ALVTH16374 (3)
–48
SN74ALVTH16374
–64
Input clamp current
VI < 0
–50
mA
Output clamp current
VO < 0
–50
mA
DGG package
89
DGV package
93
DL package
94
Tstg Storage temperature range
(1)
96
UNIT
–65
150
mA
°C/W
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
Product preview
The package thermal impedance is calculated in accordance with JESD 51.
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SN54ALVTH16374,, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES068G – JUNE 1996 – REVISED NOVEMBER 2006
Recommended Operating Conditions
(1)
VCC = 2.5 V ± 0.2 V
SN54ALVTH16374 (2)
MIN
VCC
Supply voltage
2.3
VIH
High-level input voltage
1.7
VIL
Low-level input voltage
VI
Input voltage
IOH
High-level output current
Low-level output current
IOL
0
MIN
TYP MAX
2.7
2.3
2.7
1.7
VCC
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz
Input transition rise or fall rate
∆t/∆VCC
Power-up ramp rate
200
TA
Operating free-air temperature
–55
(2)
SN74ALVTH16374
MAX
Outputs enabled
UNIT
V
V
0.7
∆t/∆v
(1)
TYP
0.7
V
5.5
V
–6
–8
mA
6
8
18
24
5.5
0
VCC
10
10
ns/V
µs/V
200
125
mA
–40
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Product preview
Recommended Operating Conditions (1)
VCC = 3.3 V ± 0.3 V
SN54ALVTH16374 (2)
MIN
VCC
Supply voltage
3
VIH
High-level input voltage
2
VIL
Low-level input voltage
VI
Input voltage
IOH
High-level output current
Low-level output current
IOL
∆t/∆v
MIN
3.6
3
TYP
MAX
3.6
2
UNIT
V
V
0.8
V
5.5
V
–24
–32
mA
24
32
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz
48
64
Input transition rise or fall rate
10
10
0
Outputs enabled
200
TA
–55
(2)
SN74ALVTH16374
MAX
0.8
∆t/∆VCC Power-up ramp rate
(1)
TYP
Operating free-air temperature
VCC
5.5
0
VCC
–40
ns/V
µs/V
200
125
mA
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Product preview
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SN54ALVTH16374,, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
www.ti.com
SCES068G – JUNE 1996 – REVISED NOVEMBER 2006
Electrical Characteristics
over operating free-air temperature range VCC = 2.5 V ± 0.2 V (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
VCC = 2.3 V,
VCC = 2.3 V
MIN TYP (2)
II = –18 mA
VCC = 2.3 V to 2.7 V, IOH = –100 µA
VOH
SN54ALVTH16374 (1)
IOH = –6 mA
–1.2
–1.2
1.8
0.2
0.2
0.4
IOL = 8 mA
0.4
IOL = 18 mA
Data inputs
0.5
VI = VCC or GND
±1
±1
VCC = 0 or 2.7 V,
VI = 5.5 V
10
10
VI = 5.5 V
10
10
1
1
–5
–5
VCC = 2.7 V
VI = VCC
VI = 0
±100
µA
Ioff
VCC = 0,
VI or VO = 0 to 4.5 V
IBHL (3)
VCC = 2.3 V,
VI = 0.7 V
115
115
µA
IBHH (4)
VCC = 2.3 V,
VI = 1.7 V
–10
–10
µA
(5)
VCC = 2.7 V,
VI = 0 to VCC
300
300
IBHHO (6)
VCC = 2.7 V,
VI = 0 to VCC
–300
–300
IEX (7)
VCC = 2.3 V,
VO = 5.5 V
IOZ(PU/PD) (8)
VCC ≤ 1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE = don’t care
IOZH
IBHLO
µA
µA
µA
125
125
µA
±100
±100
µA
VCC = 2.7 V, VO = 2.3 V,
VI = 0.7 V or 1.7 V
5
5
µA
IOZL
VCC = 2.7 V, VO = 0.5 V,
VI = 0.7 V or 1.7 V
–5
–5
µA
0.04
0.1
0.1
ICC
VCC = 2.7 V,
IO = 0,
VI = VCC or GND
2.3
4.5
4.5
0.04
0.1
0.1
Outputs high
Outputs low
Outputs disabled
Ci
VCC = 2.5 V,
VI = 2.5 V or 0
Co
VCC = 2.5 V,
VO = 2.5 V or 0
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
6
V
0.5
VCC = 2.7 V,
II
V
V
IOH = –8 mA
IOL = 24 mA
Control inputs
UNIT
VCC – 0.2
1.8
IOL = 6 mA
VCC = 2.3 V
MIN TYP (2) MAX
VCC – 0.2
VCC = 2.3 V to 2.7 V, IOL = 100 µA
VOL
SN74ALVTH16374
MAX
mA
3.5
pF
6
pF
Product preview
All typical values are at VCC = 2.5 V, TA = 25°C.
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND
and then raising it to VIL max.
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to
VCC and then lowering it to VIH min.
An external driver must source at least IBHLO to switch this node from low to high.
An external driver must sink at least IBHHO to switch this node from high to low.
Current into an output in the high state when VO > VCC
High-impedance state during power up or power down
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SN54ALVTH16374,, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
www.ti.com
SCES068G – JUNE 1996 – REVISED NOVEMBER 2006
Electrical Characteristics
over recommended operating free-air temperature range VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
SN54ALVTH16374 (1)
MIN TYP (2)
VCC = 3 V,
II = –18 mA
VCC = 3 V to 3.6 V,
IOH = –100 µA
VCC – 0.2
IOH = –24 mA
2
VCC = 3 V
VCC = 3 V to 3.6 V,
SN74ALVTH16374
MAX
MIN TYP (2)
–1.2
–1.2
2
IOL = 100 µA
0.2
0.2
0.4
0.5
IOL = 32 mA
0.5
IOL = 48 mA
0.55
VCC = 3.6 V, VI = VCC or GND
±1
±1
VCC = 0 or 3.6 V, VI = 5.5 V
10
10
10
10
1
1
II
VI = 5.5 V
Data inputs
VCC = 3.6 V
VI = VCC
VI = 0
Ioff
VCC = 0, VI or VO = 0 to 4.5 V
IBHL (3)
VCC = 3 V,
VI = 0.8 V
(4)
V
0.55
IOL = 64 mA
Control inputs
V
V
IOH = –32 mA
IOL = 24 mA
VCC = 3 V
UNIT
VCC – 0.2
IOL = 16 mA
VOL
MAX
–5
µA
–5
±100
µA
75
75
µA
VCC = 3 V,
VI = 2 V
–75
–75
µA
IBHLO (5)
VCC = 3.6 V,
VI = 0 to VCC
500
500
µA
IBHHO (6)
VCC = 3.6 V,
VI = 0 to VCC
–500
–500
IEX (7)
VCC = 3 V,
VO = 5.5 V
125
125
µA
IOZ(PU/PD) (8)
VCC ≤ 1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE = don’t care
±100
±100
µA
IOZH
VCC = 3.6 V, VO = 3 V,
VI = 0.8 V or 27 V
5
5
µA
IOZL
VCC = 3.6 V, VO = 0.5 V,
VI = 0.8 V or 2 V
–5
–5
µA
ICC
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
IBHH
Outputs high
Outputs disabled
VCC = 3 V to 3.6 V,
One input at VCC– 0.6 V,
Other inputs at VCC or GND
Ci
VCC = 3.3 V,
VI = 3.3 V or 0
Co
VCC = 3.3 V,
VO = 3.3 V or 0
(4)
(5)
(6)
(7)
(8)
(9)
0.1
0.07
3.2
5
3.2
0.07
0.1
0.1
0.4
0.4
Outputs low
∆ICC (9)
(1)
(2)
(3)
0.07
µA
0.1
5
mA
mA
3.5
3.5
pF
6
6
pF
Product preview
All typical values are at VCC = 2.5 V, TA = 25°C.
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND
and then raising it to VIL max.
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to
VCC and then lowering it to VIH min.
An external driver must source at least IBHLO to switch this node from low to high.
An external driver must sink at least IBHHO to switch this node from high to low.
Current into an output in the high state when VO > VCC
High-impedance state during power up or power down
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
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SN54ALVTH16374,, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
www.ti.com
SCES068G – JUNE 1996 – REVISED NOVEMBER 2006
Timing Requirements
over recommended operating free-air temperature range VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
SN54ALVTH16374 (1)
MIN
fclock
Clock frequency
tw
Pulse duration, CLK high or low
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
(1)
MAX
SN74ALVTH16374
MIN
150
MAX
UNIT
150
1.5
1.5
Data high
1.1
1
Data low
1.4
1.3
Data high
0.6
0.5
Data low
0.9
0.8
MHz
ns
ns
ns
Product preview
Timing Requirements
over recommended operating free-air temperature range VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
SN54ALVTH16374 (1)
MIN
fclock
Clock frequency
tw
Pulse duration, CLK high or low
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
(1)
8
MAX
SN74ALVTH16374
MIN
25
250
1.5
1.5
Data high
1.1
1
Data low
1.6
1.5
Data high
0.6
0.5
Data low
1.1
1
Product preview
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MAX
UNIT
MHz
ns
ns
ns
SN54ALVTH16374,, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
www.ti.com
SCES068G – JUNE 1996 – REVISED NOVEMBER 2006
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see
Figure 1)
PARAMETER
TO
(OUTPUT)
SN54ALVTH16374 (1)
MIN
SN74ALVTH16374
MAX
MIN
MAX
fmax
150
tPLH
1.4
3.9
1.5
3.8
1.4
3.9
1.5
3.8
1
4.2
1
4.1
1
3.8
1
3.7
1.7
4.3
1.8
4.2
1
3.5
1
3.4
tPHL
tPZH
tPZL
tPHZ
tPLZ
(1)
FROM
(INPUT)
CLK
Q
OE
Q
OE
Q
150
UNIT
MHz
ns
ns
ns
Product preview
Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see
Figure 2)
PARAMETER
TO
(OUTPUT)
SN54ALVTH16374 (1)
MIN
MAX
SN74ALVTH16374
MIN
MAX
fmax
250
tPLH
1
3.4
1
3.2
1
3.3
1
3.2
1
3.9
1
3.8
1
3.4
1
3.3
1
4.7
1
4.6
1
4.4
1
4.2
tPHL
tPZH
tPZL
tPHZ
tPLZ
(1)
FROM
(INPUT)
CLK
Q
OE
Q
OE
Q
250
UNIT
MHz
ns
ns
ns
Product preview
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SN54ALVTH16374,, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
www.ti.com
SCES068G – JUNE 1996 – REVISED NOVEMBER 2006
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 x VCC
500 W
From Output
Under Test
S1
TEST
Open
GND
CL = 30 pF
(see Note A)
S1
Open
2 x VCC
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 W
GND
tW
LOAD CIRCUIT
VCC
VCC
Timing
Input
Input
VCC/2
VCC/2
VCC/2
0V
tsu
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
0V
tPZL
VCC
VCC/2
Input
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPZH
VOH
Output
tPLZ
Output
Waveform 1
S1 at 2 x VCC
(see Note B)
tPHL
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH – 0.15 V VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, tr ≤ 2 ns,
tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
10
Submit Documentation Feedback
SN54ALVTH16374,, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
www.ti.com
SCES068G – JUNE 1996 – REVISED NOVEMBER 2006
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ±0.3 V
6V
500 W
From Output
Under Test
S1
TEST
Open
GND
CL = 50 pF
(see Note A)
S1
Open
6V
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 W
GND
tW
LOAD CIRCUIT
3V
3V
Timing
Input
Input
1.5 V
1.5 V
1.5 V
0V
tsu
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
3V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
3V
1.5 V
0V
tPZL
Input
3V
1.5 V
1.5 V
0V
tPLH
1.5 V
3V
1.5 V
tPZH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
VOH
Output
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, tr ≤ 2.5 ns,
tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
Submit Documentation Feedback
11
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74ALVTH16374DLG4
ACTIVE
SSOP
DL
48
74ALVTH16374DLRG4
ACTIVE
SSOP
DL
74ALVTH16374GRE4
ACTIVE
TSSOP
74ALVTH16374GRG4
ACTIVE
74ALVTH16374VRE4
25
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74ALVTH16374VRG4
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74ALVTH16374ZQLR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQL
56
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
SN74ALVTH16374DL
ACTIVE
SSOP
DL
48
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALVTH16374DLR
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALVTH16374GR
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALVTH16374KR
NRND
BGA MI
CROSTA
R JUNI
OR
GQL
56
1000
SNPB
Level-1-240C-UNLIM
SN74ALVTH16374VR
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
25
TBD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
74ALVTH16374ZQLR
Package Package Pins
Type Drawing
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ZQL
56
1000
330.0
16.4
4.8
7.3
1.45
8.0
16.0
Q1
SSOP
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
SN74ALVTH16374GR
TSSOP
DGG
48
2000
330.0
24.4
8.6
15.8
1.8
12.0
24.0
Q1
SN74ALVTH16374KR
BGA MI
CROSTA
R JUNI
OR
GQL
56
1000
330.0
16.4
4.8
7.3
1.45
8.0
16.0
Q1
SN74ALVTH16374VR
TVSOP
DGV
48
2000
330.0
24.4
6.8
10.1
1.6
12.0
24.0
Q1
SN74ALVTH16374DLR
BGA MI
CROSTA
R JUNI
OR
SPQ
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74ALVTH16374ZQLR
BGA MICROSTAR
JUNIOR
ZQL
56
1000
346.0
346.0
33.0
SN74ALVTH16374DLR
SSOP
DL
48
1000
346.0
346.0
49.0
SN74ALVTH16374GR
TSSOP
DGG
48
2000
346.0
346.0
41.0
SN74ALVTH16374KR
BGA MICROSTAR
JUNIOR
GQL
56
1000
346.0
346.0
33.0
SN74ALVTH16374VR
TVSOP
DGV
48
2000
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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