TI SN74LVTH16543-EP

SN74LVTH16543-EP
3.3-V ABT 16-BIT REGISTERED TRANSCEIVER
3-STATE OUTPUTS
www.ti.com
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(1)
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Member of the Texas Instruments Widebus™
Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V Operation
and Low Static-Power Dissipation
Supports Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
Supports Unregulated Battery Operation
Down to 2.7 V
Ioff and Power-Up 3-State Support Hot
Insertion
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
SCBS785B – NOVEMBER 2003 – REVISED JUNE 2006
DGG OR DL PACKAGE
(TOP VIEW)
1OEAB
1LEAB
1CEAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2CEAB
2LEAB
2OEAB
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2CEBA
2LEBA
2OEBA
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION/ORDERING INFORMATION
The SN74LVTH16543 is a 16-bit registered transceiver designed for low-voltage (3.3-V) VCC operation, but with
the capability to provide a TTL interface to a 5-V system environment. This device can be used as two 8-bit
transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or
OEBA) inputs are provided for each register to permit independent control in either direction of data flow.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2006, Texas Instruments Incorporated
SN74LVTH16543-EP
3.3-V ABT 16-BIT REGISTERED TRANSCEIVER
3-STATE OUTPUTS
www.ti.com
SCBS785B – NOVEMBER 2003 – REVISED JUNE 2006
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data
present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and
OEBA inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
ORDERING INFORMATION
PACKAGE (1)
TA
ORDERABLE PART NUMBER
TSSOP – DGG
Tape and reel
CLVTH16543IDGGREP
LH16543EP
–55°C to 125°C
SSOP – DL
Tape and reel
CLVTH16543MDLREP
LH16543MEP
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE (1)
(each 8-bit section)
INPUTS
(1)
(2)
2
TOP-SIDE MARKING
–40°C to 85°C
CEAB
LEAB
OEAB
A
OUTPUT
B
H
X
X
X
Z
X
X
H
X
Z
L
H
L
X
B0 (2)
L
L
L
L
L
L
L
L
H
H
A-to-B data flow is shown; B-to-A flow control is the same, except
that it uses CEBA, LEBA, and OEBA.
Output level before the indicated steady-state input conditions were
established
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SN74LVTH16543-EP
3.3-V ABT 16-BIT REGISTERED TRANSCEIVER
3-STATE OUTPUTS
www.ti.com
SCBS785B – NOVEMBER 2003 – REVISED JUNE 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A1
56
54
55
1
3
2
C1
5
1D
52
1B1
C1
1D
To Seven Other Channels
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2A1
29
31
30
28
26
27
C1
15
1D
42
2B1
C1
1D
To Seven Other Channels
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SN74LVTH16543-EP
3.3-V ABT 16-BIT REGISTERED TRANSCEIVER
3-STATE OUTPUTS
www.ti.com
SCBS785B – NOVEMBER 2003 – REVISED JUNE 2006
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
7
V
–0.5
7
V
–0.5
VCC + 0.5
state (2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Voltage range applied to any output in the high state (2)
IO
Current into any output in the low state
IO
Current into any output in the high state (3)
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
–50
mA
θJA
Package thermal impedance (4)
Tstg
Storage temperature range (5)
(1)
(2)
(3)
(4)
(5)
DGG package
V
128
mA
64
mA
–50
mA
81
DL package
°C/W
73.5
–65
°C
150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This current flows only when the output is in the high state and VO > VCC.
The package thermal impedance is calculated in accordance with JESD 51.
Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
Recommended Operating Conditions (1)
MAX
2.7
3.6
UNIT
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
VI
Input voltage
5.5
V
IOH
High-level output current
–32
mA
IOL
Low-level output current
64
mA
∆t/∆v
Input transition rise or fall rate
10
ns/V
∆t/∆VCC
Power-up ramp rate
TA
(1)
4
MIN
VCC
2
Outputs enabled
V
V
µs/V
200
Operating free-air temperature
V
I temp
–40
85
M temp
–55
125
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74LVTH16543-EP
3.3-V ABT 16-BIT REGISTERED TRANSCEIVER
3-STATE OUTPUTS
www.ti.com
SCBS785B – NOVEMBER 2003 – REVISED JUNE 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 2.7 V,
II = –18 mA
VCC = 2.7 V to 3.6 V,
IOH = –100 µA
VCC = 2.7 V,
IOH = –8 mA
VCC = 3 V,
IOH = –32 mA
VCC = 2.7 V
VOL
VCC = 3 V
MIN TYP (1)
2.4
V
2
IOL = 100 µA
0.2
IOL = 24 mA
0.5
IOL = 16 mA
0.4
IOL = 32 mA
0.5
±1
VCC = 0 or 3.6 V,
VI = 5.5 V
10
VI = 5.5 V (I temp)
20
VI = 5.5 V (M temp)
100
VCC = 3.6 V
VI = VCC
VCC = 0
II(hold)
A or B port
1
±100
VI or VO = 0 to 4.5 V (M temp)
±550
VI = 2 V
VCC = 3.6 V, (3)
µA
–5
VI or VO = 0 to 4.5 V (I temp)
VI = 0.8 V
VCC = 3 V
V
0.55
VI = VCC or GND
VI = 0
Ioff
V
VCC = 3.6 V,
II
A or B port (2)
UNIT
–1.2
VCC – 0.2
IOL = 64 mA (I temp)
Control
inputs
MAX
µA
75
µA
–75
±500
VI = 0 to 3.6 V
IOZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care
±100
µA
IOZPD
VCC = 1.5 to 0 V, VO = 0.5 V to 3 V, OE = don't care
±100
µA
ICC (4)
VCC = 3.6 V, IO = 0, VI = VCC or GND
Outputs high
0.19
Outputs low
5
Outputs disabled
mA
0.19
∆ICC
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = 3 V or 0
4
pF
Cio
VO = 3 V or 0
10
pF
(1)
(2)
(3)
(4)
0.2
mA
All typical values are at VCC = 3.3 V, TA = 25°C.
Unused pins at VCC or GND
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
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SN74LVTH16543-EP
3.3-V ABT 16-BIT REGISTERED TRANSCEIVER
3-STATE OUTPUTS
www.ti.com
SCBS785B – NOVEMBER 2003 – REVISED JUNE 2006
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
M TEMP
VCC = 3.3 V
± 0.3 V
MIN MAX
tw
Pulse duration, LEAB or LEBA low
A or B before LEAB↑ OR LEBA↑
tsu Setup time
A or B before CEAB↑ or CEBA↑
A or B before LEAB↑ OR LEBA↑
th
Hold time
A or B before CEAB↑ or CEBA↑
I TEMP
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN MAX
VCC = 2.7 V UNIT
MIN MAX
MIN MAX
3.3
3.3
3.3
3.3
Data high
0.7
0.9
0.5
0.5
Data low
1.2
1.9
0.8
1.3
Data high
0.5
0.8
0
0
Data low
1.1
1.9
0.6
1.1
Data high
1.5
1.0
1.5
0.7
Data low
1.2
1.5
1.2
1.3
Data high
1.7
1.1
1.7
0.9
Data low
1.6
1.9
1.6
1.8
ns
ns
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
M TEMP
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
(1)
6
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
LE
A or B
OE
A or B
OE
A or B
CE
A or B
CE
A or B
VCC = 3.3 V
± 0.3 V
I TEMP
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
MAX
MAX
MIN
TYP (1)
1.2
4.7
6.5
1.2
2.3
3.2
3.7
1.2
5.4
6.5
1.2
2.1
3.2
3.7
1.3
7.3
7.8
1.3
2.5
3.9
4.9
1.3
6.9
7.8
1.3
2.3
3.9
4.9
1.3
6.5
7.4
1.3
2.8
4.3
5.4
1.3
6.7
7.4
1.3
2.8
4.3
5.4
2
5.7
7.2
2
3.5
4.7
5.2
2
5.1
6.9
2
3.3
4.4
4.5
1.3
6.5
7.6
1.3
3
4.5
5.6
1.3
6.4
7.6
1.3
3
4.5
5.6
2
5.3
7.4
2
3.6
4.9
5.4
2
5.1
6.9
2
3.5
4.7
4.9
MIN
All typical values are at VCC = 3.3 V, TA = 25°C.
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MAX
MIN
UNIT
MAX
ns
ns
ns
ns
ns
ns
SN74LVTH16543-EP
3.3-V ABT 16-BIT REGISTERED TRANSCEIVER
3-STATE OUTPUTS
www.ti.com
SCBS785B – NOVEMBER 2003 – REVISED JUNE 2006
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
6V
Open
S1
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
Timing Input
LOAD CIRCUIT
1.5 V
0V
tw
tsu
2.7 V
Input
1.5 V
1.5 V
th
2.7 V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
VOH
1.5 V
Output
1.5 V
VOL
tPHL
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLH
1.5 V
1.5 V
1.5 V
VOL
tPZL
tPLZ
3V
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPZH
VOH
Output
2.7 V
Output
Control
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CLVTH16543IDGGREP
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CLVTH16543MDLREP
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/04715-01XE
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/04715-02YE
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVTH16543-EP :
• Catalog: SN74LVTH16543
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CLVTH16543IDGGREP
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
CLVTH16543MDLREP
SSOP
DL
56
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CLVTH16543IDGGREP
TSSOP
DGG
56
2000
346.0
346.0
41.0
CLVTH16543MDLREP
SSOP
DL
56
1000
346.0
346.0
49.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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