LTC1698 Isolated Secondary Synchronous Rectifier Controller U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC ®1698 is a precision secondary-side forward converter controller that synchronously drives external N-channel MOSFETs. It is designed for use with the LT®3781 primary-side synchronous forward converter controller to create a completely isolated power supply. The LT3781 synchronizes the LTC1698 through a small pulse transformer and the LTC1698 drives a feedback optocoupler to close the feedback loop. Output accuracy of ±0.8% and high efficiency over a wide range of load currents are obtained. High Efficiency Over Wide Load Current Range ±0.8% Output Voltage Accuracy Dual N-Channel MOSFET Synchronous Drivers Pulse Transformer Synchronization Optocoupler Feedback Driver Programmable Current Limit Protection ±5% Margin Output Voltage Adjustment Adjustable Overvoltage Fault Protection Power Good Flag Auxiliary 3.3V Logic Supply Available in 16-Lead SSOP and SO Packages The LTC1698 provides accurate secondary-side current limit using an external current sense resistor. The input voltage at the MARGIN pin provides ±5% output voltage adjustment. A power good flag and overvoltage input are provided to ensure proper power supply conditions. An auxiliary 3.3V logic supply is included that supplies up to 10mA of output current. U APPLICATIO S ■ ■ ■ ■ 48V Input Isolated DC/DC Converters Isolated Telecommunication Power Systems Distributed Power Step-Down Converters Industrial Control Systems Automotive and Heavy Equipment , LTC and LT are registered trademarks of Linear Technology Corporation. U ■ TYPICAL APPLICATIO L1 VIN 36V to 72V VOUT + Q1 1 T1 2 Q4 Q2 R1 + • • D1 VDD BIAS COUT 16 Q3 D2 12 RPRISEN VDD CG FG 10 CSG LTC1698 15 • SG T2 CC CFB ISNS VCOMP ISNSGND ICOMP SYNC OVPIN 6 13 CCILM RCILM 9 R4 RSYNC MARGIN LT3781 RK + – CK VC R5 • TG BG CSYNC RC PWRGD 8 VFB RSECSEN 11 R2 REF VFB 5 OPTODRV PGND 3 VAUX GND 4 7 VMARGIN 14 O.1µF VAUX 3.3V 10mA 1681 F01 RE RF CF ISOLATION BOUNDARY PLEASE REFER TO FIGURE 12 IN THE TYPICAL APPLICATIONS SECTION FOR THE COMPLETE 3.3V/15A APPLICATION SCHEMATIC Figure 1. Simplified 2-Transistor Isolated Forward Converter 1698f 1 LTC1698 W U U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION (Note 1) VDD, PWRGD ....................................................... 13.2V Input Voltage MARGIN, VFB, OVPIN, ISNSGND, ISNS ... – 0.3V to 5.3V SYNC ..................................................... – 14V to 14V Output Voltage VCOMP, ICOMP (Note 2) ......................... – 0.3V to 5.3V Power Dissipation .............................................. 500mW Operating Temperature Range LTC1698E (Note 3) ............................ – 40°C to 85°C LTC1698I ........................................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW VDD 1 16 FG CG 2 15 SYNC PGND 3 14 VAUX GND 4 13 ICOMP OPTODRV 5 12 ISNS VCOMP 6 11 ISNSGND MARGIN 7 10 PWRGD VFB 8 9 LTC1698EGN LTC1698ES LTC1698IGN LTC1698IS GN PART MARKING OVPIN 1698 1698I GN PACKAGE S PACKAGE 16-LEAD PLASTIC SSOP 16-LEAD PLASTIC SO TJMAX = 125°C, θJA = 130°C/W (GN) TJMAX = 125°C, θJA = 110°C/W (SO) Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 8V, unless otherwise noted. (Note 4) SYMBOL PARAMETER VDD Supply Voltage VUVLO Undervoltage Lockout IVDD VDD Supply Current CONDITIONS ● MIN TYP MAX UNITS 6 8 12.6 V 4 VFB, OVPIN, VISNS, VISNSGND = 0V, CFG = CCG = 1000pF, CVAUX = 0.1µF, VSYNC = 0V 1.8 ● fSYNC = 100kHz (Note 5) V 4 5.0 mA mA MARGIN and Error Amplifier VFB Feedback Voltage MARGIN = Open, VCOMP = 1V (Note 7) ● 1.223 1.215 1.233 1.233 1.243 1.251 V V 0.05 1 µA IVFB Feedback Input Current VFB = 1.233V VMARGIN MARGIN Voltage MARGIN = Open RMARGIN MARGIN Input Resistance ∆VFB Feedback Voltage Adjustment VMARGIN = 3.3V VMARGIN = 0V ● ● 4 –6 5 –5 GERR Error Amplifier Open-Loop DC Gain VCOMP = 0.8V to 1.2V, Load = 2kΩ, 100pF ● 65 90 dB BWERR Error Amplifier Unity-Gain Bandwidth No Load (Note 6) 2 MHz VCLAMP Error Amplifier Output Clamp Voltage VFB = 0V 2 V IVCOMP Error Amplifier Source Current Error Amplifier Sink Current VFB = 0V VFB = 5V, VCOMP = 1.233V ● ● – 25 7 – 10 3 mA mA GOPTO Opto Driver DC Gain OVPIN, VISNS, VISNSGND = 0V ● 4.75 5 5.25 V/V BWOPTO Opto Driver Unity-Gain Bandwidth No Load (Note 6) VOPTOHIGH Opto Driver Output High Voltage VFB, OVPIN, VISNSGND = 0V, VISNS = – 50mV, IOPTODRV = –10mA ● 4 5 IOPTOSC Opto Driver Output Short-Circuit Current OVPIN, VISNSGND, VISNS = 0V, VFB = 1.233V ● – 50 – 25 ● 1.65 V 16.5 kΩ 6 –4 % % OPTODRV 1 MHz V – 10 mA 1698f 2 LTC1698 ELECTRICAL CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 8V, unless otherwise noted. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 3.135 3.320 3.465 V 0.05 0.05 1 1 µA µA VAUX VAUX Auxiliary Supply Voltage CVAUX = 0.1µF, ILOAD = 0mA to 10mA, VDD = 7V to 12.6V ● IISNSGND ISNSGND Input Current IISNS ISNS Input Current VILIMTH Current Limit Threshold (VISNS – VISNSGND) VISNSGND = 0V VISNS = 0V ● IICOMP VISNSGND = 0V, VISNS = – 0.3V, VICOMP = 2.5V (Note 8) Current Limit Amplifier ICOMP Source Current ICOMP Sink Current ● VICOMP = 2.5V, VISNSGND = 0V ● – 27.0 – 27.5 – 25 – 25 – 23.0 – 22.5 mV mV ● – 280 – 370 – 200 – 200 – 120 – 80 µA µA ● 120 80 200 200 280 370 µA µA 5 VISNSGND = 0V, VISNS = 0.3V, VICOMP = 2.5V (Note 8) gmILIM Current Limit Amplifier Transconductance VISNSGND = 0V, VICOMP = 2.5V, IICOMP = ±10µA ● 2.2 3.5 GICOMP Current Limit Amplifier Open-Loop DC Gain VICOMP = 2.5V, No Load ● 48 60 VFB ↓, MARGIN = Open (Note 9) VFB = 2V VFB = 0V ● –9 –6 ● ● –3 10 10 0.4 V 1.18 1.233 0.1 1.28 1 V µA 1 0.5 2 1 5 2.5 ms ms 5 20 µs V millimho dB PWRGD and OVP Comparators VPWRGD IPWRGD VOL Percent Below VFB Power Good Sink Current IPWRGD = 3mA, VFB = 0V ● VOVPREF OVPIN Threshold IOVPIN OVPIN Input Bias Current Power Good Output Low Voltage VFB = VISNS = VISNSGND = 0V, OVPIN ↑ (Note 9) VOVPIN = 1.233V ● tPWRGD Power Good Response Time Power Bad Response Time VFB ↑ VFB ↓ ● ● tOVP Overvoltage Response Time VOVPIN ↑, COPTODRV = 0.1µF ● SYNC and Drivers VPT SYNC Input Positive Threshold ● ● 1 1.6 2.2 ● – 2.2 –1.6 –1 V 1 50 µA 400 kHz 90 ns VNT SYNC Input Negative Threshold ISYNC SYNC Input Current VSYNC = ±10V ● fSYNC SYNC Frequency Range CFG = CCG = 1000pF, VSYNC = ±5V ● td SYNC Input to Driver Output Delay CFG = CCG = 1000pF, fSYNC = 100kHz, VSYNC = ±5V ● tSYNC Minimum SYNC Pulse Width fSYNC = 100kHz, VSYNC = ±10V (Note 6) ● tr, tf Driver Rise and Fall Time CFG = CCG = 1000pF, fSYNC = 100kHz, VSYNC = ±5V, 10% to 90% ● tDDIS Driver Disable Time-Out CFG = CCG = 1000pF, fSYNC = 100kHz, VSYNC = ±5V Measured from CG ↑ (Note 10) Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. All voltages refer to GND. Note 2: The LTC1698 incorporates a 5V linear regulator to power internal circuitry. Driving these pins above 5.3V may cause excessive current flow. Guaranteed by design and not subject to test. Note 3: The LTC1698E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. For guaranteed performance to specifications over the –40°C to 85°C range, the LTC1698I is available. Note 4: All currents into device pins are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise specified. For applications with VDD < 7V, refer to the Typical Performance Characteristics. % µA mA ● 50 40 75 10 ns 10 40 ns 15 20 µs Note 5: Supply current in active operation is dominated by the current needed to charge and discharge the external FET gates. This will vary with the LTC1698 operating frequency, supply voltage and the external FETs used. Note 6: This parameter is guaranteed by correlation and is not tested. Note 7: VFB is tested in an op amp feedback loop which servos VFB to the internal bandgap voltage. Note 8: The current comparator output current varies linearly with temperature. Note 9: The PWRGD and OVP comparators incorporate 10mV of hysteresis. Note 10: The driver disable time-out is proportional to the SYNC period within the frequency synchronization range. 1698f 3 LTC1698 U W TYPICAL PERFOR A CE CHARACTERISTICS VFB vs VDD VFB vs Temperature 1.248 1.248 VDD = 8V VFB vs VMARGIN 1.295 TA = 25°C 1.282 1.242 1.242 1.230 1.230 1.224 1.224 1.218 –50 –25 1.218 0 6 5 25 50 75 100 125 150 TEMPERATURE (°C) 7 8 9 10 VDD (V) 11 12 ISNS Threshold vs Temperature –22.5 VDD = 8V 0 1.221 –1 1.208 –2 1.196 –3 1.184 –4 13 1.171 14 0 0.33 0.66 0.99 1.32 1.65 1.98 2.31 2.64 2.97 3.3 VMARGIN (V) –5 1698 G03 Current Limit Amplifier gm vs Temperature 5.0 TA = 25°C –23.0 VDD = 8V 4.6 ISNS THRESHOLD (mV) ISNS THRESHOLD (mV) –23.5 –24.0 –24.0 –24.5 –24.5 –25.0 –25.0 –25.5 –25.5 –26.0 –26.0 –26.5 –26.5 –27.0 –27.0 –27.5 –50 –25 0 5 6 7 8 9 10 VDD (V) 11 12 1.28 POWER GOOD THRESHOLD (V) OVPIN THRESHOLD (V) 25 50 75 100 125 150 TEMPERATURE (°C) 1698 G07 25 50 75 100 125 150 TEMPERATURE (°C) 1.22 5 6 7 8 9 10 VDD (V) 11 12 13 14 1698 G08 –3.0 VDD = 8V 1.181 –4.2 1.166 –5.4 1.152 –6.6 1.137 –7.8 1.122 –50 –25 0 ∆VFB (%) 1.24 1.18 0 0 1698 G06 1.196 TA = 25°C 1.20 1.20 2.2 –50 –25 14 Power Good Threshold vs Temperature 1.26 1.26 1.18 –50 –25 13 OVPIN Threshold vs VDD VDD = 8V 1.22 3.4 1698 G05 OVPIN Threshold vs Temperature 1.24 3.8 2.6 –27.5 25 50 75 100 125 150 TEMPERATURE (°C) 4.2 3.0 1698 G04 OVPIN THRESHOLD (V) 1 1.233 ISNS Threshold vs VDD –23.5 1.28 2 1.245 gmILIM (millimho) –22.5 3 1.258 1698 G02 1698 G01 –23.0 1.270 VFB (V) VFB (V) VFB (V) 1.236 4 ∆VFB (%) 1.236 5 VDD = 8V TA = 25°C –9.0 25 50 75 100 125 150 TEMPERATURE (°C) 1698 G09 1698f 4 LTC1698 U W TYPICAL PERFOR A CE CHARACTERISTICS VAUX vs Temperature VAUX vs Line Voltage 3.465 3.465 3.383 3.383 3.383 3.341 3.341 3.341 VDD = 8V 3.424 ILOAD = 0mA 3.300 VDD = 8V 3.424 TA = 25°C VAUX (V) VAUX (V) VDD = 8V 3.424 ILOAD = 0mA 3.300 3.300 3.259 3.259 3.259 3.218 3.218 3.218 3.176 3.176 3.176 3.135 3.135 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 0 5 6 7 8 9 10 VDD (V) 11 12 VAUX Short-Circuit Current vs Temperature –30 –40 TA = 25°C –10 –20 –30 –40 –50 0 25 50 75 100 125 150 TEMPERATURE (°C) 5 6 1698 G13 MAXIMUM OPTO DRIVER OUTPUT VOLTAGE (V) MAXIMUM OPTO DRIVER OUTPUT VOLTAGE (V) VDD = 8V VDD = 7V 4 VDD = 6V VDD = 5V 2 0 TA = 25°C VCOMP = 0V 0 1 2 3 4 5 6 7 8 LOAD CURRENT (mA) 8 9 10 VDD (V) 11 12 13 14 9 10 1698 G22 0.8 3.018 0.6 3.012 0.4 3.006 0.2 3.000 0 2.994 –0.2 2.988 –0.4 2.982 –0.6 2.976 –0.8 2.970 0 1 2 3 4 5 6 7 8 LOAD CURRENT (mA) 8 6 VDD = 10V VDD = 8V VDD = 7V 4 VDD = 6V VDD = 5V 2 VCOMP = 0V IOPTODRV = –10mA 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1698 G23 9 10 –1.0 1698 G15 Maximum OPTO Driver Output Voltage vs Temperature VDD = 10V 6 7 10 1.0 VDD = 8V TA = 25°C 3.024 1698 G14 Maximum OPTO Driver Output Voltage vs Load Current 8 9 Opto Driver Load Regulation 3.030 OPTO DRIVER OUTPUT VOLTAGE (V) VAUX SHORT-CIRCUIT CURRENT (mA) –20 3 4 5 6 7 8 LOAD CURRENT (mA) 2 PERCENT (%) VAUX SHORT-CIRCUIT CURRENT (mA) 0 –10 1 0 1698 G12 VAUX Short-Circuit Current vs VDD VDD = 8V –50 –50 –25 3.135 14 1698 G11 1698 G10 0 13 Opto Driver Short-Circuit Current vs Temperature OPTO DRIVER SHORT-CIRCUIT CURRENT (mA) VAUX (V) VAUX vs Load Current 3.465 –10 VDD = 8V –15 VOPTODRV = 1.233V –20 –25 –30 –35 –40 –45 –50 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1698 G16 1698f 5 LTC1698 U W TYPICAL PERFOR A CE CHARACTERISTICS SYNC Positive Threshold vs Temperature IVDD vs SYNC Frequency CFG = CCG = 4700pF CFG = CCG = 3300pF 35 CFG = CCG = 2200pF 30 25 20 15 10 CFG = CCG = 1000pF 5 0 2.00 1.75 1.50 1.25 0 –30 CFG = CCG = 2200pF 0 14 6 5 7 8 9 10 VDD (V) 11 Driver Rise, Fall and Propagation Delay vs Driver Load 90 70 80 70 CG, FG tPLH 12 13 tf 40 CG, FG tPHL tr 30 50 CG, FG tPLH CG, FG tPHL 40 30 20 20 10 10 0 0 2000 6000 4000 DRIVER LOAD (pF) 8000 10000 1698 G25 0 –50 –25 14 0 25 50 75 100 125 150 TEMPERATURE (°C) 1698 G24 0 –50 –25 0 Driver Disable Time-Out vs SYNC Frequency 30 VDD = 8V CCG = CFG = 1000pF fSYNC = 100kHz 60 t d (ns) TIME (ns) 60 50 2 25 50 75 100 125 150 TEMPERATURE (°C) 1698 G26 2.2 VDD = 8V TA = 25°C 2.0 25 20 tDISS × fSYNC 1.8 1.6 15 1.4 10 tDISS 5 1.2 0 1.0 50 100 150 200 250 300 350 400 450 500 fSYNC (kHz) NORMALIZED DRIVER DISABLE TIME-OUT tDISS × fSYNC 80 14 1 SYNC Input to Driver Output Delay vs Temperature VDD = 8V TA = 25°C 13 3 1698 G18 1698 G17 90 12 CFG = CCG = 1000pF DRIVER DISABLE TIME-OUT tDISS (µs) 13 11 4 8 2 –50 12 9 10 VDD (V) CFG = CCG = 4700pF 10 4 –40 11 8 7 Undervoltage Lockout Threshold vs Temperature 12 6 10 VDD (V) 6 1698 G21 VUVLO (V) –20 9 5 CFG = CCG = 3300pF 14 IVDD (mA) OPTO DRIVER SHORT-CIRCUIT CURRENT (mA) TA = 25°C fSYNC = 100kHz 18 16 8 1.24 5 20 –10 7 1.48 IVDD vs VDD TA = 25°C VOPTODRV = 1.233V 6 1.72 1698 G20 Opto Driver Short-Circuit Current vs VDD 5 1.96 25 50 75 100 125 150 TEMPERATURE (°C) 1698 G19 0 TA = 25°C 1.00 1.00 –50 –25 50 100 150 200 250 300 350 400 450 500 fSYNC (kHz) 2.20 VDD = 8V SYNC POSITIVE THRESHOLD (V) 40 IVDD (mA) 2.25 VDD = 8V TA = 25°C 45 SYNC POSITIVE THRESHOLD (V) 50 SYNC Positive Threshold vs VDD 1698 G27 1698f 6 LTC1698 U U U PI FU CTIO S VDD (Pin 1): Power Supply Input. For isolated applications, a simple rectifier from the power transformer is used to power the chip. This pin powers the opto driver, the VAUX supply and the FG and CG drivers. An internal 5V regulator powers the remaining circuitry. VDD requires an external 4.7µF bypass capacitor. CG (Pin 2): Catch Gate Driver. If SYNC slews positive, CG pulls high to drive an external N-channel MOSFET. CG draws power from the VDD pin and swings between VDD and PGND. PGND (Pin 3): Power Ground. Connect PGND to a low impedance ground plane in close proximity to the ground terminal of the external current sensing resistor. GND (Pin 4): Logic and Signal Ground. GND is referenced to the internal low power circuitry. Careful board layout techniques must be used to prevent corruption of signal ground reference. Connect GND and PGND together directly at the LTC1698. compensates the feedback loop. If VFB goes low, VCOMP pulls high and OPTODRV goes low. OVPIN (Pin 9): Overvoltage Input. OVPIN is a high impedance input to an internal comparator. The threshold of this comparator is set to 1.233V. If the OVPIN potential is higher than the threshold voltage, OPTODRV pulls high immediately. Use an external RC lowpass filter to prevent noisy signals from triggering this comparator. PWRGD (Pin 10): Power Good Output. This is an opendrain output. PWRGD floats if VFB is above 94% of the nominal value for more than 2ms. PWRGD pulls low if VFB is below 94% of the nominal value for more than 1ms. The PWRGD threshold is independent of the MARGIN pin potential. ISNSGND (Pin 11): Current Sense Ground. Connect to the positive side of the sense resistor, normally grounded. ISNS (Pin 12): Current Sense Input. Connect to the negative side of the sense resistor through an external RC lowpass filter. This pin normally sees a negative voltage, which is proportional to the average load current. If current limit is exceeded, OPTODRV pulls high. OPTODRV (Pin 5): Optocoupler Driver Output. This pin drives a ground referenced optocoupler through an external resistor. If VFB is low, OPTODRV pulls low. If VFB is high, OPTODRV pulls high. This optocoupler driver has a DC gain of 5. During overvoltage or overcurrent conditions, OPTODRV pulls high. The output is capable of sourcing 10mA of current and will drive an external 0.1µF capacitive load and is short-circuit protected. ICOMP (Pin 13): Current Amplifier Output. An RC network at this pin compensates the current limit feedback loop. Referencing the RC to VOUT controls output voltage overshoot on start-up. This pin can float if current limit loop compensation is not required. VCOMP (Pin 6): Error Amplifier Output. This error amplifier is able to drive more than 2kΩ and 100pF of load. The internal diode connected from VFB to VCOMP reduces OPTODRV recovery time under start-up conditions. VAUX (Pin 14): Auxiliary 3.3V Logic Supply. This pin requires a 0.1µF or greater bypass capacitor. This auxiliary power supply can power external devices and sources 10mA of current. Internal current limiting is provided. MARGIN (Pin 7): Current Input to Adjust the Output Voltage Linearly. The MARGIN pin connects to an internal 16.5k resistor. The other end of this resistor is regulated to 1.65V. Connecting MARGIN to a 3.3V logic supply sources 100µA of current into the chip and moves the output voltage 5% higher. Connecting MARGIN to 0V sinks 100µA out of the pin and moves the regulated output voltage 5% lower. The MARGIN pin voltage does not affect the PWRGD and OVPIN trip points. SYNC (Pin 15): Drivers Synchronization Input. A negative voltage slew at SYNC forces FG to pull high and CG to pull low. A positive voltage slew at SYNC resets the FG pin and CG pulls high. If SYNC loses its synchronization signal for more than the driver disable time-out interval, both the forward and catch drivers output are forced low. The SYNC circuit accepts pulse and square wave signals. The minimum pulse width is 75ns. The synchronization frequency range is between 50kHz to 400kHz. VFB (Pin 8): Feedback Voltage. VFB senses the regulated output voltage through an external resistor divider. The VFB pin is servoed to the reference voltage of 1.233V under closed-loop conditions. An RC network from VFB to VCOMP FG (Pin 16): Forward Gate Driver. If SYNC slews negative, FG goes high. FG draws power from VDD and swings between VDD and PGND. 1698f 7 LTC1698 W BLOCK DIAGRA 1 VDD 14 15 VAUX AUX GEN VCC GEN FG VCC SYNC CG 7 16 SYNC IN 2 RMARGIN MARGIN I-TO-V CONVERTER BANDGAP ±5% VREF VREF + 5 OPTODRV OPTO – + 20k ERR VFB – 100k VCOMP 10 PWRGD MPWRGD ISNSGND + MILIM ILIM – 25mV – RILIM 3k + ICOMP PWRGD + ROVP 3k VFB ISNS 0.94VREF + 8 6 11 12 13 VREF OVP – OVPIN 9 1698 BD U OPERATIO (Refer to Block Diagram) The LTC1698 is a secondary-side synchronous rectifier controller designed to work with the LT3781 primary-side synchronous controller chip to form an isolated synchronous forward converter. This chip set uses a dual transistor forward topology that is predominantly used in distributed power supply systems where isolated low voltages are needed to power complex electronic equipment. The primary stage is a current mode, fixed frequency forward converter and provides the typical PWM operation. A power transformer is used to provide the functions of input/output isolation and voltage step-down to achieve the required low output voltage. Instead of using typical Schottky diodes, synchronous rectification on the secondary offers isolation with high efficiency. It supplies high power without the need of bulky heat sinks, which is often a problem in any space constrained application. The LTC1698 not only provides synchronous drivers for the external MOSFETs, it comes with other housekeeping functions performed on the secondary side of the power supply, all within a single integrated controller. Figure 1 shows the typical chip-set application. Upon power up, the LTC1698’s VDD input is low, the gate drivers TG and BG are both at the ground potential. The secondary forward and 1698f 8 LTC1698 U OPERATIO (Refer to Block Diagram) catch MOSFETs Q3 and Q4 are off. As soon as transistors Q1 and Q2 turn on, the flux in the power transformer T1 forces the body diodes of Q3 and Q4 to conduct, and the whole circuit starts like a conventional forward converter. At the same time, the LTC1698 VDD potential ramps up quickly through the VDD bias circuitry. Once the VDD voltage exceeds 4.0V, the LTC1698 enables its drivers and enters synchronous operation. forcing the error amplifier reference voltage to move linearly by ±5%. The internal RMARGIN resistor converts the MARGIN voltage to a current and linearly controls the offset of the error amplifier. Connecting the MARGIN pin to 3.3V increases the VFB voltage by 5%, and connecting the MARGIN pin to 0V reduces VFB by 5%. With the MARGIN pin floating, the VFB voltage is regulated to the internal bandgap voltage. The pulse transformer T2 synchronizes the primary and secondary MOSFET drivers. In a typical conversion cycle, the primary MOSFETs Q1 and Q2 turn on simultaneously. SG goes low and generates a negative spike at the LTC1698 SYNC input through the pulse transformer. The LTC1698 forces FG to turn on and CG to turn off. Power is delivered to the load through the transformer T1 and the inductor L1. At the beginning of the next phase in which Q1 and Q2 turn off, SG goes high, SYNC sees a positive spike, the MOSFET Q3 shuts off, Q4 conducts and allows continuous current to flow through the inductor L1. The capacitor COUT filters the switching waveform to provide a steady DC output voltage for the load. The current limit transconductance amplifier ILIM provides the secondary side average current limit function. The average voltage drops across the RSECSEN resistor is sensed and compared to the – 25mV threshold set by the internal ILIM amplifier. Once ILIM detects high output current, the current amplifier output pulls high, overrides the error amplifier, injects more current into the photo diode and forces a lower duty cycle. An RC network connected to the ICOMP pin is used to stabilize the secondary current limit loop. Alternatively, if only overcurrent fault protection is required, ICOMP can float. The LTC1698 error amplifier ERR senses the output voltage through an external resistor divider and regulates the VFB pin potential to the 1.233V internal bandgap voltage. An external RC network across the VFB and VCOMP pins frequency compensates the error amplifier feedback. The opto driver amplifies the voltage difference between the VCOMP pin and the bandgap potential, driving the external optocoupler diode with an inverting gain of 5. The optocoupler feeds the amplified output error signal to the primary controller and closes the forward converter voltage feedback loop. Under start-up conditions, the internal diode across the LTC1698 error amplifier clamps the VCOMP pin. This speeds up the opto driver recovery time by reducing the negative slew rate excursion at the COMP pin. The forward converter output voltage can be easily adjusted. The potential at the MARGIN pin is capable of If under abnormal conditions the feedback path is broken, OVPIN provides another route for overvoltage fault protection. If the voltage at OVPIN is higher than the bandgap voltage, the OVP comparator forces OPTODRV high immediately. A simple external RC filter prevents a momentary overshoot at OVPIN from triggering the OVP comparator. Short OVPIN to ground if this pin is not used. The LTC1698 provides an open-drain PWRGD output. If VFB is less than 94% of its nominal value for more than 1ms, the PWRGD comparator pulls the PWRGD pin low. If VFB is higher than 94% of its nominal value for more than 2ms, the transistor MPWRGD shuts off, and an external resistor pulls the PWRGD pin high. The LTC1698 provides an auxiliary 3.3V logic power supply. This auxiliary power supply is externally compensated with a minimum 0.1µF bypass capacitor. It supplies up to 10mA of current to any external devices. 1698f 9 LTC1698 U W U U APPLICATIO S I FOR ATIO Undervoltage Lockout In UVLO (low VDD voltage) the drivers FG and CG are shut off and the pins OPTODRV, VAUX, PWRGD and ICOMP are forced low. The LTC1698 allows the bandgap and the internal bias currents to reach their steady-state values before releasing UVLO. Typically, this happens when VDD reaches approximately 4.0V. Beyond this threshold, the drivers start switching. The OPTODRV, VAUX, PWRGD and ICOMP pins return to their normal values and the chip is fully functional. However, if the VDD voltage is less than 7V, the OPTODRV and VAUX current sourcing capabilities are limited. See the OPTO driver graphs in the Typical Performance Characteristics section. supply requirement. Under start-up conditions, it must be small enough to power up instantaneously, enabling the LTC1698 to regulate the feedback loop. Using a larger capacitor requires evaluation of the start-up performance. SYNC Input Figure 3 shows the synchronous forward converter application. The primary controller LT3781 runs at a fixed frequency and controls MOSFETs Q1 and Q2. The secondary controller LTC1698 controls MOSFETs Q3 and Q4. An inexpensive, small-size pulse transformer T2 synchronizes the primary and the secondary controllers. Figure 4 shows the pulse transformer timing waveforms. When the LT3781 synchronization output SG goes low, MOSFET VDD Regulator L1 The bias supply for the LTC1698 is generated by peak rectifying the isolated transformer secondary winding. As shown in Figure 2, the zener diode Z1 is connected from base of Q5 to ground such that the emitter of Q5 is regulated to one diode drop below the zener voltage. RZ is selected to bring Z1 into conduction and also provide base current to Q5. A resistor (on the order of a few hundred ohms), in series with the base of Q5, may be required to surpress high frequency oscillations depending on Q5’s selection. A power MOSFET can also be used by increasing the zener diode value to offset the drop of the gate-tosource voltage. VDD supply current varies linearly with the supply voltage, driver load and clock frequency. A 4.7µF bypass capacitor for the VDD supply is sufficient for most applications. This capacitor must be large enough to provide a stable DC voltage to meet the LTC1698 VDD VOUT TG VIN PRIMARY CONTROLLER LT3781 SG BG Q1 D1 Q4 • CG • SECONDARY CONTROLLER LTC1698 T1 D2 Q2 Q3 • CSG T2 COUT FG SYNC 1698 F03 • CSYNC RSYNC PRIMARY SECONDARY ISOLATION BARRIER Figure 3. Synchronization Using Pulse Transformer TG VSECONDARY BG 1Ω SG D3 RZ 2k RB* 0.47µF Z1 10V SYNC Q5 FZT690 VDD FG 4.7µF CG *RB IS OPTIONAL, SEE TEXT 1698 F04 1698 F02 Figure 2. VDD Regulator Figure 4. Primary Side and Secondary Side Synchronization Waveforms 1698f 10 LTC1698 U W U U APPLICATIO S I FOR ATIO drivers TG and BG go high. The pulse transformer T2 generates a negative slew at the SYNC pin and forces the secondary MOSFET driver FG to go high and CG to go low. When TG and BG go low, SG goes high and the secondary controller forces CG high and FG low. For a given pulse transformer, a bigger capacitor CSG generates a higher and wider SYNC pulse. The peak of this pulse should be much higher than the SYNC threshold. Amplitudes greater than ±5V help to speed up the SYNC comparator and reduce the SYNC to FG and CG drivers propagation delay. The minimum pulse width is 75ns. Overshoot during the pulse transformer reset interval must be minimized and kept below the minimum comparator thresholds of ±1V. The amount of overshoot can be reduced by having a smaller reset resistor RSYNC. For nonisolated applications, the SYNC input can be driven directly by a square pulse. To reduce the propagation delay, make the positive and negative magnitude of the square wave much greater than the ±2.2V maximum threshold. In addition to the simple driver synchronization, the secondary controller requires a driver disable signal. Loss of synchronization while CG is high will cause Q4 to discharge the output capacitor. This produces a negative output voltage transient and possible damage to the load circuitry connected to VOUT. To overcome this problem, the LTC1698 comes with a unique adaptive time-out circuit. It works well within the 50kHz to 400kHz frequency range. At every positive SYNC pulse, the internal timer resets. If the SYNC signal is missing, the internal timer loses its reset command, and eventually exceeds the internal time-out limit. This forces both the FG and CG drivers to go low immediately. The time-out duration varies linearly with the LT3781 primary controller clocking frequency. Upon power up, the time-out circuitry takes a few clock cycles to adapt to the input clock frequency. During this time interval, the drivers pulse width might be prematurely terminated, and the inductor current flows through the MOSFETs body diode. Once the LTC1698 timer locks to the clocking frequency, the LTC1698 drivers follow the SYNC signal without fail. Figure 5 shows the SYNC time-out wave- SG SYNC FG CG RESET (INTERNAL) DISDRI (INTERNAL) 1698 F05 Figure 5. SYNC Time-Out Waveforms forms. The time-out circuit guarantees that if the SYNC pulse is missing for more than one period, both the drivers will be shut down preventing the output voltage from going below ground. The wide synchronization frequency range adds flexibility to the forward converter and allows this converter chip set to meet different application requirements. Under normal operating conditions, the time-out circuitry adapts to the switching frequency within a few cycles. Once synchronized, internal circuitry ensures the maximum time that the Catch FET (Q4) could be left turned on is typically just over one switching period. This is particularly important with high output voltages that can generate significant negative output inductor currents if the Catch FET Q4 is left on. Poor feedback loop performance including output voltage overshoot can cause the primary controller to interrupt the synchronization pulse train. While this generally is not a problem, it is possible that low frequency interruptions could lead to a time-out period longer than a switching period, limited only by the internal timer clamp (50µs typical). Output Voltage Programming The switching regulator output voltage is programmed through a resistor feedback network (R1 and R2 in Figure 1) connected to VFB. If the output is at its nominal value, the divider output is regulated to the error amplifier threshold of 1.233V. The output voltage is thus set according to the relation: VOUT = 1.233 • (1 + R2/R1) 1698f 11 LTC1698 U W U U APPLICATIO S I FOR ATIO MARGIN Adjustment The MARGIN input is used for adjusting the programmed output voltage linearly by varying the current flowing into and out of the pin. Forcing 100µA into the pin moves the output voltage 5% higher. Forcing 100µA out of the pin moves the output voltage 5% lower. With the MARGIN pin floating, the VFB pin is regulated to the bandgap voltage of 1.233V. The MARGIN pin is a high impedance input. It is important to keep this pin away from any noise source like the inductor switching node. Any stray signal coupled to the MARGIN pin can affect the switching regulator output voltage. This pin is internally connected to a 16.5k resistor that feeds the I-V converter. The I-V converter output linearly controls the error amplifier offset voltage. The input of the I-V converter is biased at 1.65V. This allows the ±100µA current to be obtained by connecting the MARGIN pin to the VAUX 3.3V supply (+ 5%) or GND (– 5%). For output voltage adjustment smaller than ±5%, an external resistor REXT as shown in Figure 6 is added in series with the internal resistor to lower the current flowing into or out of the MARGIN pin. The value of REXT is calculated as follow: 5% REXT = – 1 • 16.5k REQUIRED % REXT (OPTIONAL) REDUCE VFB INCREASE VFB BANDGAP VOVERVOLTAGE = 1.233 • (1 + R5/R4) The OVP comparator is designed to respond quickly to an overvoltage condition. A small capacitor from OVPIN to ground keeps any noise spikes from coupling to the OVP pin. This simple RC filter prevents a momentary overshoot from triggering the OVP comparator. The OVP comparator threshold is independent of the potential at the MARGIN pin. If the OVP function is not used, connect OVPIN to ground. The PWRGD pin is an open-drain output for power good indication. PWRGD floats if VFB is above 94% of the nominal value for more than 2ms. An external pull-up resistor is required for PWRGD to swing high. PWRGD pulls low if VFB drops below 94% of the nominal value for more than 1ms. The PWRGD threshold is referenced to the 1.233V bandgap voltage, which remains unchanged if the MARGIN pin is exercised. I-V CONVERTER MARGIN The OVPIN senses the output voltage through a resistor divider network (R4 and R5 in Figure 1). The divider is ratioed such that the voltage at OVPIN equals 1.233V when the output voltage rises to the overvoltage level. The overvoltage level is set following the relation: Power Good RMARGIN 7 VFB loop causes the error amplifier to drive the OPTODRV pin low, forcing the primary controller to increase the duty cycle. This causes the output voltage to increase to a dangerously high level. To eliminate this fault condition, the OVP comparator monitors the output voltage with a resistive divider at OVPIN. A voltage at OVPIN higher than the VREF potential forces the OPTODRV pin high and reduces the duty cycle, thus preventing the output voltage from increasing further. VREF ±5% VREF + VDD ERR VAUX 3.3V 14 0.1µF VAUX AUX GEN – VFB VCOMP 8 6 1698 F06 Figure 6. Output Voltage Adjustment Overvoltage Function The OVPIN is used for overvoltage protection and is designed to protect against an open VFB loop. Opening the Opto Feedback and Frequency Compensation For a forward converter to obtain good load and line regulation, the output voltage must be sensed and compared to an accurate reference potential. Any error voltage must be amplified and fed back to the supply’s control circuitry where the sensed error can be corrected. In an isolated supply, the control circuitry is frequently located on the primary. The output error signal in this type of 1698f 12 LTC1698 U W U U APPLICATIO S I FOR ATIO supply must cross the isolation boundary. Coupling this signal requires an element that will withstand the isolation potentials and still transfer the loop error signal. Optocouplers are widely used for this function due to their ability to couple DC signals. To properly apply them, a number of factors must be considered. The gain, or current transfer ratio (CTR) through an optocoupler is loosely specified and is a strong function of the input current through the diode. It changes considerably as a function of time (aging) and temperature. The amount of aging accelerates with higher operating current. This variation directly affects the overall loop gain of the system. To be an effective optical detector, the output transistor of the optocoupler must have a large base area to collect the light energy. This gives it a large collector to base capacitance which can introduce a pole into the feedback loop. This pole varies considerably with the current and interacts with the overall loop frequency compensation network. increases the frequency response. Figure 7 shows the optocoupler feedback circuitry using the common collector approach. Note that the terms RD, CTR, CDE and rπ vary from part to part. They also change with bias current. The dominant pole of the opto feedback is due to RF and CF. The feedforward capacitor CK at the optocoupler creates a low frequency zero. This zero should be chosen to provide a phase boost at the loop crossover frequency. The parallel combination of RK and RD form a high frequency pole with CK. For most optocouplers, RD is 50Ω at a DC bias of 1mA, and 25Ω at a DC bias of 2mA. The CTR term is the small signal AC current transfer ratio. For the QT Optoelectronics MOC207 optocoupler used here, the AC CTR is around 1, even though the DC CTR is much lower when biased at 1mA or 2mA. The first denominator term in the VC/VOUT equation has been simplified and assumes that CFB<<CC. The actual term is: The common collector optocoupler configuration removes the miller effect due to the parasitic capacitance and C •C s • R2 • (C C + C FB )• 1 + s • RC • C FB C C + C FB R • CTR (1 + s • C C • RC ) (1 + s • RK • C K ) 1 1 VC =– •5• • F • • (s • R2 • C C )• (1 + s • RC • C FB ) VOUT RK • RD RD + RK (1 + s • rπ • C DE ) (1 + s • RF • C F ) 1 + • • s C K RK + RD where: RD = Optocoupler diode equivalent small − signal resis tan ce CTR = Optocoupler current transfer ratio C DE = Optocoupler nonlinear capacitor across base to emitter = Optocoupler small − signal resis tan ce across the base emitter rπ LTC1698 + OPTODRV LT3781 VCC + RK – CK + 20k MOC207 VFB – VFB R1 VCOMP CC VC VOUT VREF R2 100k VREF – VREF RC RE CFB RF CF 1698 F07 Figure 7. Error Signal Feedback 1698f 13 LTC1698 U W U U APPLICATIO S I FOR ATIO A series RC network can be added in parallel with R2 (Figure 7) to provide a zero for the feedback loop frequency compensation. The opto driver will drive a capacitive load up to 0.1µF. For optocouplers with a base pin, switching signal noise can get into this high impedance node. Connect a large resistor, 1M or 2M between the base and the emitter. This increases the diode current and the overall feedback bandwidth slightly, and decreases the optocoupler gain. When designing the resistor in series with the optocoupler diode, it is important to consider the part to part variations in the current transfer ratio and its reduction over temperature and aging. The bigger the biasing current, the faster the aging. The LTC1698 opto driver is designed to source up to 10mA of current and swing between 0.4V to (VDD – 2.5V). This should meet the design consideration of most optocouplers. Besides the voltage feedback function, the LTC1698 opto driver couples fault signals to the primary controller and prevents catastrophic damage to the circuit. Upon current limit or an overvoltage fault, the ILIM or OVP comparator overrides the error amplifier output and forces the OPTODRV pin high. This sources maximum current into the external optodiode and reduces the forward converter duty cycle. amplifier ILIM has a – 25mV threshold. As shown in Figure 8, if the secondary current is small, the ICOMP pin goes low and the transistor MILIM shuts off. The potential at VCOMP determines the OPTODRV output. If the secondary current is large, ICOMP pulls high and forces the transistor MILIM to turn on hard. Thus the current limit circuit overrides the voltage feedback and forces OPTODRV high and injects maximum current into the external optocoupler. The RILIM resistor provides a linear relationship between the current sensed and the OPTODRV output. The ISNS and ISNSGND pins allow a true Kelvin current sense measurement and offer true differential measurement across the sense resistor. A differential lowpass filter formed by R6 and C2 removes the pulse-to-pulse inductor current ripple and generates the average secondary current which is equal to the load current. The lowpass corner frequency is typically set to 1 to 2 orders of magnitude below the switching frequency and follows the relationship: 25mV ILMAX 1 R6 = fSW 2 • π • C2 • 10 RSECSEN = where: Average Current Limit The secondary current limit function is implemented by measuring the negative voltage across the current sense resistor RSECSEN. The current limit transconductance RSECSEN = Secondary current sense resistor ILMAX = Maximum allowed secondary current fSW = Forward converter switching frequency DRIVE CG + 5 OPTODRV OPTO – VOUT VREF FG 20k VCOMP 100k 13 ICOMP MILIM + ISNS Q4 16 ISNSGND T1 Q3 R6 12 C2 ILIM RILIM 3k + CCILM 25mV – RCILM 2 RDIV (OPTIONAL) R6 RSECSEN 11 1698 F08 LTC1698 Figure 8. Secondary Average Current Limit 1698f 14 LTC1698 U W U U APPLICATIO S I FOR ATIO If the application generates a bigger current sense voltage, a potential divider can be easily obtained by adding a resistor across C2. With this additional resistor, the voltage sensed by the current comparator becomes: RDIV • VRSENSE RDIV + (2 • R6) An RC network formed by RCILM and CCILM between ICOMP and VOUT can be used to stabilize the current limit loop. Connecting the compensation network to VOUT minimizes output overshoot during start-up or short-circuit recovery. The RCILM and CCILM zero should be chosen to be well within the closed-loop crossover frequency. This pin can be left floating if current loop compensation is not required. The forward converter secondary current limit function can be disabled by shorting ISNS and ISNSGND to ground. Auxiliary 3.3V Logic Power Supply An internal P-channel LDO (low dropout regulator) produces the 3.3V auxiliary supply that can power external devices or drive the MARGIN pin. This supply can source up to 10mA of current and the current limit is provided internally. The pin requires at least a 0.1µF bypass capacitor. MOSFET Selection Two logic-level N-channel power MOSFETs (Q3 and Q4 in Figure 1) are required for most LTC1698 circuits. They are selected based primarily on the on-resistance and body diode considerations. The required MOSFET RDS(ON) should be determined based on input and output voltage, allowable power dissipation and maximum required output current. The average inductor (L1) current is equal to the output load current. This current is always flowing through either Q3 or Q4 with the power dissipation split up according to the duty cycle: VOUT NP • VIN NS V N DC (Q 4) = 1 – OUT • P VIN NS DC (Q 3) = where NP/NS is the turns ratio of the transformer T1. The RDS(ON) required for a given conduction loss can now be calculated by rearranging the relation P = I2R. 2 PMAX(Q3) = IMAX • RDS(ON)Q3 • DC (Q 3) PMAX(Q3) ⇒ RDS(ON)Q3 = 2 IMAX • DC (Q 3) 2 PMAX(Q4) = IMAX • RDS(ON)Q4 • DC (Q 4) ⇒ RDS(ON)Q4 = PMAX(Q4) 2 IMAX • DC (Q 4) where IMAX is the maximum load current and PMAX is the allowable conduction loss. In a typical 2-transistor forward converter circuit, the duty cycle is less than 50% to prevent the transformer core from saturating. This results in the duty cycle of Q4 being greater than that of Q3. Q4 will dissipate more power due to the higher duty cycle. A lower RDS(ON) MOSFET can be used for Q4. This will slow down the turn-on time of Q4 since a lower RDS(ON) MOSFET will have a larger gate capacitance. The next consideration for the MOSFET is the characteristic of the body diode. The body diodes conduct during the power-up phase, when the LTC1698 VDD supply is ramping up and the time-out circuit is adapting to the SYNC input frequency. The CG and FG signals terminate prematurely and the inductor current flows through the body diodes. The body diodes must be able to take the comparable amount of current as the MOSFETs. Most power MOSFETs have the same current rating for the body diode and the MOSFET itself. The LTC1698 CG and FG MOSFET drivers will dissipate power. This will increase with higher switching frequency, higher VDD or larger MOSFETs. To calculate the driver dissipation, the total gate charge Qg is used. This parameter is found on the MOSFET manufacturers data sheet. The power dissipated in each LTC1698 MOSFET driver is: PDRIVER = Qg • VDD • fSW where fSW is the switching frequency of the converter. 1698f 15 LTC1698 U W U U APPLICATIO S I FOR ATIO Power Transformer Selection The forward transformer provides DC isolation and delivers energy from the primary to the secondary. Unlike the flyback topology, the transformer in the forward converter is not an energy storage device. As such, ungapped ferrite material is typically used. Select a power material rated with low loss at the switching frequency. Many core manufacturers have selection guides and application notes for transformer design. A brief overview of the more important design considerations is presented here. For operating frequencies greater than 100kHz, the flux in the core is usually limited by core loss, not saturation. It is important to review both criteria when selecting the transformer. The AC operating flux density for core loss is given by: B AC = VIN • DC • 108 2 • NP • Ae • fSW where: BAC is the AC operating flux density (gauss) DC is the operating duty cycle Ae is the effective cross sectional core area (cm2) fSW is the switching frequency To prevent core saturation during a transient condition, the peak flux density is: BPK = VIN(MAX) • DC (MAX)• 108 NP • Ae • f SW The core must be sized to provide sufficient window area for the amount of wire and insulation needed. The best performance is achieved by making each winding a single layer evenly distributed across the width of the bobbin. Multiple layers may be used to increase the copper area. Interleaving the primary and secondary windings will decrease the leakage inductance. In a single-ended forward converter, much of the energy stored in the leakage inductance is dissipated in the primary-side MOSFET during turn-off. It is good design practice to sandwich the secondary winding between two primary windings. For the 2-transistor forward converter shown in Figure 1, energy stored in the leakage inductance is returned to the input by diodes D1 and D2. With this topology, additional insulation for higher isolation can be used without significant penalty. For a more detailed discussion on transformer core and winding losses, see Application Note AN19. Inductor Selection The output inductor in a typical LTC1698 circuit is chosen for inductance value and saturation current rating. The output inductor in a forward converter operates the same as in a buck regulator. The inductance sets the ripple current, which is commonly chosen to be 40% of the full load current. Ripple current is set by: IRIPPLE = VOUT • tOFF(MAX) where: The minimum secondary turns count is: NS(MIN) VOUT + VD = NP • VIN(MIN)• D C (MAX) where: VOUT is the secondary output voltage VD is the voltage drop across the rectifier in the secondary VIN(MIN) is the minimum input voltage DC(MAX) is the maximum duty cycle L tOFF(MAX) = (1– DC (MIN)) fSW and DC(MIN) is calculated based on the maximum input voltage. DC (MIN) = NP V • OUT NS VIN(MAX) 1698f 16 LTC1698 U W U U APPLICATIO S I FOR ATIO Once the value of the inductor has been determined, an inductor with sufficient DC current rating is selected. Core saturation must be avoided under all operating conditions. Under start-up conditions, the converter sees a short circuit while charging the output capacitor. If the inductor saturates, the peak current will dramatically increase. The current will be limited only by the primary controller minimum on time and the circuit impedances. High efficiency converters generally cannot afford the core loss found in low cost iron powder cores, forcing the use of more expensive ferrite, molypermalloy, or Kool Mµ® cores. As inductance increases, core loss goes down. Increased inductance requires more turns of wire so copper losses will increase. The optimum inductor will have equal core and copper loss. Ferrite designs have very low core losses and are preferred at higher switching frequencies. Therefore, design goals concentrate on minimizing copper loss and preventing saturation. Kool Mµ is a very good, low-loss powder material with a “soft” saturation characteristic. Molypermalloy is more efficient at higher switching frequencies, but is also more expensive. Surface mount designs are available from many manufacturers using all of these materials. Output Capacitor Selection The output capacitor selection is primarily determined by the effective series resistance (ESR) to minimize voltage ripple. In a forward converter application, the inductor current is constantly flowing to the output capacitor, therefore, the ripple current at the output capacitor is small. The output ripple voltage is approximately given by: 1 VRIPPLE ≈ IRIPPLE • ESR + 8 • fSW • C OUT The output ripple is highest at maximum input voltage since IRIPPLE increases with input voltage. Typically, once the ESR requirement for COUT has been satisfied the capacitance is adequate for filtering and has the required RMS current rating. Fast load current transitions at the output will appear as a voltage across the ESR of the output capacitor until the feedback loop can change the inductor current to match the new load current value. As an example: at 3.3V out, a 10A load step with a 0.01Ω ESR output capacitor would experience a 100mV step at the output, a 3% output change. In surface mount applications, multiple capacitors may have to be placed in parallel to meet the ESR requirement. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1698. These items are also illustrated graphically in Figure 9. Check the following for your layout: 1. Keep the power circuit and the signal circuit segregated. Place the power circuit, shown in bold, so that the two MOSFET drain connections are made directly at the transformer. The two MOSFET sources should be as close together as possible. 2. Connect PGND directly to the sense resistor with as short a path as possible. The MOSFET gate drive return currents flow through this connection. 3. Connect the 4.7µF ceramic capacitor directly between VDD and PGND. This supplies the FG and CG drivers and must supply the gate drive current. 4. Bypass the VAUX supply with a 0.1µF ceramic capacitor returned to GND. 5. Place all signal components in close proximity to their associated LTC1698 pins. Return all signal component grounds directly to the GND pin. One common connection can be made to VOUT+ from R2, R5 and CCILM. 6. Make the connection between GND and PGND right at the LTC1698 pins. 7. Use a Kelvin-sense connection from the ISNS and ISNSGND pins to the secondary-side current-limit resistor RSECSEN. Kool Mµ is a registered trademark of Magnetics, Inc. 1698f 17 LTC1698 U W U U APPLICATIO S I FOR ATIO L1 VOUT+ • • T1 + 1Ω Q3 COUT Q4 RSECSEN VOUT – D3 1 C4 2 • • T2 4.7µF R7 FG LTC1698 CG SYNC 3 R2 VAUX PGND 4 GND 5 6 RK MOC207 R1 CK VDD RC CC 7 CFB 8 ICOMP ISNS OPTODRV ISENSGND VCOMP MARGIN PWRGD VFB OVPIN 16 CCILM 15 RCILM 14 R5 13 1k 12 0.1µF 11 10 1k 0.1µF 9 0.1µF BOLD LINES INDICATE HIGH CURRENT PATHS R4 1698 F09 Figure 9. LTC1698 Layout Diagram VOUT1 3.3V AT 10A L1 VIN 36V TO 72V VCC BIAS 10k VCC BOOST VDD • • CMDSH-3 SYNC GBIAS VCOMP 10pF CG 4.7µF LT3710 VFB CS 680pF FG CSET Q1 TG L2 1.8µH 0.1µF 0.006Ω SW ISNS LTC1698 10k 180pF TG BG LT3781 SG • • + Q2 ILCOMP BG 0.01µF SS B340A VOUT2 1.8V AT 10A COUT2 4700pF VAOUT BGS SYNC 3.3k 3.01k 220Ω 33nF PGND VFB CL– CL+ 2.32k 1698 F10 OPTODRV VC + – VREF GND VFB ISOLATION BOUNDARY COUT2: POSCAP, 680µF/4V L2: SUMIDA CEP125-IR8MC-H Q1, Q2: SILICONIX Si7440DP Figure 10. Simplified Single Secondary Winding 3.3V and 1.8V Output Isolated DC/DC Converter 1698f 18 4.7µF 16V 1000pF 10k VIN 5241B 11V 20k 270k 0.25W VIN MMBD4148 VCC 1µF ON/OFF VIN– 0.56µH DO1813P-561HC VCC 0.1µF 100V 100Ω FMMT718 FMMT619 VCC B2100 10k 0.047µF 330pF BAT54 1.24k 1% 1µF 5VREF 52.3k 1% 5 RT1 100k 82pF 6 0Ω 7 0.1µF 8 4 10Ω 10 3300pF 3k 1k 5VREF 5 6 7 1• 4 MOC207 8 4 3 220pF 0Ω 2 1 •8 7 T2 PULSE ENG P2033 2200pF 250VAC 3.3Ω 2200pF 4700pF VOUT 1µF 16V 1 VAUX FG 16 GND 4 LTC1698 ISNSGND 11 0.22µF 50V PGND 3 ISNS 12 2k 0.25W 1000pF 2 6 ICOMP MARGIN OVPIN VFB VCOMP PWRGD 10 CG 13 7 9 8 0.022µF 3.3k 1698 F11 1.24k 1% VOUT– RTN VOUT+ 5V /30A 976Ω 1% VOUT TRIM 3.01k 1% VOUT 22µF 6.3V 4.22k 1% 470µF 6.3V POSCAP 470µF 6.3V Si7884DP Si7884DP Si7884DP POSCAP + 470µF 6.3V POSCAP + + 470µF 6.3V POSCAP VOUT + OPTODRV SYNC VDD 0.1µF 14 5 15 MMBZ5240B 100Ω 0.25W Si7884DP 470Ω 1k 4.7µF 16V FZT690B B0540W Si7884DP 1000pF 100V 10Ω 1/4W 10Ω 1/4W 1000pF 100V PULSE PA0265 Figure 11. 36VIN-72VIN to 5V/30A Isolated Synchronous Forward Converter 0.01µF 2.43k 1% 3 VCC BAT54S BAS21 3 4 2 5 7 T1 PULSE PA0285 1 Si7456DP BAS21 0.008Ω 1%, 1W ZVN3310F 10Ω B2100 Si7456DP 1mH DO1608C-105 COILCRAFT VCC Si7456DP Si7456DP 20 18 19 15 11 14 13 VCC VBST BSTREF TG BG SENSE PGND 12 2 SG OVLO LT3781 1 SHDN 9 5VREF FSET THERM SYNC SS SGND VC VFB BAS21 73.2k 1% B0540W FZT853 1.5µF 100V 1.5µF 100V 0Ω • VIN • • • VIN+ 36V TO 72V LTC1698 TYPICAL APPLICATIO S 1698f 19 U 0.1µF 20V 270k 1/4W 47k 100Ω 1/4W 0.82µF 100V ×2 3300pF 10k RIN (OPTIONAL) VIN 20 18 19 17 16 15 10Ω MMBT3906 11 10k BAT54 BAT54 0.1µF 12 VCC 330pF ZETEX ZVN3310F 1mH DO1608C-105 COILCRAFT 1.24k 1% 52.3k 1% 5 RT1 100k 82pF 6 0.01µF 2.43k 1% 3 10k 7 4 4700pF 8 3k 1k 3300pF 10Ω 10 5 8 4 3 MOC207 8 100Ω 2 1 5 •4 4700pF 1k 8 470Ω 10V MMBZ5240B 2k PULSE ENG PA0184 1• 3.3Ω 2200pF 250V 6 5 7 • 14 1 12 VAUX PGND 3 OPTODRV SYNC 11 1k 16 2 10Ω 1/4W GND 4 LTC1698 6 PWRGD 10 7 9 8 + + 4 3 3.01k 1% 100Ω 1/4W 3.01k 1% –SENSE 3.01k 1% 100Ω 1/4W +SENSE + 330µF 6.3V KEMET T520 1.78k 1% 3.01k 1% 1698 F12 0.22µF 1.24k 1% 1k 2.43k 1% VOUT+ VOUT+ TRIM OPTIONAL DIFFERENTIAL SENSE** 3.01k 2 1% – LT1783CS5 ROUT (OPTIONAL) 1 9V 5 + VOUT 330µF 6.3V + KEMET Si7892DP Si7892DP T520 ICOMP 13 MARGIN OVPIN VFB 0.022µF 1k 1000pF 1000pF 100V VCOMP 10Ω 1/4W FG CG Si7892DP ISNSGND 0.1µF 1k VDD ISNS 9V 0.1µF 5 15 4.7µF FZT690B MBR0540 4.7Ω Si7892DP 1000pF 100V 330µF 6.3V KEMET T520 Figure 12. LT3781/LTC1698 36VIN-72VIN to 3.3V/15A Isolated Synchronous Forward Converter-Quarter Brick 1µF 5VREF 7 6 5VREF BAT54 220pF 0.22µF BAS21 BAS21 0.03Ω 3 4 2 1 T1 38431 SCHOTT Si7456DP Si7456DP MURS120 MMBT3906 VCC MURS120 10Ω 13 VCC VBST BSTREF TG NC NC BG SENSE SG 14 2 PGND OVLO LT3781 1 SHDN 9 THERM SYNC SS SGND VC VFB 5VREF FSET BAS21 73.2k 1% 62k 1/4W 0.1µF VIN MMBT3904 18V MMBZ5248B 100Ω 1/4W 0.82µF 100V VIN OPTIONAL FAST START* 4.7µF 5VREF MMBD914 VCC FQT7N10L 1000pF VCC + 100µF ON/OFF VIN– VIN+ • • 20 • 3.3µH D01608C-332 COILCRAFT VOUT– 330µF 6.3V KEMET T520 VOUT+ LTC1698 TYPICAL APPLICATIO S 1698f U 1.5µF 100V + 68µF 25V 1000pF 18V MMBZ5248BLT1 0.33µF 50V 0.1µF 50V 270k 0.25W 20k 10k 15V MMBZ5245BLT1 VCC PINS 9-10 5T BIFILAR 33AWG PINS 2-5 12T BIFILAR 33AWG PINS 4-3 7T QUADFILAR 26AWG PINS 7,8-11,12 12T BIFILAR 24AWG PINS 6-4 8T QUADFILAR 26AWG VIN– VIN+ 1.24k 1% 24k 56k 73.2k 1% VIN 0.1µF 100V VTOP 2M POLYESTER FILM 1.5µF 100V 100pF 200Ω 10Ω VCC 330pF ZVN3310F VTOP BAT54 10k BAT54 1mH DO1608C-105 COILCRAFT VCC 1µF 25V 5VREF 52.3k 1% 5 6 7 4700pF 8 4 10Ω 10 3300pF 3k 5 6 1 4 2 100Ω 0.25W 1k 5 7 6 1• 3 8 2 ISO1 MOC207 4 3 1 1k 4 •6 0.1µF 50V 10k 4.7µF 16V 5 15 Si4486EY ×2 VDD 1 22Ω 0.25W 470pF 100V 22Ω 0.25W FG 16 LTC1698 2 CG Si4486EY ×2 + 6 OVPIN VFB VCOMP 9 215Ω 215Ω VOUT– 0.1µF 110Ω 0.033µF 3.3k 1000pF 8 + 68µF 25V AVX BAT54 0.022µF + 68µF 25V AVX 7 MARGIN ICOMP 13 VAUX ISNS ISNSGND PGND GND PWRGD 14 12 11 3 4 10 OPTODRV SYNC 470pF 100V MURS120T3 10Ω 0.25W FZT603 ZETEX 0.1µF 50V 4700pF 1k 220pF 10V MMBZ5240BLT1 20k 0.25W 2200pF 250V 3.3Ω 9 10 7 8 11 12 25µH MAG INC CORE 55380-A2 18T #18AWG Figure 13. 36VIN-72VIN to 12V/5A Isolated Synchronous Forward Converter 82pF 3 T1 3 EFD25 T2 0.01µF 50V MIDCOM, INC 31264R 5VREF BAT54 47Ω 0.22µF 50V BAS21LT1 NC VTOP SUD40N10-25 BAS21LT1 0.025Ω 1/2W MURS120T3 SUD40N10-25 SUD40N10-25 MURS120T3 10Ω 12 13 20 18 19 17 16 11 14 VCC VBST BSTREF TG BLKSENS BG SENSE IMAX SG 15 2 PGND OVLO LT3781 1 SHDN 9 5VREF FSET THERM SYNC SGND VC VFB SS BAS21LT1 SQUARE 0.031 INCH MARGIN TAPE T1 EFD25-3F3 LP = 120µH 2mil GAP EACH LEG 1.5µF 100V VIN • • • • 4.7µH DO1608C-472 COILCRAFT 1698 F13 909Ω 0.1% 0.015Ω 68µF 25V AVX 0.01µF VOUT+ VOUT– UNLESS NOTED: ALL PNPs MMBT39O6LT1 1k 8.25k 0.1% VOUT+ + 68µF 25V AVX VOUT+ LTC1698 TYPICAL APPLICATIO S 1698f 21 U LTC1698 U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 TYP RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) .053 – .068 (1.351 – 1.727) 2 3 4 5 6 7 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE .008 – .012 (0.203 – 0.305) .0250 (0.635) BSC GN16 (SSOP) 0502 1698f 22 LTC1698 U PACKAGE DESCRIPTIO S Package 16-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .386 – .394 (9.804 – 10.008) NOTE 3 .045 ±.005 .050 BSC 16 N 15 14 13 12 11 10 9 N .245 MIN .160 ±.005 .150 – .157 (3.810 – 3.988) NOTE 3 .228 – .244 (5.791 – 6.197) 1 .030 ±.005 TYP 2 3 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT 1 .010 – .020 × 45° (0.254 – 0.508) 2 3 4 5 6 .053 – .069 (1.346 – 1.752) .008 – .010 (0.203 – 0.254) NOTE: 1. DIMENSIONS IN .014 – .019 (0.355 – 0.483) TYP 8 .004 – .010 (0.101 – 0.254) 0° – 8° TYP .016 – .050 (0.406 – 1.270) 7 .050 (1.270) BSC S16 0502 INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 1698f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC1698 U TYPICAL APPLICATIO S LT3781/LTC1698 Isolated 5V/30A Converter Efficiency vs Load Current LT3781/LTC1698 Isolated 3.3V/15A Converter 95 VIN = 36V 90 EFFICIENCY (%) VIN = 48V 85 80 VIN = 72V 75 70 65 TOP 0 10 15 20 LOAD CURRENT (A) 5 25 30 1698 TA01 LT3781/LTC1698 Isolated 3.3V/15A Converter LT3781/LTC1698 Isolated 3.3V/15A Converter Efficiency vs Load Current 95 VIN = 36V EFFICIENCY (%) 90 85 VIN = 48V 80 75 VIN = 72V 70 BOTTOM 0 3 9 6 IOUT (XX) 12 15 1698 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1339 High Power Synchronous DC/DC Controller Operation Up to 60V Maximum LT1425 Isolated Flyback Switching Regulator General Purpose with External Application Resistor LT1431 Programmable Reference 0.4% Initial Voltage Tolerance LT1680 High Power DC/DC Step-Up Controller Operation Up to 60V Maximum LT1681 Dual Transistor Synchronous Forward Controller Operation Up to 72V Maximum LT1725 General Purpose Isolated Flyback Controller Drives External Power MOSFET with External ISENSE Resistor LT1737 High Power Isolated Flyback Controller Sense Output Voltage Directly from Primary-Side Winding LT3710 Secondary Side Synchronous Post Regulator Generates a Regulated Auxiliary Output in Isolated DC/DC Converters, Dual N-Channel MOSFET Synchronous Drivers LT3781 Dual Transistor Synchronous Forward Controller Operation up to 72V Maximum 1698f 24 Linear Technology Corporation LT/TP 0203 2K • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2000