TWL1200 www.ti.com...................................................................................................................................................................................................... SCES786 – JUNE 2009 SDIO, UART, AND AUDIO VOLTAGE-TRANSLATION TRANSCEIVER FEATURES 1 • Level Translator – VCCA and VCCB Range of 1.1 V to 3.6 V • Seamlessly Bridges 1.8-V/2.6-V Digital-Switching Compatibility Gap Between 2.6-V processors and TI’s Wi-Link (WL1271 and WL1273) • 23 • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2500-V Human-Body Model (A114-B) – 250-V Machine Model (A115-A) – 1500-V Charged-Device Model (C101) YFF PACKAGE (TOP VIEW) ZQC PACKAGE (TOP VIEW) 1 1 2 3 4 5 6 7 A B C D E F G 3 2 4 5 6 7 A B C D E F G BGA PACKAGE TERMINAL ASSIGNMENTS 1 2 3 4 5 6 7 A SDIO_CLK(A) SDIO_CMD(A) AUDIO_CLK(A) AUD_DIR AUDIO_CLK(B) SDIO_CMD(B) SDIO_CLK(B) B SDIO_DATA3(A) SDIO_DATA0(A) AUDIO_F-SYN(A) C SDIO_DATA2(A) SDIO_DATA1(A) D WLAN_EN(A) WLAN_IRQ(A) E CLK_REQ(A) F G OE AUDIO_F-SYN(B) SDIO_DATA0(B) SDIO_DATA3(B) VCCA VCCB SDIO_DATA1(B) SDIO_DATA2(B) GND VCCA VCCB WLAN_EN(B) WLAN_IRQ(B) BT_EN(A) GND GND GND BT_EN(B) CLK_REQ(B) BT_UART_CTS(A) BT_UART_RTS(A) AUDIO_IN(A) SLOW_CLK(B) AUDIO_IN(B) BT_UART_RTS(B) BT_UART_CTS(B) BT_UART_RX(A) BT_UART_TX(A) AUDIO_OUT(A) SLOW_CLK(A) AUDIO_OUT(B) BT_UART_TX(B) BT_UART_RX(B) 1 2 3 4 5 6 7 A SDIO_CLK(A) SDIO_CMD(A) AUDIO_CLK(A) AUD_DIR AUDIO_CLK(B) SDIO_CMD(B) SDIO_CLK(B) B SDIO_DATA3(A) SDIO_DATA0(A) AUDIO_F-SYN(A) OE AUDIO_F-SYN(B) SDIO_DATA0(B) SDIO_DATA3(B) C SDIO_DATA2(A) SDIO_DATA1(A) NC (1) VCCA VCCB SDIO_DATA1(B) SDIO_DATA2(B) D WLAN_EN(A) WLAN_IRQ(A) GND VCCA VCCB WLAN_EN(B) WLAN_IRQ(B) E CLK_REQ(A) BT_EN(A) GND GND GND BT_EN(B) CLK_REQ(B) F BT_UART_CTS(A) BT_UART_RTS(A) AUDIO_IN(A) SLOW_CLK(B) AUDIO_IN(B) BT_UART_RTS(B) BT_UART_CTS(B) G BT_UART_RX(A) BT_UART_TX(A) AUDIO_OUT(A) SLOW_CLK(A) AUDIO_OUT(B) BT_UART_TX(B) BT_UART_RX(B) WCS PACKAGE TERMINAL ASSIGNMENTS (1) NC – No internal connection 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MicroStar Junior is a trademark of Texas Instruments. MicroStar Junior, are trademarks of ~ Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TWL1200 SCES786 – JUNE 2009...................................................................................................................................................................................................... www.ti.com DESCRIPTION/ORDERING INFORMATION The TWL1200 is an 19-bit voltage translator specifically designed to seamlessly bridge the 1.8-V/2.6-V digital-switching compatibility gap between 2.6-V baseband and the TI Wi-Link-6 (WL1271/3). It is optimized for SDIO, UART, and audio functions. The TWL1200 has two supply-voltage pins, VCCA and VCCB, that can be operated over the full range of 1.1 V to 3.6 V. The TWL1200 enables system designers to easily interface applications processors or digital basebands to peripherals operating at a different I/O voltage levels, such as the TI Wi-Link-6 (WL1271/3) or other SDIO/memory cards. The TWL1200 is offered in both 48-ball 0.5-mm ball grid array (BGA) and 49-bump 0.4-mm wafer chip scale package (WCSP) packages. Low static power consumption and small package size make the TWL1200 an ideal choice for mobile-phone applications. ORDERING INFORMATION (1) –40°C to 85°C (1) (2) ORDERABLE PART NUMBER PACKAGE (2) TA TOP-SIDE MARKING BGA MicroStar Junior™ – ZQC (Pb-free) Tape and reel TWL1200ZQCR YW200 WCSP™ – YFF (Pb-free) Tape and reel TWL1200YFFR PREVIEW For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. TERMINAL FUNCTIONS TERMINAL 2 ZQC BALL NO. YFF BUMP NO. C4, D4 C4, D4 VCCA Power B2 B2 SDIO_DATA0(A) I/O Data bit 1 connected to baseband SDIO controller C2 C2 SDIO_DATA1(A) I/O Data bit 2 connected to baseband SDIO controller C1 C1 SDIO_DATA2(A) I/O Data bit 3 connected to baseband SDIO controller B1 B1 SDIO_DATA3(A) I/O Data bit 4 connected to baseband SDIO controller A2 A2 SDIO_CMD(A) I/O Command bit connected to baseband SDIO controller. Referenced to VCCA. A6 A6 SDIO_CMD(B) I/O Command bit connected to SD/SDIO peripheral. Includes a 15-kΩ pullup resistor to VCCB. D3, E3, E4, E5 D3, E3, E4, E5 GND NAME TYPE DESCRIPTION A-side supply voltage (1.1 V to 3.6 V) Ground B6 B6 SDIO_DATA0(B) I/O Data bit 1 connected to SD/SDIO peripheral C6 C6 SDIO_DATA1(B) I/O Data bit 2 connected to SD/SDIO peripheral C7 C7 SDIO_DATA2(B) I/O Data bit 3 connected to SD/SDIO peripheral B7 B7 SDIO_DATA3(B) I/O Data bit 4 connected to SD/SDIO peripheral A1 A1 SDIO_CLK(A) I Clock signal connected to baseband SDIO controller. Referenced to VCCA. A7 A7 SDIO_CLK(B) O Clock signal connected to SD/SDIO peripheral. Referenced to VCCB; drive strength = 8 mA C5, D5 C5, D5 VCCB Pwr C3 C3 – – No ball (for ZQC) and No-Connect (for YFF) B4 B4 OE I Output enable (active low) A4 A4 AUD_DIR I Direction control signal for AUDIO_CLK and AUDIO_F-SYNC signals G3 G3 AUDIO_OUT(A) O Connected to baseband audio subsystem; drive strength = 4 mA G5 G5 AUDIO_OUT(B) I Connected to Wi-Link-6 PCM subsystem D1 D1 WLAN_EN(A) I Connected to baseband SDIO controller D6 D6 WLAN_EN(B) O Connected to SD/SDIO peripheral; drive strength = 2 mA G2 G2 BT_UART_TX(A) O Connected to baseband UART subsystem; drive strength = 8 mA G6 G6 BT_UART_TX(B) I Connected to BT UART subsystem of Wi-Link-6 B-side supply voltage (1.1 V to 3.6 V) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 TWL1200 www.ti.com...................................................................................................................................................................................................... SCES786 – JUNE 2009 TERMINAL FUNCTIONS (continued) TERMINAL ZQC BALL NO. YFF BUMP NO. NAME D2 D2 WLAN_IRQ(A) O Connected to baseband SDIO controller; drive strength = 4 mA D7 D7 WLAN_IRQ(B) I Connected to SD/SDIO peripheral G4 G4 SLOW_CLK(A) I Low frequency 32-kHz clock connected to baseband device F4 F4 SLOW_CLK(B) O Low frequency 32-kHz clock connected to Wi-Link-6 device; drive strength = 2 mA G1 G1 BT_UART_RX(A) I Connected to baseband UART subsystem G7 G7 BT_UART_RX(B) O Connected to BT UART subsystem of Wi-Link-6; drive strength = 8 mA E1 E1 CLK_REQ(A) O Connected to baseband SDIO controller; drive strength = 4 mA E7 E7 CLK_REQ(B) I Connected to SD/SDIO peripheral F1 F1 BT_UART_CTS(A) I Connected to baseband UART subsystem F3 F3 AUDIO_IN(A) I Connected to baseband audio subsystem F5 F5 AUDIO_IN(B) O Connected to Wi-Link-6 PCM subsystem; drive strength = 4 mA A3 A3 AUDIO_CLK(A) I/O Connected to baseband audio subsystem; drive strength = 4 mA A5 A5 AUDIO_CLK(B) I/O Connected to Wi-Link-6 PCM subsystem; drive strength = 4 mA E2 E2 BT_EN(A) I Connected to baseband UART subsystem E6 E6 BT_EN(B) O Connected to BT UART subsystem of Wi-Link-6; drive strength = 2 mA F7 F7 BT_UART CTS(B) O Connected to BT UART subsystem of Wi-Link-6; drive strength = 4 mA F2 F2 BT_UART RTS(A) O Connected to baseband UART subsystem; drive strength = 4 mA F6 F6 BT_UART RTS(B) I Connected to BT UART subsystem of Wi-Link-6 B3 B3 AUDIO_F-SYN(A) I/O Connected to baseband audio subsystem; drive strength = 4 mA B5 B5 AUDIO_F-SYN(B) I/O Connected to Wi-Link-6 PCM subsystem; drive strength = 4 mA TYPE DESCRIPTION FUNCTION TABLE CONTROL INPUTS OPERATION OE AUD_DIR H X All outputs are Hi-Z L H AUDIO_CLK(A) to AUDIO_CLK(B) and AUDIO_F-SYNC(A) to AUDIO_F-SYNC(B) L L AUDIO_CLK(B) to AUDIO_CLK(A) and AUDIO_F-SYNC(B) to AUDIO_F-SYNC(A) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 3 TWL1200 SCES786 – JUNE 2009...................................................................................................................................................................................................... www.ti.com LOGIC DIAGRAM VCCA VCCB Control Logic OE BT_EANBLE(A) BT_EANBLE(B) BT_UART_RX(A) BT_UART_RX(B) BT_UART_CTS(A) BT_UART_CTS(B) BT_UART_TX(A) BT_UART_TX(B) BT_UART_RTS(A) BT_UART_RTS(B) AUDIO_IN(A) AUDIO_IN(B) AUDIO_OUT(A) AUDIO_OUT(B) SLOW_CLK(A) SLOW_CLK(B) Audio Control AUD_DIR AUDIO_CLK(A) AUDIO_CLK(B) AUDIO_FSYNC(A) AUDIO_F_SYNC(B) VCCA SDIO Bit R1 (see Note A) SDIO-CMD(A) VCCB R2 (see Note A) One-Shot Translator Gate Control One-Shot SDIO-CMD(B) One-Shot Translator One-Shot VCCA SDIO Bit R1 (see Note A) SDIO-DATA0(A) VCCB R2 (see Note A) One-Shot Translator Gate Control One-Shot SDIO-DATA0(B) One-Shot Translator One-Shot VCCA SDIO Bit R1 (see Note A) SDIO-DATA1(A) VCCB R2 (see Note A) One-Shot Translator Gate Control One-Shot SDIO-DATA1(B) One-Shot Translator One-Shot SDIO Bit VCCA R1 (see Note A) SDIO-DATA2(A) VCCB R2 (see Note A) One-Shot Translator Gate Control One-Shot SDIO-DATA2(B) One-Shot Translator One-Shot VCCA SDIO Bit R1 (see Note A) SDIO-DATA3(A) VCCB R2 (see Note A) One-Shot Translator Gate Control One-Shot SDIO-DATA3(B) One-Shot Translator One-Shot SDIO-CLK(A) WLAN-ENABLE(A) 4 SDIO-CLK(B) WLAN-ENABLE(B) WLAN-IRQ(A) WLAN-IRQ(B) CLK-REQ(A) CLK-REQ(B) A. R1 and R2 resistor values are determined based upon the logic level applied to the A port or B port as follows: R1 and R2 = 25 kΩ when a logic level low is applied to the A port or B port. R1 and R2 = 4 kΩ when a logic level high is applied to the A port or B port. R1 and R2 = 70 kΩ when the port is deselected (or in High-Z or 3-state). B. OE controls all output buffers. When OE = high, all outputs are Hi-Z. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 TWL1200 www.ti.com...................................................................................................................................................................................................... SCES786 – JUNE 2009 TYPICAL APPLICATION BLOCK DIAGRAM 1.8 V 2.6 V Wi-Link-6 (WL1271/3) Baseband Processor VCCA SDIO Controller SDIO_DATA0(B) SDIO_DATA1(A) SDIO_DATA1(B) SDIO_DATA2(A) SDIO_DATA2(B) SDIO_DATA3(A) SDIO_DATA3(B) SDIO_CMD(A) SDIO_CMD(B) SDIO_CLK(A) SDIO_CLK(B) WLAN_ENABLE(A) WLAN_ENABLE(B) WLAN_IRQ(A) WLAN_IRQ(B) CLK_REQ(A) CLK_REQ(B) BT_ENABLE(A) UART Audio VCCB SDIO_DATA0(A) SD/SDIO Peripheral BT_ENABLE(B) TWL1200 BT_UART_RX(A) BT_UART_RX(B) BT_UART_CTS(A) BT_UART_CTS(B) BT_UART_TX(A) BT_UART_TX(B) BT_UART_RTS(A) BT_UART_RTS(B) AUDIO_IN(A) AUDIO_IN(B) AUDIO_CLK(A) AUDIO_CLK(B) AUDIO F-SYNK(A) AUDIO F-SYNK(B) AUDIO_OUT(A) AUDIO_OUT(B) SLOW_CLK(A) BT UART PCM SLOW_CLK(B) AUD_DIR (see Note A) OE (see Note B) GND A. AUD_DIR must be biased to determine audio direction (see Function Table for properly establishing the bias). B. OE is an active-low pin that must be grounded to 0 V to enable operation of the TWL1200 device. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 5 TWL1200 SCES786 – JUNE 2009...................................................................................................................................................................................................... www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCCA Supply voltage range –0.5 4.6 UNIT V VCCB Supply voltage range –0.5 4.6 V I/O ports (A port) –0.5 4.6 VI Input voltage range I/O ports (B port) –0.5 4.6 Control inputs –0.5 4.6 A port –0.5 4.6 B port –0.5 4.6 A port –0.5 4.6 B port –0.5 4.6 V VO Voltage range applied to any output in the high-impedance or power-off state (2) VO Voltage range applied to any output in the high or low state (2) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA 150 °C Continuous current through VCCA, VCCB, or GND Tstg (1) (2) Storage temperature range –65 V V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. THERMAL IMPEDANCE RATINGS UNIT θJA (1) 6 Package thermal impedance (1) ZQC package 171.6 YFF package TBD °C/W The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 TWL1200 www.ti.com...................................................................................................................................................................................................... SCES786 – JUNE 2009 RECOMMENDED OPERATING CONDITIONS (1) VCCI VCCO MIN MAX UNIT VCCA Supply voltage 1.1 3.6 V VCCB Supply voltage 1.1 3.6 V VCCI × 0.65 3.6 VCCA × 0.65 3.6 VCCI – 0.2 VCCI 0 VCCI × 0.35 0 VCCA × 0.35 0 0.15 V 0 3.6 V Active state 0 VCCO 3-state 0 3.6 VIH High-level input voltage VIH High-level input voltage Low-level input voltage VIL Buffer type 1.1 V to 3.6 V 1.1 V to 3.6 V Switch type 1.1 V to 3.6 V 1.1 V to 3.6 V Buffer type and Control Logic 1.1 V to 3.6 V 1.1 V to 3.6 V OE and AUD_DIR OE and AUD_DIR VIL (2) Low-level input voltage VI Input voltage VO Output voltage IOH High-level output current IOL Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature (1) (2) Switch type 1.1 V to 3.6 V 1.1 V to 3.6 V 1.1 V to 1.3 V –0.5 1.4 V to 1.6 V –1 1.65 V to 1.95 V –2 2.3 V to 2.7 V –4 3 V to 3.6 V –8 1.1 V to 1.3 V 0.5 1.4 V to 1.6 V 1 1.65 V to 1.95 V 2 2.3 V to 2.7 V 4 3 V to 3.6 V 8 –40 V V V V mA mA 5 ns/V 85 °C All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Note, the max VIL value is provided to ensure that a valid VOL is maintained. The VOL value is the VIL + the voltage-drop across the pass-gate transistor. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 7 TWL1200 SCES786 – JUNE 2009...................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER A port (Buffer-type output, 8-mA drive) VOH A port (Buffer-type output, 4-mA drive) VOH A port (Switch-type outputs) A port (Buffer-type output, 8-mA drive) VOL A port (Buffer-type output, 4-mA drive) VOL A port (Switch-type outputs) B port (Buffer-type output, 8-mA drive) VOH B port (Buffer-type output, 4-mA drive) B port (Buffer-type output, 2-mA drive) B port (Switch-type outputs) B port (Buffer-type output, 8-mA drive) VOL B port (Buffer-type output, 4-mA drive) B port (Buffer-type output, 2-mA drive) B port (Switch-type outputs) TEST CONDITIONS IOH = –100 µA IOH = –8 mA IOH = –100 µA IOH = –4 mA MIN 1.1 V to 3.6 V 1.1 V to 3.6 V 1.65 V 1.65 V TYP (1) MAX UNIT VCCO – 0.2 1.2 2.5 V 2.5 V 1.1 V to 3.6 V 1.1 V to 3.6 V 1.97 1.65 V 1.65 V 1.2 V VCCO – 0.2 2.5 V 2.5 V 1.97 1.65 V 1.5 2.5 V 2.5 V 2.3 1.1 V to 3.6 V 1.1 V to 3.6 V 0.2 1.65 V 1.65 V 0.45 2.5 V 2.5 V 0.55 1.1 V to 3.6 V 1.1 V to 3.6 V 0.2 1.65 V 1.65 V 0.45 2.5 V 2.5 V 0.55 IOL = 220 µA, VIN = 0.15 V 1.65 V 1.65 V 0.45 IOL = 300 µA, VIN = 0.15 V 2.5 V 2.5 V 0.55 1.1 V to 3.6 V 1.1 V to 3.6 V 1.65 V 1.65 V 1.2 2.5 V 2.5 V 1.97 1.1 V to 3.6 V 1.1 V to 3.6 V 1.65 V 1.65 V 1.2 2.5 V 2.5 V 1.97 1.1 V to 3.6 V 1.1 V to 3.6 V 1.65 V 1.65 V 1.2 IOH = –20 µA IOL = 100 µA IOL = 8 mA IOL = 100 µA IOL = 4 mA IOH = –100 µA IOH = –8 mA IOH = –100 µA IOH = –4 mA IOH = –100 µA IOH = –2 mA V V VCC0 – 0.2 2.5 V 1.97 1.65 V 1.5 2.5 V 2.5 V 2.3 1.1 V to 3.6 V 1.1 V to 3.6 V 0.2 1.65 V 1.65 V 0.45 2.5 V 2.5 V 0.55 1.1 V to 3.6 V 1.1 V to 3.6 V 0.2 1.65 V 1.65 V 0.45 2.5 V 2.5 V 0.55 1.1 V to 3.6 V 1.1 V to 3.6 V 0.2 1.65 V 1.65 V 0.45 2.5 V 2.5 V 0.55 IOL = 220 µA, VIN = 0.15 V 1.65 V 1.65 V 0.45 IOL = 300 µA, VIN = 0.15 V 2.5 V 2.5 V 0.55 1.1 V to 3.6 V 1.1 V to 3.6 V ±1 1.1 V to 3.6 V 1.1 V to 3.6 V 15 3.6 V 0V 14 0V 3.6 V –12 IOL = 100 µA IOL = 8 mA IOL = 100 µA IOL = 4 mA IOL = 100 µA IOL = 2 mA ICCA Switch-type I/O are open and all other inputs are biased at either VCC or GND V VCC0 – 0.2 2.5 V IOH = –20 µA V VCC0 – 0.2 1.65 V VI = VCCA or GND 8 VCCB 1.65 V II (1) VCCA V µA µA All typical values are at TA = 25°C. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 TWL1200 www.ti.com...................................................................................................................................................................................................... SCES786 – JUNE 2009 ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS ICCB Switch-type I/O are open and all other inputs are biased at either VCC or GND ICCA + ICCB VI = VCCI or GND, IO = 0 Cio Ci Co MIN TYP (1) MAX UNIT VCCA VCCB 1.1 V to 3.6 V 1.1 V to 3.6 V 15 3.6 V 0V –12 0V 3.6 V 14 1.1 V to 3.6 V 1.1 V to 3.6 V 30 Auto-Dir (SDIO lines) VI = VCCI 5.5 Bi-Dir buffer VI = VCCX or GND 4.5 AUD_DIR / OE VI = VCCA or GND 4 Buffer VI = VCCX or GND 4 2-mA buffer VI = VCCX or GND 5 4-mA buffer VI = VCCX or GND 5 8-mA buffer VI = VCCX or GND 6 µA µA pF pF pF OUTPUT DRIVE STRENGTH 2 mA 4 mA 8 mA WLAN_EN(B) AUDIO_OUT(A) SDIO_CLK(B) SLOW_CLK(B) WLAN_IRQ(A) BT_UART_TX(A) BT_EN(B) CLK_REQ(A) BT_UART_RX(B) AUDIO_IN(B) AUDIO_CLK(A) BT_UART CTS(B) BT_UART RTS(A) AUDIO_F-SYNC(A) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 9 TWL1200 SCES786 – JUNE 2009...................................................................................................................................................................................................... www.ti.com TIMING REQUIREMENTS VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range (unless otherwise noted) VCCB = 1.8 V ± 0.15 V MIN SDIO_CMD Data rate SDIO_CLK SDIO_DATAx SDIO_CMD tW Pulse duration SDIO_CLK SDIO_DATAx Push-pull driving 60 Open-drain driving 1 Push-pull driving Push-pull driving Open-drain driving Push-pull driving UNIT MAX Mbps 50 MHz 60 Mbps 17 ns 1 µs 10 ns 17 ns TIMING REQUIREMENTS VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range (unless otherwise noted) VCCB = 1.8 V ± 0.15 V MIN SDIO_CMD Data rate SDIO_CLK SDIO_DATAx SDIO_CMD tW Pulse duration SDIO_CLK SDIO_DATAx 10 Push-pull driving 60 Open-drain driving 1 Push-pull driving Push-pull driving Open-drain driving Push-pull driving Submit Documentation Feedback UNIT MAX Mbps 50 MHz 60 Mbps 17 ns 1 µs 10 ns 17 ns Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 TWL1200 www.ti.com...................................................................................................................................................................................................... SCES786 – JUNE 2009 SWITCHING CHARACTERISTICS VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCCB = 1.8 V ± 0.15 V MIN Push-pull driving SDIO_CMD(A) SDIO_CMD(B) 7 Open-drain driving (H-to-L) 1.1 7 Open-drain driving (L-to-H) 30 510 Push-pull driving SDIO_CMD(B) tpd ten tdis trA SDIO_CMD(A) SDIO_CLK(A) SDIO_CLK(B) SDIO_DATAx(A) SDIO_DATAx(B) SDIO_DATAx(B) SDIO_DATAx(A) Buffered input 2-mA drive strength output Buffered input Buffered input OE OE 1 6.5 1 7 Push-pull driving 7 7.6 4-mA drive strength output Push-pull driving 1 7 8-mA drive strength output Push-pull driving 1 6.5 2-mA drive strength output Push-pull driving 16 4-mA drive strength output Push-pull driving 19 8-mA drive strength output Push-pull driving 18 Switch-type output Push-pull driving 1 2-mA drive strength output Push-pull driving 17 4-mA drive strength output Push-pull driving 16.5 8-mA drive strength output Push-pull driving 16 Switch-type outputs Push-pull driving SDIO_CMD(A) rise time SDIO_CLK(B) rise time SDIO_CMD(A) fall time SDIO_DATAx(A) fall time SDIO_CMD(B) fall time SDIO_CLK(B) fall time SDIO_DATAx(B) fall time tsk(O) 515 1 SDIO_DATAx(B) rise time tfB 7.5 30 Push-pull driving SDIO_CMD(B) rise time tfA 1 Open-drain driving (L-to-H) 1 SDIO_DATAx(A) rise time trB 7 Open-drain driving (H-to-L) Push-pull driving Push-pull driving Open-drain driving 1 1 5 15 420 Push-pull driving 1 4.7 Push-pull driving 1 9.7 Open-drain driving 15 420 0.5 6 1 9.7 Push-pull driving 0.7 8.3 Open-drain driving 1.6 8.3 Push-pull driving 1 8.3 Push-pull driving 1 9.9 1.6 10.9 0.5 5.3 1 9.9 Push-pull driving Open-drain driving Push-pull driving SDIO Ch-A to Ch-B skew Push-pull driving 0.4 SDIO Ch-B to Ch-A skew Push-pull driving 0.4 SDIO channel-to-clock skew Push-pull driving 1.3 Push-pull driving 60 SDIO_CMD Max data rate SDIO_CLK SDIO_DATAx Open-drain driving Push-pull driving 1 Product Folder Link(s): TWL1200 ns ns µs ns µs ns ns ns ns ns Mbps 50 MHz 60 Mbps Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated UNIT MAX 11 TWL1200 SCES786 – JUNE 2009...................................................................................................................................................................................................... www.ti.com SWITCHING CHARACTERISTICS VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCCB = 1.8 V ± 0.15 V MIN Push-pull driving SDIO_CMD(A) SDIO_CMD(B) 7 Open-drain driving (H-to-L) 1.1 7 Open-drain driving (L-to-H) 30 510 Push-pull driving SDIO_CMD(B) tpd ten tdis trA SDIO_CMD(A) SDIO_CLK(A) SDIO_CLK(B) SDIO_DATAx(A) SDIO_DATAx(B) SDIO_DATAx(B) SDIO_DATAx(A) Buffered input 2-mA drive strength output Buffered input Buffered -nput OE OE 6.5 1 7 Push-pull driving 7 4-mA drive strength output Push-pull driving 1 7 8-mA drive strength output Push-pull driving 1 6.5 2-mA drive strength output Push-pull driving 16 4-mA drive strength output Push-pull driving 19 8-mA drive strength output Push-pull driving 19 Switch-type output Push-pull driving 1 2-mA drive strength output Push-pull driving 17 4-mA drive strength output Push-pull driving 16 8-mA drive strength output Push-pull driving 16 Switch-type output Push-pull driving SDIO_CMD(A) rise time SDIO_CLK(B) rise time SDIO_CMD(A) fall time SDIO_CMD(B) fall time SDIO_CLK(B) fall time SDIO_DATAx(B) fall time Push-pull driving Open-drain driving 1 1 15 420 Push-pull driving 1 4.25 Push-pull driving 1 9.5 Open-drain driving 15 420 0.5 5.9 1 9.6 Push-pull driving 0.7 8.2 Open-drain driving 1.6 8.2 Push-pull driving 1 8.2 Push-pull driving 1 9.2 1.6 10.8 0.5 5.2 1 9.8 Push-pull driving Open-drain driving Push-pull driving Push-pull driving 0.4 SDIO Ch-B to Ch-A skew Push-pull driving 0.4 SDIO Channel-to-Clock skew Push-pull driving 1.3 Push-pull driving 60 Max data rate SDIO_CLK SDIO_DATAx Open-drain driving Push-pull driving Submit Documentation Feedback ns ns µs ns µs 4.25 SDIO Ch-A to Ch-B skew SDIO_CMD 12 1 7.6 SDIO_DATAx(A) fall time tsk(O) 515 1 SDIO_DATAx(B) rise time tfB 7.5 30 Push-pull driving SDIO_CMD(B) rise time tfA 1 Open-drain driving (L-to-H) 1 SDIO_DATAx(A) rise time trB 7 Open-drain driving (H-to-L) Push-pull driving UNIT MAX 1 ns ns ns ns ns Mbps 50 MHz 60 Mbps Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 TWL1200 www.ti.com...................................................................................................................................................................................................... SCES786 – JUNE 2009 OPERATING CHARACTERISTICS TA = 25°C PARAMETER Enabled DATAx and CMD Disabled Enabled Clock Disabled Enabled 2-mA buffer Disabled Enabled 4-mA buffer Disabled Enabled 8-mA buffer Disabled Enabled 4-mA I/O Disabled TEST CONDITIONS Cpd input side Cpd output side Cpd input side CL = 0, f = 10 MHz, tr = tf = 1 ns Cpd output side Cpd input side VCCA = VCCB = 1.8 V VCCA = VCCB = 2.5 V 18.3 20.3 18.25 19.52 0.8 0.8 0.1 0.1 0.6 0.9 8.8 10.1 0.1 0.1 0.1 0.1 0.6 1.0 7.1 7.9 0.1 0.1 Cpd output side 0.1 0.1 Cpd input side 0.6 1.0 7.6 8.6 0.1 0.1 Cpd output side 0.1 0.1 Cpd input side 0.6 1.0 8.8 10.1 0.1 0.1 Cpd output side Cpd input side CL = 0, f = 10 MHz, tr = tf = 1 ns Cpd output side Cpd input side Cpd output side Cpd input side Cpd output side Cpd input side Cpd output side Cpd input side CL = 0, f = 10 MHz, tr = tf = 1 ns CL = 0, f = 10 MHz, tr = tf = 1 ns CL = 0, f = 10 MHz, tr = tf = 1 ns Cpd output side 0.1 0.1 Cpd input side 0.6 0.95 8.2 9.1 0.1 0.1 0.1 0.1 Cpd output side Cpd input side CL = 0, f = 10 MHz, tr = tf = 1 ns Cpd output side Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 UNIT pF pF pF pF pF pF 13 TWL1200 SCES786 – JUNE 2009...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 0.25 0.28 Sw itch Type V CCA = V CCB = 1.8 V V IN = 0.15 V 0.24 0.26 0.23 0.25 0.22 0.24 TA = 85°C TA = 85°C 0.23 0.21 TA = 25°C V OL (V) V OL (V) Sw itch Type V CCA = V CCB = 2.6 V V IN = 0.15 V 0.27 0.20 TA = -40°C 0.19 TA = 25°C 0.22 0.21 TA = -40°C 0.20 0.19 0.18 0.18 0.17 0.17 0.16 0.16 0.15 0.15 0 20 40 60 80 100 120 140 160 180 200 220 0 30 60 90 120 150 180 210 240 270 300 IOL (µA) Figure 1. IOL (µA) Figure 2. LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 0.10 0.09 0.10 2-m A Buffer Type V CCA = V CCB = 1.8 V V IN = 0.0 V 0.09 0.08 2-m A Buffer Type V CCA = V CCB = 2.6 V V IN = 0.0 V 0.08 TA = 85°C 0.07 0.07 0.06 0.06 TA = 25°C V OL (V) V OL (V) TA = 85°C 0.05 0.04 0.05 TA = 25°C 0.04 TA = -40°C 0.03 0.03 0.02 0.02 0.01 0.01 0.00 0.00 0.0 14 TA = -40°C 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.6 0.8 1.0 IOL (m A) IOL (m A) Figure 3. Figure 4. Submit Documentation Feedback 1.2 1.4 1.6 1.8 2.0 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 TWL1200 www.ti.com...................................................................................................................................................................................................... SCES786 – JUNE 2009 TYPICAL CHARACTERISTICS (continued) LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 0.15 0.15 4-m A Buffer Type V CCA = V CCB = 1.8 V V IN = 0.0 V 0.14 0.13 0.13 0.12 0.12 0.11 TA = 85°C 0.10 0.10 0.09 0.09 V OL (V) V OL (V) 0.11 TA = 25°C 0.08 0.07 TA = 85°C 0.08 0.07 TA = 25°C 0.06 0.06 TA = -40°C 0.05 0.05 0.04 0.04 0.03 0.03 0.02 0.02 0.01 0.01 0.00 TA = -40°C 0.00 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 IOL (m A) Figure 5. IOL (m A) Figure 6. LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 0.20 3.6 4.0 7.2 8.0 0.20 8-m A Buffer Type V CCA = V CCB = 1.8 V V IN = 0.0 V 0.18 8-m A Buffer Type V CCA = V CCB = 2.6 V V IN = 0.0 V 0.18 0.16 0.16 0.14 0.14 TA = 85°C 0.12 V OL (V) 0.12 V OL (V) 4-m A Buffer Type V CCA = V CCB = 2.6 V V IN = 0.0 V 0.14 TA = 25°C 0.10 0.08 TA = 85°C 0.10 TA = 25°C 0.08 0.06 0.06 TA = -40°C 0.04 0.04 0.02 0.02 0.00 TA = -40°C 0.00 0.0 0.8 1.6 2.4 3.2 4.0 4.8 5.6 6.4 7.2 8.0 0.0 0.8 IOL (m A) Figure 7. 1.6 2.4 3.2 4.0 4.8 5.6 6.4 IOL (m A) Figure 8. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 15 TWL1200 SCES786 – JUNE 2009...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 1.81 2.61 Sw itch Type V CCA = V CCB = 1.8 V V IN = 1.8 V 1.80 1.79 2.60 2.59 1.78 2.58 1.77 2.57 TA = -40°C 1.76 V OH (V) V OH (V) Sw itch Type V CCA = V CCB = 2.6 V V IN = 2.6 V 1.75 TA = 25°C 2.56 TA = -40°C 2.55 TA = 25°C 1.74 2.54 TA = 85°C 1.73 1.72 2.52 1.71 2.51 1.70 -20 -18 -16 -14 -12 TA = 85°C 2.53 -10 -8 -6 -4 -2 2.50 -20 0 -18 -16 -14 -12 IOH (µA) 1.79 -8 -6 Figure 9. HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT -4 -2 0 2.61 1.81 1.80 -10 IOH (µA) Figure 10. 2-m A Buffer Type V CCA = V CCB = 1.8 V V IN = 1.8 V 2.60 2.59 2-m A Buffer Type V CCA = V CCB = 2.6 V V IN = 2.6 V 1.78 2.58 1.77 2.57 TA = -40°C V OH (V) V OH (V) 1.76 1.75 1.74 TA = 25°C 1.73 1.72 2.56 TA = 25°C 2.55 2.54 TA = 85°C TA = -40°C TA = 85°C 2.53 1.71 2.52 1.70 1.69 2.51 1.68 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 2.50 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 IOH (m A) IOH (m A) Figure 12. Figure 11. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 TWL1200 www.ti.com...................................................................................................................................................................................................... SCES786 – JUNE 2009 TYPICAL CHARACTERISTICS (continued) 1.81 1.80 4-m A Buffer Type 1.79 V CCA = V CCB = 1.8 V 1.78 V IN = 1.8 V 1.77 1.76 1.75 1.74 TA = -40°C 1.73 1.72 1.71 TA = 25°C 1.70 1.69 TA = 85°C 1.68 1.67 1.66 1.65 1.64 1.63 -4.0 -3.6 -3.2 -2.8 -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0.0 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 2.61 2.60 2.59 2.57 1.77 2.51 2.50 2.49 2.48 -4.0 -3.6 -3.2 -2.8 -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0.0 IOH (m A) Figure 14. HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 2.61 8-m A Buffer Type V CCA = V CCB = 1.8 V V IN = 1.8 V 2.59 8-m A Buffer Type V CCA = V CCB = 2.6 V V IN = 2.6 V 2.57 2.55 TA = -40°C 2.53 V OH (V) V OH (V) TA = 85°C IOH (m A) Figure 13. 1.69 TA = 25°C TA = -40°C 2.51 TA = 25°C 2.49 1.65 1.63 TA = 25°C 2.54 2.52 1.73 1.67 2.55 2.53 1.75 1.71 TA = -40°C 2.56 1.81 1.79 4-m A Buffer Type V CCA = V CCB = 2.6 V V IN = 2.6 V 2.58 V OH (V) V OH (V) HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 2.47 TA = 85°C 1.61 TA = 85°C 2.45 1.59 2.43 1.57 1.55 -8.0 -7.2 -6.4 -5.6 -4.8 -4.0 -3.2 -2.4 -1.6 -0.8 0.0 2.41 -8.0 -7.2 -6.4 -5.6 -4.8 -4.0 -3.2 -2.4 -1.6 -0.8 0.0 IOH (m A) Figure 16. IOH (m A) Figure 15. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 17 TWL1200 SCES786 – JUNE 2009...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) PROPAGATION DELAY TIME (HIGH TO LOW) vs LOAD CAPACITANCE PROPAGATION DELAY TIME (LOW TO HIGH) vs LOAD CAPACITANCE 6 6 Sw itch Type TA = -40°C 5 5 4 4 t PD(L-H) (ns) t PD(H-L) (ns) Sw itch Type TA = -40°C V CCA = V CCB = 1.8 V 3 V CCA = V CCB = 1.8 V 3 2 2 V CCA = V CCB = 2.6 V V CCA = V CCB = 2.6 V 1 1 0 0 0 10 20 30 40 50 0 60 30 40 50 60 CL (pF) Figure 18. PROPAGATION DELAY TIME (HIGH TO LOW) vs LOAD CAPACITANCE PROPAGATION DELAY TIME (LOW TO HIGH) vs LOAD CAPACITANCE 6 Sw itch Type TA = 25°C Sw itch Type TA = 25°C 5 5 4 4 t PD(L-H) (ns) V CCA = V CCB = 1.8 V 3 2 V CCA = V CCB = 1.8 V 3 2 V CCA = V CCB = 2.6 V V CCA = V CCB = 2.6 V 1 1 0 0 0 10 20 30 40 50 60 0 10 CL (pF) 20 30 40 50 60 CL (pF) Figure 20. Figure 19. 18 20 CL (pF) Figure 17. 6 t PD(H-L) (ns) 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 TWL1200 www.ti.com...................................................................................................................................................................................................... SCES786 – JUNE 2009 TYPICAL CHARACTERISTICS (continued) PROPAGATION DELAY TIME (HIGH TO LOW) vs LOAD CAPACITANCE PROPAGATION DELAY TIME (LOW TO HIGH) vs LOAD CAPACITANCE 6 6 Sw itch Type TA = 85°C Sw itch Type TA = 85°C 5 5 V CCA = V CCB = 1.8 V 4 t PD(L-H) (ns) t PD(H-L) (ns) 4 3 2 V CCA = V CCB = 1.8 V 3 2 V CCA = V CCB = 2.6 V V CCA = V CCB = 2.6 V 1 1 0 0 0 10 20 30 40 50 60 0 10 CL (pF) 20 30 40 50 60 Submit Documentation Feedback 19 CL (pF) Figure 22. Figure 21. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 TWL1200 SCES786 – JUNE 2009...................................................................................................................................................................................................... www.ti.com Typical Application Wiring for TWL1200 When Connecting to the WL1271 Table 1. WL1271+TWL1200 Interface HOST (MSM) 20 PIN NAME BALL NO. TYPE TYPE BALL NO. PIN NAME WL1271 COB VCCA C4 Power (3.0 V) Power (1.8 V) C5 VCCB VCCA D4 Power (3.0 V) Power (1.8 V) D5 VCCB SDIO_DATA0(A) B2 I/O ↔ I/O ↔ B6 SDIO_DATA0(B) K4 SDIO_DATA1(A) C2 I/O ↔ I/O ↔ C6 SDIO_DATA1(B) J4 SDIO_DATA2(A) C1 I/O ↔ I/O ↔ C7 SDIO_DATA2(B) J3 SDIO_DATA3(A) B1 I/O ↔ I/O ↔ B7 SDIO_DATA3(B) J5 SDIO_CMD(A) A2 I/O ↔ I/O ↔ A6 SDIO_CMD(B) L3 SDIO_CLK(A) A1 I→ O→ A7 SDIO_CLK(B) M3 WLAN_EN(A) D1 I→ O→ D6 WLAN_EN(B) J2 WLAN_IRQ(A) D2 O← I← D7 WLAN_IRQ(B) G4 CLK_REQ(A) E1 O← I← E7 CLK_REQ(B) F5 BT_EN(A) E2 I→ O→ E6 BT_EN(B) G5 BT_UART_RX(A) G1 I→ O→ G7 BT_UART_RX(B) G7 BT_UART_CTS(A) F1 I→ O→ F7 BT_UART_CTS(B) E11 TWL1200 BT_UART_TX(A) G2 O← I← G6 BT_UART_TX(B) G8 BT_UART_RTS(A) F2 O← I← F6 BT_UART_RTS(B) G11 AUDIO_IN(A) F3 I→ I/O ↔ F5 AUDIO_IN(B) F6 AUDIO_CLK(A) A3 I/O ↔ I/O ↔ A5 AUDIO_CLK(B) F8 AUDIO_F-SYN(A) B3 I/O ↔ I/O ↔ B5 AUDIO_F-SYN(B) H11 AUDIO_OUT(A) G3 O← I← G5 AUDIO_OUT(B) F7 SLOW_CLK(A) G4 I→ O→ F4 SLOW_CLK(B) K9 AUD_DIR A4 I→ GND D3 GND OE B4 active low E3 GND E4 GND E5 GND Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 TWL1200 www.ti.com...................................................................................................................................................................................................... SCES786 – JUNE 2009 PARAMETER MEASUREMENT INFORMATION 2 × VCCO S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCCO GND RL tw LOAD CIRCUIT FOR BUFFER-TYPE OUTPUTS VCCI VCCI/2 Input VCCO CL RL VTP 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 15 pF 15 pF 15 pF 2 kΩ 2 kΩ 2 kΩ 0.15 V 0.15 V 0.3 V VCCI/2 0V VOLTAGE WAVEFORMS PULSE DURATION VCCA Output Control (low-level enabling) VCCA/2 VCCA/2 0V tPZL VCCI Input VCCI/2 VCCI/2 0V tPLH Output tPHL VOH VCCO/2 VOL VCCO/2 tPLZ VCCO Output Waveform 1 S1 at 2 × VCCO (see Note B) VCCO/2 VOL + VTP VOL tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHZ VCCO/2 VOH − VTP VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. VCCI is the VCC associated with the input port. I. VCCO is the VCC associated with the output port. Figure 23. Push-Pull Buffered Direction Control Load Circuit and Voltage Waveform Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 21 TWL1200 SCES786 – JUNE 2009...................................................................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VCCI VCCO VCCI VCCO DUT IN DUT IN OUT 15 pF OUT 1 MW 15 pF 1 MW DATA RATE, PULSE DURATION, PROPAGATION DELAY, OUTPUT RISE AND FALL TIME MEASUREMENT USING AN OPEN-DRAIN DRIVER DATA RATE, PULSE DURATION, PROPAGATION DELAY, OUTPUT RISE AND FALL TIME MEASUREMENT USING A PUSH-PULL DRIVER From Output Under Test 15 pF 1 MW LOAD CIRCUIT FOR ENABLE/DISABLE TIME MEASUREMENT − SWITCH-TYPE SDIOs tw VCCI VCCI/2 Input VCCI/2 0V VOLTAGE WAVEFORMS PULSE DURATION OE VCCI Input VCCI/2 VCCI/2 Input 0V tPLH Output tPHL VCCO/2 0.9 y VCCO 0.1 y VCCO tr VOH VCCO/2 VOL tf Output ten tdis VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. VCCI is the VCC associated with the input port. I. VCCO is the VCC associated with the output port. J. All parameters and waveforms are not applicable to all devices. Figure 24. Auto-Direction Control Load Circuit and Voltage Waveform 22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 TWL1200 www.ti.com...................................................................................................................................................................................................... SCES786 – JUNE 2009 APPLICATION CIRCUIT EXAMPLES VCCB VCCA C C TWL1200 C4 D4 C5 D5 BT_PCM30_DO BT_PCM_DO F3 F5 BT_PCM30_CLK BT_PCM_CLK A3 A5 BT_PCM30_SYNC BT_PCM_SYNC B3 B5 A4 VCCA VCCA VCCB VCCB AUDIO_IN(A) AUDIO_IN(B) CLK_REQ(A) CLK_REQ(B) SDIO_CLK(A) SDIO_CLK(B) SDIO_CMD(A) SDIO_CMD(B) AUDIO_CLK(A) AUDIO_CLK(B) SDIO_DATA0(A) SDIO_DATA1(A) AUDIO_F-SYN(A) SDIO_DATA2(A) AUDIO_F-SYN(B) SDIO_DATA3(A) AUD_DIR SDIO_DATA0(B) SDIO_DATA1(B) SDIO_DATA2(B) SDIO_DATA3(B) BT_PCM30_DI BT_PCM_DI G3 G5 BT_EN30 BT_EN E2 E6 BT_EN(A) BT_EN(B) BT_UART30_RTS BT_UART_RTS F1 F7 BT_UART_CTS(A) BT_UART_CTS(B) WLAN_EN(A) WLAN_EN(B) BT_IRQ30 BT_UART30_CTS BT_UART_CTS F2 F6 BT_UART_RTS(A) BT_UART_RTS(B) WLAN_IRQ(A) WLAN_IRQ(B) BT_UART30_TXD BT_UART_TXD G1 G7 BT_UART30_RXD BT_UART_RXD G2 G6 B4 AUDIO_OUT(A) AUDIO_OUT(B) SLOW_CLK(A) SLOW_CLK(B) E1 E7 A1 A7 A2 A6 B2 C2 C1 B1 B6 C6 C7 B7 G4 F4 D1 D6 D2 D7 WLAN_SDIO30_CLK WLAN_SDIO_CLK WLAN_SDIO30_CMD WLAN_SDIO_CMD WLAN_SDIO30_D0 WLAN_SDIO30_D1 WLAN_SDIO30_D2 WLAN_SDIO30_D3 WLAN_SDIO_D0 WLAN_SDIO_D1 WLAN_SDIO_D2 WLAN_SDIO_D3 CLK32_COMBO CLK32_COMBO18 WLAN_EN30 WLAN_EN WLAN_IRQ30 WLAN_IRQ BT_UART_RX(A) BT_UART_RX(B) BT_UART_TX(A) BT_UART_TX(B) OE GND GND GND GND D3 E3 E4 E5 R Figure 25. Application Circuit Example, OE Connection With Audio_CLK and Audio_F-SYNC Channels Established From B Side to A Side Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 23 TWL1200 SCES786 – JUNE 2009...................................................................................................................................................................................................... www.ti.com VCCB C VCCA C TWL1200 C4 D4 C5 D5 BT_PCM30_DO BT_PCM_DO F3 F5 BT_PCM30_CLK BT_PCM_CLK A3 A5 BT_PCM30_SYNC BT_PCM_SYNC B3 B5 VCCA R A4 R VCCA VCCA VCCB VCCB AUDIO_IN(A) AUDIO_IN(B) CLK_REQ(A) CLK_REQ(B) SDIO_CLK(A) SDIO_CLK(B) SDIO_CMD(A) SDIO_CMD(B) AUDIO_CLK(A) AUDIO_CLK(B) SDIO_DATA0(A) SDIO_DATA1(A) AUDIO_F-SYN(A) SDIO_DATA2(A) AUDIO_F-SYN(B) SDIO_DATA3(A) AUD_DIR SDIO_DATA0(B) SDIO_DATA1(B) SDIO_DATA2(B) SDIO_DATA3(B) BT_PCM30_DI BT_PCM_DI G3 G5 BT_EN30 BT_EN E2 E6 BT_EN(A) BT_EN(B) BT_UART30_RTS BT_UART_RTS F1 F7 BT_UART_CTS(A) BT_UART_CTS(B) WLAN_EN(A) WLAN_EN(B) BT_UART30_CTS BT_UART_CTS F2 F6 BT_UART_RTS(A) BT_UART_RTS(B) WLAN_IRQ(A) WLAN_IRQ(B) BT_UART30_TXD BT_UART_TXD G1 G7 BT_UART30_RXD BT_UART_RXD G2 G6 B4 BT_WLAN_LEVEL_EN AUDIO_OUT(A) AUDIO_OUT(B) SLOW_CLK(A) SLOW_CLK(B) E1 E7 A1 A7 A2 A6 B2 C2 C1 B1 B6 C6 C7 B7 G4 F4 D1 D6 D2 D7 WLAN_SDIO30_CLK WLAN_SDIO_CLK WLAN_SDIO30_CMD WLAN_SDIO_CMD WLAN_SDIO30_D0 WLAN_SDIO30_D1 WLAN_SDIO30_D2 WLAN_SDIO30_D3 WLAN_SDIO_D0 WLAN_SDIO_D1 WLAN_SDIO_D2 WLAN_SDIO_D3 CLK32_COMBO CLK32_COMBO18 WLAN_EN30 WLAN_EN WLAN_IRQ30 WLAN_IRQ BT_UART_RX(A) BT_UART_RX(B) BT_UART_TX(A) BT_UART_TX(B) OE GND GND GND GND D3 E3 E4 E5 R VCCB Figure 26. Application Circuit Example, With Voltage Divider for AUD_DIR Connection 24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 TWL1200 www.ti.com...................................................................................................................................................................................................... SCES786 – JUNE 2009 PRINCIPLES OF OPERATION Applications The TWL1200 device has been designed to bridge the digital-switching compatibility gap between two voltage nodes to successfully interface logic threshold levels between a host processor and the Texas Instruments Wi-Link-6 WLAN/BT/FM products. It is intended to be used in a point-to-point topology when interfacing these devices that may or may not be operating at different interface voltages. Architecture The BT/UART and PCM/Audio subsystem interfaces consist of a fully-buffered voltage translator design that has its output transistors to source and sink current optimized for drive strength. The SDIO lines comprise a semi-buffered auto-direction-sensing based translator architecture (see Figure 27) that does not require a direction-control signal to control the direction of data flow of the A to B ports (or from B to A ports). VCCA VCCB R1 One-Shot T1 One-Shot T2 R2 Translator SDIO-DATAx(A) SDIO-DATAx(B) Bias N1 T3 One-Shot Translator T4 One-Shot Figure 27. Architecture of an SDIO Switch-Type Cell Each of these bidirectional SDIO channels independently determines the direction of data flow without a direction-control signal. Each I/O pin can be automatically reconfigured as either an input or an output, which is how this auto-direction feature is realized. The following two key circuits are employed to facilitate the "switch-type" voltage translation function: 1. Integrated pullup resistors to provide dc-bias and drive capabilities 2. An N-channel pass-gate transistor topology (with a high RON of ~300 Ω) that ties the A-port to the B-port 3. Output one-shot (O.S.) edge-rate accelerator circuitry to detect and accelerate rising edges on the A or B ports Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 25 TWL1200 SCES786 – JUNE 2009...................................................................................................................................................................................................... www.ti.com For bidirectional voltage translation, pullup resistors are included on the device for dc current sourcing capability. The VGATE gate bias of the N-channel pass transistor is set at a level that optimizes the switch characteristics for maximum data rate as well as minimal static supply leakage. Data can flow in either direction without guidance from a control signal. The edge-rate acceleration circuitry speeds up the output slew rate by monitoring the input edge for transitions, helping maintain the data rate through the device. During a low-to-high signal rising-edge, the O.S. circuits turn on the PMOS transistors (T1, T3) and its associated driver output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase to increase the current drive capability of the driver for approximately 30 ns or 95% of the input edge, whichever occurs first. This edge-rate acceleration provides high ac drive by bypassing the internal pullup resistors during the low-to-high transition to speed up the rising-edge signal. During a high-to-low signal falling-edge, the O.S. circuits turn on the NMOS transistors (T2, T4) and its associated driver output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase to increase the current drive capability of the driver for approximately 30 ns or 95% of the input edge, whichever occurs first. To minimize dynamic ICC and the possibility of signal contention, the user should wait for the O.S. circuit to turn-off before applying a signal in the opposite direction. The worst-case duration is equal to the minimum pulse-width number provided in the Timing Requirements section of this data sheet. Once the O.S. is triggered and switched off, both the A and B ports must go to the same state (i.e. both High or both Low) for the one-shot to trigger again. In a DC state, the output drivers maintain a Low state through the pass transistor. The output drivers maintain a High through the "smart pullup resistors" that dynamically change value based on whether a Low or a High is being passed through the SDIO lines, as follows: • RPU1 and RPU2 values are 25 kΩ when the output is driving a low • RPU1 and RPU2 values are 4 kΩ when the output is driving a high • RPU1 and RPU2 values are 70 kΩ when the device is disabled via the OE pin or by pulling the either VCCA or VCCB to 0 V. The reason for using these "smart" pullup resistors is to allow the TWL1200 to realize a lower static power consumption (when the I/Os are low), support lower VOL values for the same size pass-gate transistor, and improved simultaneous switching performance. Input Driver Requirements The continuous dc-current "sinking" capability is determined by the external system-level driver interfaced to the SDIO pins. Since the high bandwidth of these bidirectional SDIO circuits necessitates the need for a port to quickly change from an input to an output (and vice-vera), they have a modest dc-current "sourcing" capability of hundreds of micro-Amps, as determined by the smart pullup resistor values. The fall time (tfA, tfB) of a signal depends on the edge rate and output impedance of the external device driving the SDIO I/Os, as well as the capacitive loading on these lines. Similarly, the tpd and max data rates also depend on the output impedance of the external driver. The values for tfA, tfB, tpd, and maximum data rates in the data sheet assume that the output impedance of the external driver is less than 50 Ω. Output Load Considerations TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay on for approximately 30 ns. The maximum capacitance of the lumped load that can be driven also depends directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC, load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the capacitance that the TWL1200 SDIO output sees, so it is recommended that this lumped-load capacitance be considered and kept below 75 pF to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level affects. 26 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TWL1200 PACKAGE OPTION ADDENDUM www.ti.com 29-Jun-2009 PACKAGING INFORMATION Orderable Device Status (1) TWL1200ZQCR ACTIVE Package Type BGA MI CROSTA R JUNI OR Package Drawing ZQC Pins Package Eco Plan (2) Qty 48 2500 Green (RoHS & no Sb/Br) Lead/Ball Finish SNAGCU MSL Peak Temp (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device TWL1200ZQCR Package Package Pins Type Drawing BGA MI CROSTA R JUNI OR ZQC 48 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 4.3 4.3 1.5 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TWL1200ZQCR BGA MICROSTAR JUNIOR ZQC 48 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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