TI PCA9538DB

PCA9538
www.ti.com ................................................................................................................................................ SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
FEATURES
1
RGV PACKAGE
(TOP VIEW)
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
SDA
SCL
INT
P7
P6
P5
P4
16 15 14 13
RESET 1
12 SCL
P0 2
11
P1 3
10 P7
P2 4
9 P6
5
6
7
8
P5
2
P4
16
GND
1
P3
A0
A1
RESET
P0
P1
P2
P3
GND
RGT PACKAGE
(TOP VIEW)
A1
A0
VCC
SDA
A1
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
•
INT
RESET
P0
P1
P2
16 15 14 13
12 SCL
2
11 INT
10 P7
3
1
9 P6
4
5 6 7
8
P3
GND
P4
P5
•
•
•
Power-Up With All Channels Configured as
Inputs
No Glitch on Power Up
Noise Filter on SCL/SDA Inputs
Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SDA
•
•
•
•
•
•
VCC
•
•
•
•
•
Low Standby Current Consumption of
1 µA Max
I2C to Parallel Port Expander
Open-Drain Active-Low Interrupt Output
Active-Low Reset Input
Operating Power-Supply Voltage Range of
2.3 V to 5.5 V
5-V Tolerant I/O Ports
400-kHz Fast I2C Bus
Two Hardware Address Pins Allow up to Four
Devices on the I2C/SMBus
Input/Output Configuration Register
Polarity Inversion Register
A0
•
DESCRIPTION/ORDERING INFORMATION
This 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3-V to 5.5-V VCC operation. It
provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock
(SCL), serial data (SDA)].
The PCA9538 consists of one 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity
Inversion (active high or active low) registers. At power on, the I/Os are configured as inputs. However, the
system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port
register can be inverted with the Polarity Inversion register. All registers can be read by the system master.
The system master can reset the PCA9538 in the event of a timeout or other improper operation by asserting a
low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus
state machine. The RESET pin causes the same reset/initialization to occur without powering down the part.
The PCA9538 open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2008, Texas Instruments Incorporated
PCA9538
SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ................................................................................................................................................ www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the PCA9538 can remain a simple slave device.
The device outputs (latched) have high-current drive capability for directly driving LEDs. It has low current
consumption.
Two hardware pins (A0 and A1) are used to program and vary the fixed I2C address and allow up to four devices
to share the same I2C bus or SMBus.
ORDERING INFORMATION
PACKAGE (1) (2)
TA
TOP-SIDE MARKING
Reel of 3000
PCA9538RGTR
ZWZ
QFN – RGV
Reel of 2500
PCA9538RGVR
PREVIEW
QSOP – DBQ
Reel of 2500
PCA9538DBQR
PD538
Tube of 40
PCA9538DW
Reel of 2000
PCA9538DWR
Reel of 2000
PCA9538DBR
Tube of 80
PCA9538DB
Tube of 90
PCA9538PW
Reel of 2000
PCA9538PWR
Reel of 2000
PCA9538DGVR
SOIC – DW
–40°C to 85°C
SSOP – DB
TSSOP – PW
TVSOP – DGV
(1)
(2)
ORDERABLE PART NUMBER
QFN – RGT
PCA9538
PD538
PD538
PD538
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
TERMINAL FUNCTIONS
NO.
QSOP (DBQ),
SSOP (DB),
TSSOP (PW), OR
TVSOP (DGV)
QFN (RGT) OR
QFN (RGV)
NAME
1
15
A0
Address input. Connect directly to VCC or ground.
2
16
A1
Address input. Connect directly to VCC or ground.
3
1
RESET
4
2
P0
P-port input/output. Push-pull design structure.
5
3
P1
P-port input/output. Push-pull design structure.
6
4
P2
P-port input/output. Push-pull design structure.
7
5
P3
P-port input/output. Push-pull design structure.
8
6
GND
9
7
P4
P-port input/output. Push-pull design structure.
10
8
P5
P-port input/output. Push-pull design structure.
11
9
P6
P-port input/output. Push-pull design structure.
12
10
P7
P-port input/output. Push-pull design structure.
13
11
INT
Interrupt output. Connect to VCC through a pullup resistor.
14
12
SCL
Serial clock bus. Connect to VCC through a pullup resistor.
15
13
SDA
Serial data bus. Connect to VCC through a pullup resistor.
16
14
VCC
Supply voltage
2
DESCRIPTION
Active-low reset input. Connect to VCC through a pullup resistor if no active
connection is used.
Ground
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www.ti.com ................................................................................................................................................ SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008
FUNCTIONAL BLOCK DIAGRAM
INT
A0
A1
SCL
SDA
RESET
VCC
GND
A.
13
Interrupt
Logic
LP Filter
1
2
P7−P0
14
15
Input
Filter
I2C Bus
Control
Shift
Register
8
I/O
Port
Write Pulse
3
16
8 Bits
Power-On
Reset
Read Pulse
Pin numbers shown are for the DB, DBQ, DGV, DW, or PW package.
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PCA9538
SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ................................................................................................................................................ www.ti.com
SIMPLIFIED SCHEMATIC OF P0 TO P7
Data From
Shift Register
Data From
Shift Register
Output Port
Register Data
Configuration
Register
D
VCC
Q1
Q
FF
Write Configuration
Pulse
CK Q
Write Pulse
D
Q
FF
P0 to P7
CK Q
Q2
Output Port
Register
Input Port
Register
D
Q
FF
Read Pulse
Data From
Shift Register
ESD Protection
Diode
GND
Input Port
Register Data
CK Q
To INT
D
Polarity
Register Data
Q
FF
Write Polarity
Pulse
CK Q
Polarity
Inversion
Register
A.
At power-on reset, all registers return to default values.
I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input
voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In
this case, there are low impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address byte
is sent, most significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A1) of the slave device must
not be changed between the Start and the Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 2).
4
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A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 1).
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver will signal an end of data to the slave transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 1. Definition of Start and Stop Conditions
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 2. Bit Transfer
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PCA9538
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Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 3. Acknowledgment on I2C Bus
Interface Definition Table
BYTE
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
I2C slave address
H
H
H
L
L
A1
A0
R/W
Px I/O data bus
P7
P6
P5
P4
P3
P2
P1
P0
Device Address
Figure 4 shows the address byte of the PCA9538.
Slave Address
1
1
1
Fixed
0
0
A1
A0 R/W
Hardware
Selectable
Figure 4. PCA9538 Address
Address Reference Table
INPUTS
A1
6
A0
I2C BUS SLAVE ADDRESS
L
L
112 (decimal), 70 (hexadecimal)
L
H
113 (decimal), 71 (hexadecimal)
H
L
114 (decimal), 72 (hexadecimal)
H
H
115 (decimal), 73 (hexadecimal)
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The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected while a low (0) selects a write operation.
Control Register and Command Byte
Following the successful Acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9538 (see Figure 5). Two bits of this command byte state the operation
(read or write) and the internal register (input, output, polarity inversion or configuration) that will be affected. This
register can be written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a
new command byte has been sent.
0
0
0
0
0
0
B1
B0
Figure 5. Control Register Bits
Command Byte Table
CONTROL REGISTER BITS
B1
B0
COMMAND BYTE
(HEX)
0
0
0x00
0
1
0x01
1
0
0x02
1
1
0x03
REGISTER
PROTOCOL
POWER-UP DEFAULT
Input Port
Read byte
XXXX XXXX
Output Port
Read/write byte
1111 1111
Polarity Inversion
Read/write byte
0000 0000
Configuration
Read/write byte
1111 1111
Register Descriptions
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the
Input Port register is accessed next.
Register 0 (Input Port Register) Table
BIT
I7
I6
I5
I4
I3
I2
I1
I0
DEFAULT
X
X
X
X
X
X
X
X
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Register 1 (Output Port Register) Table
BIT
O7
O6
O5
O4
O3
O2
O1
O0
DEFAULT
1
1
1
1
1
1
1
1
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin original polarity is retained.
Register 2 (Polarity Inversion Register) Table
BIT
N7
N6
N5
N4
N3
N2
N1
N0
DEFAULT
0
0
0
0
0
0
0
0
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The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Register 3 (Configuration Register) Table
BIT
C7
C6
C5
C4
C3
C2
C1
C0
DEFAULT
1
1
1
1
1
1
1
1
Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9538 in a reset condition until
VCC has reached VPOR. At that point, the reset condition is released and the PCA9538 registers and SMBus/I2C
state machine will initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back
up to the operating voltage for a power-reset cycle.
RESET Input
The RESET input can be asserted to reset the system while keeping the VCC at its operating level. A reset can
be accomplished by holding the RESET pin low for a minimum of tW. The PCA9538 registers and I2C/SMBus
state machine are changed to their default states once RESET is low (0). Once RESET is high (1), the I/O levels
at the P port can be changed externally or through the master. This input requires a pullup resistor to VCC if no
active connection is used.
Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting,
data is read from the port that generated the interrupt or in a Stop event. Resetting occurs in the read mode at
the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that
occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt
during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the
state of the pin does not match the contents of the Input Port register.
The INT output has an open-drain structure and requires pullup resistor to VCC.
Bus Transactions
Data is exchanged between the master and PCA9538 through write and read commands.
Writes
Data is transmitted to the PCA9538 by sending the device address and setting the least-significant bit (LSB) to a
logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte (see Figure 6 and Figure 7). There is no limitation on
the number of data bytes sent in one write transmission.
8
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SCL
1
2
3
4
5
6
7
8
9
Slave Address
S
SDA
1
1
1
0
Command Byte
0 A1 A0 0
A
0
0
0
0
0
0
0
1
Data 1
A
A
P
ACK From Slave
ACK From Slave
R/W ACK From Slave
Start Condition
Data to Port
Write to Port
Data Out
From Port
Data 1 Valid
tpv
Figure 6. Write to Output Port Register
<br/>
SCL
1
2
3
4
5
6
7
8
9
Slave Address
SDA
S
1
1
1
0
Start Condition
Command Byte
0 A1 A0 0
A
R/W
0
0
0
0
ACK From Slave
0
0
Data to Register
1 1/0 A
Data
ACK From Slave
A
P
ACK From Slave
Data to
Register
Figure 7. Write to Configuration or Polarity Inversion Registers
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Reads
The bus master first must send the PCA9538 address with the LSB set to a logic 0 (see Figure 4 for device
address). The command byte is sent after the address and determines which register is accessed. After a restart,
the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the
command byte then is sent by the PCA9538 (see Figure 8 and Figure 9). After a restart, the value of the register
defined by the command byte matches the register being accessed when the restart occurred. Data is clocked
into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes
received in one read transmission, but when the final byte is received, the bus master must not acknowledge the
data.
S 1
1
1
0
ACK From
Slave
ACK From
Slave
Slave Address
0 A1 A0 0
Command Byte
A
ACK From
ACK From
Master
Slave Data from Register
Slave Address
A S 1
1
1
0
Data
A
Data from Register
NACK From
Master
0 A1 A0 1 A
R/W
R/W
Data
NA P
Last Byte
Figure 8. Read From Register
<br/>
1
SCL
2
3
4
5
6
7
8
9
Data From Port
Slave Address
S 1
SDA
1
1
0
0 A1 A0 1
Start
Condition
R/W
Data 1
A
Data From Port
Data 4
A
ACK From
Master
ACK From
Slave
NA P
NACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
tph
Data 3
Data 4
Data 5
tps
INT
tiv
tir
A.
This figure assumes the command byte has previously been programmed with 00h.
B.
Transfer of data can be stopped at any moment by a Stop condition.
C.
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port. See Figure 8 for these details.
Figure 9. Read From Input Port Register
10
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
6
V
VI
Input voltage range (2)
–0.5
6
V
(2)
VO
Output voltage range
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
IIOK
Input/output clamp current
VO < 0 or VO > VCC
±20
mA
IOL
Continuous output low current
VO = 0 to VCC
50
mA
IOH
Continuous output high current
VO = 0 to VCC
–50
mA
ICC
θJA
–0.5
Continuous current through GND
–250
Continuous current through VCC
160
Package thermal impedance (3)
DB package
82
DBQ package
90
DGV package
86
DW package
46
PW package
88
RGT package
(1)
(2)
(3)
Storage temperature range
V
mA
°C/W
TBD
RGV package
Tstg
6
UNIT
TBD
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
2.3
5.5
0.7 × VCC
5.5
2
5.5
SCL, SDA
–0.5
0.3 × VCC
A0, A1, RESET, P7–P0
–0.5
0.8
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
P7–P0
–10
mA
IOL
Low-level output current
P7–P0
25
mA
TA
Operating free-air temperature
85
°C
SCL, SDA
A0, A1, RESET, P7–P0
–40
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V
V
V
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input diode clamp voltage
II = –18 mA
VPOR
Power-on reset voltage
VI = VCC or GND, IO = 0
IOH = –8 mA
P-port high-level output voltage (2)
VOH
IOH = –10 mA
SDA
VOL = 0.4 V
VOL = 0.5 V
P port (3)
IOL
VOL = 0.7 V
INT
SCL, SDA
II
A0, A1, RESET
VCC
MIN
2.3 V to 5.5 V
–1.2
VPOR
2.3 V
1.8
3V
2.6
4.5 V
4.1
4.75 V
4.1
2.3 V
1.7
3V
2.5
TYP (1)
MAX
1.5
1.65
UNIT
V
V
V
4.5 V
4
4.75 V
4
2.3 V to 5.5 V
3
8
2.3 V
8
10
3V
8
14
4.5 V
8
17
4.75 V
8
35
2.3 V
10
13
3V
10
19
4.5 V
10
24
4.75 V
10
45
VOL = 0.4 V
2.3 V to 5.5 V
3
10
VI = VCC or GND
2.3 V to 5.5 V
mA
±1
±1
µA
IIH
P port
VI = VCC
2.3 V to 5.5 V
1
µA
IIL
P port
VI = GND
2.3 V to 5.5 V
–1
µA
VI = VCC or GND, IO = 0,
I/O = inputs, fscl = 400 kHz, No load
Operating mode
VI = VCC or GND, IO = 0,
I/O = inputs, fscl = 100 kHz, No load
ICC
Standby mode
ΔICC
Ci
Cio
(1)
(2)
(3)
12
Additional current in standby
mode
SCL
SDA
P port
VI = VCC or GND, IO = 0,
I/O = inputs, fscl = 0 kHz, No load
One input at VCC – 0.6 V,
Other inputs at VCC or GND
All LED I/Os at VI = 4.3 V,
fscl = 0 kHz
VI = VCC or GND
VIO = VCC or GND
5.5 V
104
175
3.6 V
50
90
2.7 V
20
65
5.5 V
60
150
3.6 V
15
40
2.7 V
8
20
5.5 V
0.25
1
3.6 V
0.2
0.9
2.7 V
0.1
0.8
2.3 V to 5.5 V
µA
1.5
mA
5.5 V
2.3 V to 5.5 V
2.3 V to 5.5 V
1
4
5
5.5
6.5
8
9.5
pF
pF
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
The total current sourced by all I/Os must be limited to 85 mA.
Each I/O must be externally limited to a maximum of 25 mA, and the P port (P7–P0) must be limited to a maximum current of 200 mA.
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I2C INTERFACE TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted) (see Figure 10)
STANDARD MODE
I2C BUS
MIN
MAX
100
FAST MODE
I2C BUS
UNIT
MIN
MAX
0
400
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
0.6
µs
tscl
I2C clock low time
4.7
1.3
µs
2
tsp
I C spike time
tsds
I2C serial-data setup time
50
tsdh
I2C serial-data hold time
ticr
I2C input rise time
50
250
100
0
0
kHz
ns
ns
ns
1000
20 + 0.1Cb (1)
300
ns
300
20 + 0.1Cb
(1)
300
ns
300
20 + 0.1Cb (1)
300
2
ticf
I C input fall time
tocf
I2C output fall time
tbuf
I2C bus free time between Stop and Start
4.7
1.3
µs
tsts
I2C Start or repeated Start condition setup
4.7
0.6
µs
tsth
I2C Start or repeated Start condition hold
4
0.6
µs
tsps
I2C Stop condition setup
4
0.6
µs
50
ns
10-pF to 400-pF bus
tvd(data) Valid data time
SCL low to SDA output valid
300
tvd(ack)
Valid data time of ACK condition
ACK signal from SCL low to
SDA (out) low
0.3
Cb
I2C bus capacitive load
(1)
3.45
0.1
400
ns
0.9
µs
400
ns
Cb = Total capacitance of one bus in pF
RESET TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted)
STANDARD MODE
I2C BUS
PARAMETER
MIN
FAST MODE
I2C BUS
MAX
MIN
UNIT
MAX
t<Subscrip
t>w</Subs Reset pulse duration
cript>
4
4
ns
tREC
Reset recovery time
0
0
ns
tRESET
Time to reset
400
400
ns
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted) (see Figure 11 and Figure 12)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
P port
INT
STANDARD MODE
I2C BUS
MIN
MAX
FAST MODE
I2C BUS
MIN
UNIT
MAX
4
µs
4
4
µs
200
200
ns
tiv
Interrupt valid time
4
tir
Interrupt reset delay time
SCL
INT
tpv
Output data valid
SCL
P7–P0
tps
Input data setup time
P port
SCL
100
100
ns
tph
Input data hold time
P port
SCL
1
1
µs
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PCA9538
SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ................................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
SUPPLY CURRENT
vs
TEMPERATURE
QUIESCENT SUPPLY CURRENT
vs
TEMPERATURE
35
55
50
VCC = 5 V
30
ICC – Supply Current – nA
ICC – Supply Current – µA
45
40
f SCL = 400 kHz
I/Os unloaded
35
30
25
VCC = 3.3 V
20
15
VCC = 2.5 V
10
VCC = 5 V
25
VCC = 3.3 V
20
15
VCC = 2.5 V
10
5
5
SCL = VCC
0
-40
-15
10
35
60
0
-40
85
10
35
60
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
NUMBER OF I/Os HELD LOW
70
85
600
f SCL = 400 kHz
I/Os unloaded
60
VCC = 5 V
550
500
ICC – Supply Current – µA
ICC – Supply Current – µA
-15
50
40
30
20
450
400
TA = –40°C
350
300
TA = 25°C
250
200
TA = 85°C
150
100
10
50
0
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
0
VCC – Supply Voltage – V
14
1
2
3
4
5
6
7
8
Number of I/Os Held Low
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TYPICAL CHARACTERISTICS (continued)
TA = 25°C (unless otherwise noted)
I/O OUTPUT LOW VOLTAGE
vs
TEMPERATURE
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
30
VCC = 2.5 V
250
VCC = 2.5 V, IOL = 10 mA
25
225
ISINK – I/O Sink Current – mA
(V CC – V OH ) – Output High Voltage – mV
275
200
175
150
125
VCC = 5 V, IOL = 10 mA
100
75
VCC = 2.5 V, IOL = 1 mA
50
VCC = 5 V, IOL = 1 mA
25
TA = –40°C
20
TA = 25°C
15
TA = 85°C
10
5
0
0
-40
0.0
-15
10
35
60
0.1
85
0.2
0.3
0.4
0.5
0.6
0.7
VOL – Output Low Voltage – V
TA – Free-Air Temperature – °C
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
60
40
VCC = 3.3 V
50
TA = –40°C
ISINK – I/O Sink Current – mA
ISINK – I/O Sink Current – mA
VCC = 5 V
55
35
30
25
TA = 25°C
20
15
TA = 85°C
10
45
TA = –40°C
40
35
TA = 25°C
30
25
TA = 85°C
20
15
10
5
5
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
VOL – Output Low Voltage – V
VOL – Output Low Voltage – V
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TYPICAL CHARACTERISTICS (continued)
TA = 25°C (unless otherwise noted)
I/O OUTPUT HIGH VOLTAGE
vs
TEMPERATURE
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
35
VCC = 2.5 V
250
VCC = 2.5 V, IOL = 10 mA
ISOURCE – I/O Source Current – mA
(V CC – V OH ) – Output High Voltage – mV
275
225
200
175
150
125
VCC = 5 V, IOL = 10 mA
100
75
VCC = 2.5 V, IOL = 1 mA
50
VCC = 5 V, IOL = 1 mA
25
30
TA = –40°C
25
TA = 25°C
20
15
10
TA = 85°C
5
0
0
-40
0.0
-15
10
35
60
85
0.1
0.2
0.3
0.4
0.5
0.6
0.7
(VCC – VOH) – Output High Voltage – V
TA – Free-Air Temperature – °C
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
75
70
50
VCC = 3.3 V
40
ISOURCE – I/O Source Current – mA
ISOURCE – I/O Source Current – mA
45
TA = –40°C
35
TA = 25°C
30
25
20
TA = 85°C
15
10
5
VCC = 5 V
65
60
55
50
TA = –40°C
45
40
35
30
TA = 25°C
TA = 85°C
25
20
15
10
5
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0
(VCC – VOH) – Output High Voltage – V
16
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0.1
0.2
0.3
0.4
0.5
0.6
0.7
(VCC – VOH) – Output High Voltage – V
Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): PCA9538
PCA9538
www.ti.com ................................................................................................................................................ SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008
TYPICAL CHARACTERISTICS (continued)
TA = 25°C (unless otherwise noted)
OUTPUT HIGH VOLTAGE
vs
SUPPLY VOLTAGE
6
TA = 25°C
VOH – Output High Voltage – V
5
4
IOH = –8 mA
3
IOH = –10 mA
2
1
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VCC – Supply Voltage – V
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PCA9538
SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ................................................................................................................................................ www.ti.com
PARAMETER MEASUREMENT INFORMATION
VCC
RL = 1 kΩ
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition
(P)
Start
Address
Address
Condition
Bit 7
Bit 6
(S)
(MSB)
Address
Bit 1
tscl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
tsch
0.7 × VCC
SCL
0.3 × VCC
ticr
ticf
tbuf
tsts
tPHL
tPLH
tsp
0.7 × VCC
SDA
0.3 × VCC
ticf
ticr
tsth
tsdh
tsds
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I2C address
2, 3
P-port data
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 10. I2C Interface Load Circuit and Voltage Waveforms
18
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
8 Bits
(One Data Byte)
From Port
R/W
Slave Address
S
1
1
1
0
0 A1 A0 1
A
1
2
3
4
5
A
6
7
8
Data 1
ACK
From Slave
Data From Port
A
Data 2
1
P
A
tir
tir
B
B
INT
A
tiv
tsps
A
Data
Into
Port
Address
Data 1
0.7 × VCC
INT
0.3 × VCC
SCL
Data 2
0.7 × VCC
R/W
tiv
A
0.3 × VCC
tir
0.7 × VCC
Pn
0.7 × VCC
INT
0.3 × VCC
0.3 × VCC
View A−A
View B−B
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 11. Interrupt Load Circuit and Voltage Waveforms
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PCA9538
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PARAMETER MEASUREMENT INFORMATION (continued)
Pn
500 W
2 × VCC
DUT
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
0.7 × VCC
SCL
P0
A
P3
0.3 × VCC
Slave
ACK
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
SDA
Pn
tpv
(see Note B)
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
0.7 × VCC
SCL
P0
A
tps
P3
0.3 × VCC
tph
0.7 × VCC
Pn
0.3 × VCC
READ MODE (R/W = 1)
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
The outputs are measured one at a time, with one transition per measurement.
D.
All parameters and waveforms are not applicable to all devices.
Figure 12. P-Port Load Circuit and Voltage Waveforms
20
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC
Pn
RL = 1 kΩ
DUT
500 W
2 × VCC
DUT
SDA
CL = 50 pF
(see Note A)
500 W
CL = 50 pF
(see Note A)
P-PORT LOAD CONFIGURATION
SDA LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 y VCC
tRESET
RESET
VCC/2
tREC
tw
Px
(see Note D)
VCC/2
tRESET
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
The outputs are measured one at a time, with one transition per measurement.
D.
I/Os are configured as inputs.
E.
All parameters and waveforms are not applicable to all devices.
Figure 13. Reset Load Circuits and Voltage Waveforms
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PCA9538
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APPLICATION INFORMATION
Figure 14 shows an application in which the PCA9538 can be used.
VCC
(5 V)
10 kW
VCC
Master
Controller
10 kW
10 kW
2 kW
10 kW
100 kW
(y3)
VCC
SDA
SDA
SCL
SCL
INT
INT
RESET
RESET
P0
Subsystem 1
(e.g., temperature sensor)
P1
INT
P2
RESET
P3
GND
Subsystem 2
(e.g., counter)
PCA9538
P4
A
P5
Controlled Device
(e.g., CBT device)
P6
ENABLE
A1
P7
B
A0
GND
ALARM
Subsystem 3
(e.g., alarm system)
VCC
A.
Device address is configured as 1110000 for this example.
B.
P0, P2, and P3 are configured as outputs.
C.
P1, P4, and P5 are configured as inputs.
D.
P6 and P7 are not used and must be configured as outputs.
Figure 14. Typical Application
22
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Minimizing ICC When I/Os Control LEDs
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in
Figure 14. The LED acts as a diode, so when the LED is off, the I/O VIN is about 1.2 V less than VCC. ICC in
Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC.
For battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC when
the LED is off to minimize current consumption. Figure 15 shows a high-value resistor in parallel with the LED.
Figure 16 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O
VIN at or above VCC and prevents additional supply current consumption when the LED is off.
VCC
LED
100 kW
VCC
LEDx
Figure 15. High-Value Resistor in Parallel With LED
3.3 V
VCC
5V
LED
LEDx
Figure 16. Device Supplied by a Lower Voltage
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PACKAGE OPTION ADDENDUM
www.ti.com
5-May-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
PCA9538DB
ACTIVE
SSOP
DB
16
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9538DBG4
ACTIVE
SSOP
DB
16
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9538DBR
ACTIVE
SSOP
DB
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9538DBRG4
ACTIVE
SSOP
DB
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9538DGVR
ACTIVE
TVSOP
DGV
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9538DGVRG4
ACTIVE
TVSOP
DGV
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9538DW
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9538DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9538DWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9538DWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9538PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9538PWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9538PWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9538PWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-May-2008
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-May-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.2
6.6
2.5
12.0
16.0
Q1
PCA9538DBR
SSOP
DB
16
2000
330.0
16.4
PCA9538DGVR
TVSOP
DGV
16
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
PCA9538DWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
PCA9538PWR
TSSOP
PW
16
2000
330.0
12.4
7.0
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-May-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCA9538DBR
SSOP
DB
16
2000
346.0
346.0
33.0
PCA9538DGVR
TVSOP
DGV
16
2000
346.0
346.0
29.0
PCA9538DWR
SOIC
DW
16
2000
346.0
346.0
33.0
PCA9538PWR
TSSOP
PW
16
2000
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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