SN54LVTH16652, SN74LVTH16652 3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS150K – JULY 1994 – REVISED APRIL 1999 D D D D D D D D D D D D Members of the Texas Instruments Widebus Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings SN54LVTH16652 . . . WD PACKAGE SN74LVTH16652 . . . DGG OR DL PACKAGE (TOP VIEW) 1OEAB 1CLKAB 1SAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2SAB 2CLKAB 2OEAB 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OEBA 1CLKBA 1SBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2SBA 2CLKBA 2OEBA description The ’LVTH16652 devices are 16-bit bus transceivers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’LVTH16652 devices. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LVTH16652, SN74LVTH16652 3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS150K – JULY 1994 – REVISED APRIL 1999 description (continued) Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last level configuration. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH16652 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVTH16652 is characterized for operation from –40°C to 85°C. FUNCTION TABLE DATA I/O† INPUTS OEAB OEBA CLKAB CLKBA SAB SBA L H H or L L H ↑ H or L X ↑ X X H ↑ H or L H H ↑ L X H or L L L L L OPERATION OR FUNCTION A1–A8 B1–B8 X Input Input Isolation X Input Input Store A and B data X Input Unspecified‡ Store A, hold B ↑ X X‡ X Input Output Store A in both registers ↑ X Unspecified‡ Input Hold A, store B ↑ ↑ X X X‡ Output Input Store B in both registers X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus H H X X L X Input Output Real-time A data to B bus H H H or L X H X Input Output Stored A data to B bus H L H or L H or L H H Output Output Stored A data to B bus and stored B data to A bus † The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. ‡ Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered to load both registers. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVTH16652, SN74LVTH16652 3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS OEAB OEBA L L CLKAB CLKBA SAB X X X BUS B BUS A BUS A BUS B SCBS150K – JULY 1994 – REVISED APRIL 1999 SBA L OEAB OEBA H H X L L H X H ↑ X ↑ CLKBA SAB X ↑ ↑ X X X SAB L SBA X BUS B BUS A BUS A OEAB OEBA CLKAB CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A CLKAB X SBA X X X STORAGE FROM A, B, OR A AND B OEAB OEBA H L CLKAB CLKBA SAB SBA H or L H or L H H TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LVTH16652, SN74LVTH16652 3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS150K – JULY 1994 – REVISED APRIL 1999 logic symbol† 56 1OEBA 1OEAB 1CLKBA 1SBA 1CLKAB 1SAB 2OEBA 2OEAB 2CLKBA 2SBA 2CLKAB 2SAB 1A1 1 55 54 2 EN1 [BA] EN2 [AB] C3 G4 C5 3 29 28 30 31 27 26 G6 EN7 [BA] EN8 [AB] C9 G10 C11 G12 ≥1 5 3D 4 1 52 1B1 4 1 5D 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 6 1 6 ≥1 2 6 51 8 49 9 48 10 47 12 45 13 44 14 43 ≥1 15 10 7 9D 42 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 10 1 11D 12 ≥1 8 2A2 2A3 2A4 2A5 2A6 2A7 2A8 16 1 12 40 19 38 20 37 21 36 23 34 24 33 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 4 41 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2B2 2B3 2B4 2B5 2B6 2B7 2B8 SN54LVTH16652, SN74LVTH16652 3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS150K – JULY 1994 – REVISED APRIL 1999 logic diagram (positive logic) 1OEBA 1OEAB 1CLKBA 1SBA 1CLKAB 1SAB 56 1 55 54 2 3 One of Eight Channels 1A1 1D C1 5 52 1B1 1D C1 To Seven Other Channels 2OEBA 2OEAB 2CLKBA 2SBA 2CLKAB 2SAB 29 28 30 31 27 26 One of Eight Channels 2A1 1D C1 15 42 1D 2B1 C1 To Seven Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LVTH16652, SN74LVTH16652 3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS150K – JULY 1994 – REVISED APRIL 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Current into any output in the low state, IO: SN54LVTH16652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVTH16652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVTH16652 . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVTH16652 . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) SN54LVTH16652 SN74LVTH16652 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 V Input voltage 5.5 5.5 V IOH IOL High-level output current –24 –32 mA Low-level output current 48 64 mA ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 High-level input voltage 2 Outputs enabled 2 10 V 10 –40 ns/V µs/V 200 125 V 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVTH16652, SN74LVTH16652 3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS150K – JULY 1994 – REVISED APRIL 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 2.7 V, IOH = –8 mA IOH = –24 mA VCC = 3 V VCC = 2 2.7 7V VOL VCC = 3 V Control inputs VCC = 0 or 3.6 V, VCC = 3.6 V, II A or B ports‡ Ioff II(hold) ( ) VCC = 3.6 V VCC = 0, A or B ports SN54LVTH16652 TYP† MAX TEST CONDITIONS VCC = 3 V MIN –1.2 VCC–0.2 2.4 –1.2 VCC–0.2 2.4 IOH = –32 mA IOL = 100 µA UNIT V V 2 2 0.2 0.2 IOL = 24 mA IOL = 16 mA 0.5 0.5 0.4 0.4 IOL = 32 mA IOL = 48 mA 0.5 0.5 V 0.55 IOL = 64 mA VI = 5.5 V 0.55 10 10 VI = VCC or GND VI = 5.5 V ±1 ±1 20 20 VI = VCC VI = 0 1 1 –5 –5 VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V ±100 75 75 –75 –75 µA µA µA ±500 IOZPU VCC = 3.6 V§, VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE/OE = don’t care IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE/OE = don’t care ICC VCC = 3.6 V, IO = 0, VI = VCC or GND ∆ICC¶ VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 VO = 3 V or 0 Cio SN74LVTH16652 TYP† MAX MIN Outputs high Outputs low Outputs disabled ±100* ± 100 µA ±100* ±100 µA 0.19 0.19 5 5 0.19 0.19 0.2 0.2 mA mA 4 4 pF 10 10 pF * On products compliant to MIL-PRF-38535, this parameter is not production tested. † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ Unused pins at VCC or GND § This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54LVTH16652, SN74LVTH16652 3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS150K – JULY 1994 – REVISED APRIL 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN54LVTH16652 VCC = 3.3 V ± 0.3 V MIN fclock tw Clock frequency MAX VCC = 2.7 V MIN 150 Pulse duration, CLK high or low tsu Setup time,, A or B before CLKAB↑ or CLKBA↑ th Hold time, A or B after CLKAB↑ ↑ or CLKBA↑ ↑ SN74LVTH16652 VCC = 3.3 ± 0.3 V MAX MIN 150 MAX VCC = 2.7 V MIN 150 3.3 3.3 3.3 1.2 1.5 1.2 1.5 2 2.8 2 2.8 Data high 0.5 0 0.5 0 Data low 0.5 0.5 0.5 0.5 Data high Data low MAX 150 3.3 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2) SN54LVTH16652 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ VCC = 2.7 V MAX 150 CLK B or A A or B B or A SAB or SBA B or A OEBA A OEBA A OEAB B OEAB B SN74LVTH16652 MIN MAX 150 MIN VCC = 2.7 V TYP† MAX 150 MIN 150 MHz 4.5 5 1.3 2.7 4.2 4.7 1.3 4.5 5 1.3 2.8 4.2 4.7 1 3.6 4.1 1 2.4 3.4 3.9 1 3.6 4.1 1 2.1 3.4 3.9 1 4.7 5.6 1 2.7 4.5 5.4 1 4.7 5.6 1 3 4.5 5.4 1 4.5 5.4 1 2.4 4.3 5.2 1 4.5 5.4 1 2.3 4.3 5.2 2 5.8 6.3 2 3.9 5.6 6.1 2 5.6 6.3 2 3.4 5.4 6.1 1.3 4.4 5.1 1.3 2.7 4.2 4.9 1.3 4.4 5.1 1.3 2.6 4.2 4.9 1.6 5.8 6.5 1.3 3.5 5.5 6.2 1.6 5.8 6.5 1.3 3.2 5.5 6.2 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MAX 1.3 † All typical values are at VCC = 3.3 V, TA = 25°C. 8 VCC = 3.3 V ± 0.3 V ns ns ns ns ns ns ns SN54LVTH16652, SN74LVTH16652 3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS150K – JULY 1994 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V 1.5 V Timing Input LOAD CIRCUIT 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1.5 V Output 1.5 V VOL tPHL Output Waveform 1 S1 at 6 V (see Note B) 1.5 V 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZL tPLZ 3V 1.5 V tPZH tPLH VOH Output 2.7 V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 8-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74LVTH16652DGGRE4 ACTIVE TSSOP DGG 56 2000 74LVTH16652DLRG4 ACTIVE SSOP DL 56 SN74LVTH16652DGGR ACTIVE TSSOP DGG SN74LVTH16652DL ACTIVE SSOP SN74LVTH16652DLR ACTIVE SSOP Pb-Free (RoHS) Lead/Ball Finish MSL Peak Temp (3) CU NIPDAU Level-1-250C-UNLIM 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 56 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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