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IUHTXHQF\ï $FWLYDWLQJ 7$26 FDXVHV 7326 DQG 71(* LQSXWV WR EH LJQRUHGï 7$26 LV LQKLELWHG GXULQJ 5HPRWH /RRSð EDFNï 6HWWLQJ 7$26ñ //223 DQG 5/223 +LJK VLPXOWDQHRXVO\ HQDEOHV 1HWZRUN /RRSEDFN GHWHFWLRQï ëé ëè ëç ëæ ëå êðé L1 )XQFWLRQDO 'HVFULSWLRQ )81&7,21$/ '(6&5,37,21 7KH /;7êìí LV D IXOO\ LQWHJUDWHG 3&0 WUDQVFHLYHU IRU ìïèéé 0ESV õ7ìô DSSOLFDWLRQVï ,W DOORZV IXOOðGXSOH[ WUDQVð PLVVLRQ RI GLJLWDO GDWD RYHU H[LVWLQJ WZLVWHGðSDLU LQVWDOODð WLRQVï 7KH /;7êìí LQWHUIDFHV ZLWK WZR WZLVWHGðSDLU OLQHV õRQH SDLU IRU WUDQVPLWñ RQH SDLU IRU UHFHLYHô WKURXJK VWDQGDUG SXOVH WUDQVIRUPHUV DQG DSSURSULDWH UHVLVWRUVï The figure on the front page of this section is a block diagram of the LXT310. The transceiver may be controlled by a microprocessor through the serial port (Host Mode), or by individual pin settings (Hardware Mode). The jitter attenuator may be positioned in either the transmit or receive path. 3RZHU 5HTXLUHPHQWV The LXT310 is a low-power CMOS device. It operates from a single +5 V power supply which can be connected externally to both the transmitter and receiver. However, the two inputs must be within ± .3 V of each other, and decoupled to their respective grounds separately. Refer to Application Information for typical decoupling circuitry. Isolation between the transmit and receive circuits is provided internally. ,QLWLDOL]DWLRQ DQG 5HVHW 2SHUDWLRQV 8SRQ SRZHU XSñ WKH WUDQVFHLYHU LV KHOG VWDWLF XQWLO WKH SRZHU VXSSO\ UHDFKHV DSSUR[LPDWHO\ ê 9ï 8SRQ FURVVLQJ WKLV WKUHVKROGñ WKH GHYLFH EHJLQV D êë PV UHVHW F\FOH WR FDOð LEUDWH WKH WUDQVPLW DQG UHFHLYH GHOD\ OLQHV DQG ORFN WKH 3KDVH /RFN /RRS WR WKH UHFHLYH OLQHï $ UHIHUHQFH FORFN LV UHTXLUHG WR FDOLEUDWH WKH GHOD\ OLQHVï 7KH WUDQVPLWWHU UHIHUð HQFH LV SURYLGHG E\ 7&/.ï 7KH FU\VWDO RVFLOODWRU SURYLGHV WKH UHFHLYHU UHIHUHQFHï ,I WKH FU\VWDO RVFLOODWRU LV JURXQGHGñ 0&/. LV XVHG DV WKH UHFHLYHU UHIHUHQFH FORFNï 7KH WUDQVFHLYHU FDQ DOVR EH UHVHW IURP WKH +RVW RU +DUGð ZDUH 0RGHï ,Q +RVW 0RGHñ UHVHW LV FRPPDQGHG E\ VLPXOð WDQHRXVO\ ZULWLQJ RQHV WR 5/223 DQG //223ñ DQG D ]HUR WR 7$26ï ,Q +DUGZDUH 0RGHñ UHVHW LV FRPPDQGHG E\ KROGLQJ 5/223 DQG //223 +LJK VLPXOWDQHRXVO\ IRU ëíí QV ZKLOH KROGLQJ 7$26 /RZï ,Q HLWKHU PRGHñ UHVHW FOHDUV DQG VHWV DOO UHJLVWHUV WR íï 5HFHLYHU The twisted-pair input is received via a 1:1 transformer. Recovered data is output at RPOS/RNEG (RDATA in unipolar mode), and the recovered clock is output at RCLK. Refer to Test Specifications for receiver timing. The signal received at RPOS and RNEG is processed through the receive equalizer. The Equalizer Gain Limit (EGL) input determines the maximum gain that may be applied at the equalizer. When set Low, up to 36 dB of gain may be applied. :KHQ (*/ LV +LJKñ JDLQ LV OLPLWHG WR QR PRUH WKDQ ëç G% SURYLGLQJ IRU LQFUHDVHG QRLVH PDUJLQ LQ VKRUWHU ORRS RSHUð DWLRQï ,QVHUWLRQ ORVV RI WKH OLQH LQ æïè G% VWHSVñ DV LQGLFDWHG E\ WKH UHFHLYH HTXDOL]HU VHWWLQJñ LV HQFRGHG LQ WKH /$71 RXWSXW DV VKRZQ LQ )LJXUH ëï )LJXUH ëã /$71 3XOVH :LGWK (QFRGLQJ 5&/. /$71 ì ë /$71 ê é è /$71 é 5&/.ñ í G% RI $WWHQXDWLRQ /$71 ê 5&/.ñ ëëïè G% RI $WWHQXDWLRQ /$71 ë 5&/.ñ ìè G% RI $WWHQXDWLRQ ì 5&/.ñ æïè G% RI $WWHQXDWLRQ 127(ã /$71 LV VWDEOH DQG YDOLG RQ WKH ULVLQJ HGJH RI 5&/. L1 êðè /;7êìí 7ì &68î,6'1 35, 7UDQVFHLYHU The equalized signal is filtered and applied to the peak detector and data slicers. The peak detector samples the inputs and determines the maximum value of the received signal. A percentage of the peak value is provided to the data slicers as a threshold level to ensure optimum signalto-noise ratio. The threshold is set to 50% of the peak value. The receiver is capable of accurately recovering signals with up to 36 dB of cable attenuation (from 2.4 V) 7KH WUDQVPLWWHG SXOVH VKDSH LV GHWHUPLQHG E\ /LQH %XLOG 2XW õ/%2ô LQSXWV /%2ì DQG /%2ë DV IROORZVã After processing through the data slicers, the received signal is routed to the data and timing recovery section, then to the B8ZS decoder (if selected) and to the LOS processor. The LOS Processor loads a digital counter at the RCLK frequency. The count is incremented each time a zero (space) is received, and reset to zero each time a one (mark) is received. Upon receipt of 175 consecutive zeros the LOS pin goes High, and a smooth transition replaces the RCLK output with the MCLK. (During LOS if MCLK is not supplied and JASEL = 1, the RCLK output is replaced with the centered crystal clock.) LBO settings are input through the serial port in the Host Mode. In the Hardware Mode, LBO inputs are applied through individual pins. Shaped pulses meeting the various T1 CSU and ISDN PRI requirements are applied to the AMI line driver for transmission onto the line at TTIP and TRING. Refer to Test Specifications for T1 pulse mask specifications. Received marks will be output regardless of the LOS status, but the LOS pin will not reset until the ones density reaches 12.5 %. This level is based on receipt of at least 4 ones in any 32-bit period. 7UDQVPLWWHU Input data (bipolar or unipolar) for transmission onto the line is clocked serially into the device. Bipolar data is input at pin 3 (TPOS) and pin 4 (TNEG). Unipolar data is input at pin 3 (TDATA) only. (Unipolar mode is enabled by holding pin 4 high for 16 RCLK cycles). Input data may be passed through the Jitter Attenuator and/or B8ZS encoder, if selected. In Host Mode, B8ZS is selected by setting bit D3 of the input data byte. In Hardware Mode, B8ZS is selected by connecting the MODE pin to RCLK. Input synchronization is supplied by the transmit clock (TCLK). Timing requirements for TCLK and the Master Clock (MCLK) are defined in Test Specifications. ,GOH 0RGH 7KH /;7êìí LQFRUSRUDWHV D WUDQVPLW LGOH PRGHï 7KLV DOORZV PXOWLSOH WUDQVFHLYHUV WR EH FRQQHFWHG WR D VLQJOH OLQH IRU UHGXQGDQW DSSOLFDWLRQVï 77,3 DQG 75,1* UHPDLQ LQ D KLJKð LPSHGDQFH VWDWH ZKHQ 7&/. LV QRW SUHVHQW õ7&/. JURXQGHGôï 7KH KLJKðLPSHGDQFH VWDWH FDQ EH WHPSRUDULO\ GLVDEOHG E\ HQDEOLQJ HLWKHU 7$26ñ 5HPRWH /RRSEDFN RU 1HWZRUN /RRSEDFNï êðç /LQH %XLOGð2XW õG%ô í æïè ìè ëëïè /%2ì í ì í ì /%2ë í í ì ì 6KRUW &LUFXLW /LPLW 7KH /;7êìí WUDQVPLWWHU LV HTXLSSHG ZLWK D VKRUWðFLUFXLW OLPLWHUï 7KLV IHDWXUH OLPLWV WR DSSUR[LPDWHO\ ìëí P$ 506 WKH FXUUHQW WKH WUDQVPLWWHU ZLOO VRXUFH LQWR D ORZðLPSHGð DQFH ORDGï 7KH OLPLWHU WULSV ZKHQ WKH 506 FXUUHQW H[FHHGV WKH OLPLW IRU ìíí “V õa ìèí PDUNVôï ,W DXWRPDWLFDOO\ UHVHWV ZKHQ WKH ORDG FXUUHQW GURSV EHORZ WKH OLPLWï 7KH /;7êìí PHHWV RU H[FHHGV )&& DQG $7÷7 VSHFLILFDð WLRQV IRU &68 DQG 1, DSSOLFDWLRQVñ DV ZHOO DV $16, 7ì(ìñ DQG &&,77 UHTXLUHPHQWV IRU ,6'1 35,ï /LQH &RGH The LXT310 transmits data as a 50% AMI line code as shown in Figure 3. Power consumption is reduced by activating the AMI line driver only to transmit a mark. The output driver is disabled during transmission of a space. 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VKRZQ LQ 7DEOH êï SET DIAGNOSTICS OR RESET RLOOP LLOOP D0 (LSB) 1=ENABLE D5 1=ENABLE 1=ENABLE TAOS D7(MSB) 1=ENABLE êðæ /;7êìí 7ì &68î,6'1 35, 7UDQVFHLYHU ï 7DEOH êã /;7êìí 6HULDO 'DWD 2XWSXW %LWV õ6HH )LJXUH éô %LW 'è %LW 'ç %LW 'æ í í í 5HVHW KDV RFFXUUHGñ RU QR SURJUDP LQSXWï í í ì 7$26 LV DFWLYHï í ì í /RFDO /RRSEDFN LV DFWLYHï í ì ì 7$26 DQG /RFDO /RRSEDFN DUH DFWLYHï ì í í 5HPRWH /RRSEDFN LV DFWLYHï ì í ì '30 KDV FKDQJHG VWDWH VLQFH ODVW &OHDU '30 RFFXUUHGï ì ì í /26 KDV FKDQJHG VWDWH VLQFH ODVW &OHDU /26 RFFXUUHGï ì ì ì /26 DQG '30 KDYH ERWK FKDQJHG VWDWH VLQFH ODVW &OHDU '30 DQG &OHDU /26 RFFXUUHGï 6WDWXV +DUGZDUH 0RGH 2SHUDWLRQ In Hardware Mode the transceiver is accessed and controlled through individual pins. With the exception of the INT and CLKE functions, Hardware Mode provides all the functions provided in the Host Mode. In the Hardware Mode RPOS/RNEG or RDATA outputs are valid on the rising edge of RCLK. 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Table 4 provides the decoded output for each equalizer setting. Figure 5 is a typical decoding circuit for the LATN output. It uses a 2-bit synchronous counter (half of a 4-bit counter) with synchronous reset, and a pair of flip-flops. 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The LXT310 is operating in the Hardware Mode with B8ZS encoding enabled (MODE pin 5 tied to RCLK). As in the T1/CSU application, Figure 6, this configuration is illustrated with a single power supply bus. CMOS control logic is used to set both LBO pins high, selecting the 22.5 dB LBO, and the EGL pin is tied low, allowing for full receiver gain. The TAOS, LLOOP and RLOOP diagnostic modes are individually controllable. The RCLK input to the OR gate at RLOOP allows for clocking of the RLOOP pin, which enables network loopback detection. The receive and transmit line interfaces are identical to the Host Mode application shown in Figure 6. )LJXUH æã 7\SLFDO /;7êìí +DUGZDUH 0RGH $SSOLFDWLRQ /;3çíí$ &/$' &/., FSI &/.2 ëïíéå 0+] ìïèéé 0+] /;7êìí 75$16&(,9(5 7ìî(6) )5$0(5 1RWH ì 0&/. 7$26 7&/. 7&/. //223 7326 7326 RLOOP 71(* 71(* /%2ì 02'( /%2ë 51(* 51(* NLOOP 5326 5326 5*1' 5&/. 5&/. 59ò çïìæç 0+] 127( ì 7KH /;7êìí LV FRPSDWLEOH ZLWK D ZLGH YDULHW\ RI IUDPLQJîVLJQDOLQJ GHYLFHVï êðìë ;7$/,1 55,1* ;7$/287 57,3 -$6(/ /$71 /26 (*/ 77,3 75,1* 7*1' )URP &026 &RQWURO /RJLF í9 íïì µ) ìãì 7ì /LQH 5HFHLYH ìíí Ω ìëïè Ω 79ò ìïí µ) çå µ) ìïèéé 0+] 7ì /LQH 7UDQVPLW ìëïè Ω ìãë 9ò L1 7HVW 6SHFLILFDWLRQV 7(67 63(&,),&$7,216 127( 7KH PLQLPXP DQG PD[LPXP YDOXHV LQ 7DEOHV æ WKURXJK ìé DQG )LJXUHV å WKURXJK ìë UHSUHVHQW WKH SHUIRUPDQFH VSHFLILFDð WLRQV RI WKH /;7êìí DQG DUH JXDUDQWHHG E\ WHVWñ H[FHSW ZKHUH QRWHG E\ GHVLJQï 7DEOH æã $EVROXWH 0D[LPXP 5DWLQJV 3DUDPHWHU 6\P 0LQ 0D[ 8QLWV 59òñ 79ò ðíïê çïí 9 ,QSXW YROWDJHñ DQ\ SLQ 9,1 5*1' ð íïê 59ò ò íïê 9 ,QSXW FXUUHQWñ DQ\ SLQì ,,1 ðìí ìí P$ $PELHQW RSHUDWLQJ WHPSHUDWXUH 7$ ðéí åè ƒ& 767* ðçè ìèí ƒ& '& VXSSO\ õUHIHUHQFHG WR *1'ô 6WRUDJH WHPSHUDWXUH &$87,21 2SHUDWLRQV DW RU EH\RQG WKHVH OLPLWV PD\ UHVXOW LQ SHUPDQHQW GDPDJH WR WKH GHYLFHï 1RUPDO RSHUDWLRQ LV QRW JXDUDQWHHG DW WKHVH H[WUHPHVï ìï 7UDQVLHQW FXUUHQWV RI XS WR ìíí P$ ZLOO QRW FDXVH 6&5 ODWFK XSï 77,3ñ 75,1*ñ 79ò DQG 7*1' FDQ ZLWKVWDQG D FRQWLQXRXV FXUUHQW RI ìíí P$ï 7DEOH åã 5HFRPPHQGHG 2SHUDWLQJ &RQGLWLRQV DQG &KDUDFWHULVWLFV 3DUDPHWHU '& VXSSO\ì $PELHQW RSHUDWLQJ WHPSHUDWXUH 6\P 0LQ 7\S 0D[ 8QLWV 59òñ 79ò 7$ éïæè ¤ èïí ëè èïëè ¤ 9 ƒ& ìï 79ò PXVW QRW H[FHHG 59ò E\ PRUH WKDQ íïê 9ï 7DEOH äã (OHFWULFDO &KDUDFWHULVWLFV õ8QGHU 5HFRPPHQGHG 2SHUDWLQJ &RQGLWLRQVô 3DUDPHWHU +LJK OHYHO LQSXW YROWDJHëñê õSLQV ìðèñ ìíñ ëêðëåô /RZ OHYHO LQSXW YROWDJH ëñê +LJK OHYHO RXWSXW YROWDJH /RZ OHYHO RXWSXW YROWDJH ,QSXW OHDNDJH FXUUHQW õSLQV ìðèñ ìíñ ëêðëåô ëñê ëñê õSLQV çðåñ ììñ ìëñ ëêñ ëèô õSLQV çðåñ ììñ ìëñ ëêñ ëèô 6\P 0LQ 7\Sì 0D[ 8QLWV 9,+ ëïí ¤ ¤ 9 9,/ ¤ ¤ íïå 9 92+ ëïé ¤ ¤ 9 ,287 ðéíí µ$ 92/ ¤ ¤ íïé 9 ,287 ìïç P$ ,// í ¤ ‘ìí µ$ 7HVW &RQGLWLRQV ìï 7\SLFDO YDOXHV DUH PHDVXUHG DW ëè °& DQG DUH IRU GHVLJQ DLG RQO\â QRW JXDUDQWHHG DQG QRW VXEMHFW WR SURGXFWLRQ WHVWLQJï ëï )XQFWLRQDOLW\ RI SLQV ëê DQG ëè GHSHQGV RQ PRGHï 6HH +RVWî+DUGZDUH 0RGH GHVFULSWLRQVï êï 2XWSXW GULYHUV ZLOO RXWSXW &026 ORJLF OHYHOV LQWR &026 ORDGVï 4. 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