ETC XE1201A

XE1201A
Data Sheet
TLA
TLB
FILTERING + IO
OFFSET
REDUCTION
RFA
QO
AVDD
AGND
DVDD
DGND
RFB
RXD
DEMODULATOR
SYMBOL SYNCHRO
CLKD
SD
SC
BUS CONTROL
POWER MANAGEMENT
DE
90 DEG
EN
RXTX
RF POWER AMP
RFOUT
TXD
DDS
VREF
90 DEG
LO
CLOCK
TPA
TPB
RFGND
RFVDD
TKA
TKB
TKC
SWA
SWB
LOGND
XTAL
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Cool Solutions
XEMICS SA, Switzerland Tel: +41 32 720 51 70 Fax: +41 32 720 57 70 e-mail: [email protected] Web:www.xemics.com
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IO
RFA
RFB
RFOUT
RFGND
TLA
TLB
RFVDD
'HWDLOHG3LQ'HVFULSWLRQ
PIN
NAME
DESCRIPTION
1
EN
Chip enable
DE
DVDD
2
DE
Bus data enable
AVDD
XTAL
TPA
EN
QO
XTAL
3
AVDD
Supply voltage for analog
4
TPA
Power amplifier tank circuit
AGND
5
TPB
Power amplifier tank circuit
SC
CLKD
6
AGND
Ground for analog
SD
TXD
7
SC
Bus clock
8
SD
Bus data input
9
LOGND
Ground for local oscillator
10
TKA
Oscillator tank circuit
11
TKB
Oscillator tank circuit
12
TKC
Oscillator tank circuit
13
SWA
SAW resonator
14
SWB
SAW resonator
15
RXTX
Receiver / transmitter enable
16
VREF
Voltage stabilizer decoupling
17
TXD
Data input stream
18
CLKD
Received data clock
19
RXD
Received data output
20
DGND
Ground for digital
21
XTAL
Reference oscillator
22
XTAL
Reference oscillator
23
DVDD
Supply voltage for digital
24
QO
Test pin
25
IO
Test pin
26
RFA
RF input
27
RFB
RF input
28
RFGND
Ground for RF
29
RFOUT
Transmitter output
30
TLA
Low noise amplifier tank circuit
31
TLB
Low noise amplifier tank circuit
32
RFVDD
Supply voltage for RF
DGND
TPB
VREF
RXTX
SWB
TKC
SWA
TKB
TKA
LOGND
RXD
fig. 2: TQFP 32L package
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Tamb = 25° C; VDD = 3.0 V; FLO = 433.92 MHz; +/- 125 kHz frequency deviation; 16 kbit/s pseudo random bit sequence
unless otherwise specified
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SYMBOL PARAMETER
CONDITIONS
Min
Typ
Max Units
VDD
Operating supply voltage
2.4
3.0
5.5
V
IDDR
Reception supply current
4.5
6
7.5
mA
IDDT
Transmission supply current
- 15 dBm output power
- 5 dBm output power
+ 2.5 dBm output power
+ 5 dBm output power
IDDS
Standby current
Clock running
Clock stopped
FR
Frequency range
TP
Transmitter output power
RFS
RF sensitivity
-
55
0.2
65
1
µA
300
-
500
MHz
µA
dBm
dBm
dBm
dBm
-15
-5
+2
+5
C13 = 0 ; C12 = 0
C13 = 0 ; C12 = 1
C13 = 1 ; C12 = 0
C13 = 1 ; C12 = 1
BER=1%, Rsource = 50Ω
8 kbit/s
16 kbit/s
64 kbit/s
mA
mA
mA
mA
5.5
8
11
13.5
-106
-104
-99
-109
-107
-102
-
dBm
dBm
dBm
RF input impedance
Parallel real part
Parallel capacitive part
-
1
4
-
kΩ
pF
ZOUT
RF output impedance
Parallel capacitive part
-
2.4
-
pF
CCR
Co-channel rejection
Funw =FLO ±125 kHz
RFlevel = RFS+3dB
-12
-7
-
dB
BI
Blocking immunity
Funw =FRF ±1MHz
RFlevel = RFS+3dB
39
43
-
dB
ML
Maximum receiver input level
1 channel, BER=1%
0
-
-
dBm
BW
Baseband filter bandwidth
3 dB cutoff frequency
250
330
410
kHz
LOD
Local oscillator drift
-40 < Tamb < +85° C
-
-4
-
ppm/°
ZIN
C
LOS
Local oscillator shift
TBW
DDS anti-alias filter bandwidth
FDEV
Frequency deviation
DR
Data rate
LOL
Digital input/output low level
2.4 V < Vdd < 3.6 V
-
+/-8
+/-15
KHz
-
160
-
kHz
programmable by 3-wire bus
+/-4
-
programmable by 3-wire bus
4
-
64
kbit/s
0
-
0.4
V
+/-200 kHz
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SYMBOL PARAMETER
CONDITIONS
Min
Typ
Max Units
2.6
-
3
V
HIL
Digital input/output high level
Tclk
Clock wake-up time
from cold start (see fig. 5)
-
2
3.5
ms
Rwu
Receiver wake-up time
from oscillator running (see fig. 4)
bit synchronizer bypassed
-
60
75
µs
Twu
Transmitter wake-up time
from oscillator running (see fig. 4)
-
60
75
µs
Tsu
Data set-up time
(see fig. 3)
125
-
-
ns
Trt
Receive to transmit switching
time
(see fig. 4)
-
15
25
µs
Ttr
Transmit to receive switching
time
(see fig. 4)
bit synchronizer bypassed
-
60
75
µs
Tr
SC bus clock rise time
-
-
50
ns
Tf
SC bus clock fall time
-
-
50
ns
SC bus clock frequency
-
-
4
MHz
FSC
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Figure 3: timing diagram for 3-wire bus
Rwu
ready to receive
Ttr
ready to transmit
EN
RXTX
A,B,C0
RECEIVE MODE
TRANSMIT MODE
Figure 4: timing diagram for RXTX and EN control pins
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ready to transmit or receive
EN
Tclk
Twu
Figure 5: timing diagram for chip wake-up (from cold start)
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5;'SLQ
measurement conditions: 16 kbit/s - RFlevel = -102 dBm
Figure 6: Received data stream with internal bit synchronizer bypassed
5;'SLQ
&/.'SLQ
measurement conditions: 16 kbit/s - RFlevel = -102 dBm
Figure 7: Received data stream with internal bit synchronizer and synchronised data clock output
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components side (front)
copper side (back)
Figure 8: reference board layout (not actual scale)
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1k3
p i n1 1
p in 4 a n d 5 : p o w e r a m p lif ie r
p in 1 0 , 1 1 , 1 2 , 1 3 a n d 1 4 : o s c illa t o r
pin21
2p2
pin22
5p
3p
p i n1 6
p in 1 6 : vo lt a g e s t a b il iz e r
p in 2 1 a n d 2 2 : c lo c k o s c illa t o r
p i n2 6
p i n2 7
p i n24, 25
p in 2 4 a n d 2 5 : I an d Q o u t p u t s
p in 2 6 a n d 2 7 : R F a m p lif ie r in p u t s
pi n3 0
pi n3 1
pin2 9
p in 2 9 : t r a n s m it t e r o u tp u t
p in 3 0 an d 3 1 : L N A t an k
Figure 9: analog pins description
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VDD
12nH
ustrip
12nH
ustrip
2.7 pF
VDD
10nF
50 OHM
2.2pF
TLA
FILTERING+
OFFSET
REDUCTION
TLB
RFA
FROM ANTENNA
18nH
ustrip
IO
QO
AVDD
AGND
DVDD
DGND
RXD
RFB
2.2pF
DEMODULATOR
SYMBOL SYNCHRO
DATA
OU TPUT
CLKD
2.2pF
SD
SC
BUS CONTROL
POWER MANAGEMENT
90 DEG
CHIP
CONTROL
DE
VDD
EN
3.3pF
18nH
ustrip
50 OHM
RF POWER AMP
RXTX
RFOUT
TXD
DDS
2.2pF
DATA
INPUT
TO ANTENNA
VREF
10nF
90 DEG
LO
CLOCK
TPB
2.2pF
RFGND
RFVDD
TKA
TKC
SWA
SWB
LOGND
XTAL
27nH
2 - 6pF
10nF
12nH
TKB
VDD
TPA
12nH 12nH
12nH
SAW
RESON ATOR
RFM R02101A
10nF
VDD
Figure 10: application information
4 MHz
IQD HC43
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DIMENSIONS
Body Thickness
Footpint (Body+)
A
A1
A2
D
D1
E
E1
L
e
b
ccc
ddd
0
VALUE
1.00
2.00
1.20
0.05 min/0.15 max
1.00
9.00
7.00
9.00
7.00
0.60
0.80
0.35
0.10
0.20
0°-7°
TOLERANCE
MAX
±0.05
±0.25
±0.10
±0.25
±0.10
+0.15/-0.10
BASIC
±0.05
MAX
MAX
Package Information for TQFP 32L
XEMICS, 2001
All rights reserved. Reproduction of whole or part of this document is prohibited without the prior written consent of the copyright
owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and
reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in Switzerland Date of release 02-01
D0101-118