November 1998
PRELIMINARY
ML4801
Variable Feedforward PFC/PWM Controller Combo
GENERAL DESCRIPTION
FEATURES
The ML4801 is a controller for power factor corrected,
switched mode power supplies. Key features of this
combined PFC and PWM controller are low start-up and
operating currents. Power Factor Correction (PFC) allows
the use of smaller, lower cost bulk capacitors, reduces
power line loading and stress on the switching FETs, and
results in a power supply that fully complies with
IEC1000-2-3 specifications. The ML4801 includes circuits
for the implementation of a leading edge, average current
“boost” type power factor correction and a trailing edge
pulse width modulator (PWM).
■
Internally synchronized PFC and PWM in one IC
■
Low start-up current (200µA typ.)
■
Low operating current (5.5mA typ.)
■
Low total harmonic distortion
■
Reduces ripple current in the storage capacitor
between the PFC and PWM sections
■
Average current continuous boost leading edge PFC
■
High efficiency trailing edge PWM optimized for
current mode operation
■
Current fed gain modulator for improved noise
immunity
■
Brown-out control, overvoltage protection, UVLO, and
soft start
The PFC frequency of the ML4801 is automatically set at
half that of the PWM frequency generated by the internal
oscillator. This technique allows the user to design with
smaller output components while maintaining the
optimum operating frequency for the PFC. An overvoltage comparator shuts down the PFC section in the
event of a sudden decrease in load. The PFC section also
includes peak current limiting and input voltage brownout protection.
BLOCK DIAGRAM
16
VFB
15
13
1
POWER FACTOR CORRECTOR
IEAO
VEAO
OVP
VEA
+
2.5V
7.5V
REFERENCE
+
IEA
1.6kΩ
-
+
+
2.75V
-
-1V
+
–
IAC
-
2
GAIN
MODULATOR
VRMS
4
-
S
Q
R
Q
S
Q
R
Q
S
Q
R
Q
VREF
14
PFC OUT
1.6kΩ
ISENSE
VCC
VCC
PFC ILIMIT
12
3
RAMP 1
8
RTCT
OSCILLATOR
7
÷2
RAMP 2
DUTY CYCLE
LIMIT
9
8V
VDC
6
1.25V
VCC
SS
+
-
25µA
5
+
VFB
-
2.5V
+
PWM OUT
11
VIN OK
+
1.5V
8V
-
GND
DC ILIMIT
10
PULSE WIDTH MODULATOR
VCC
UVLO
1
ML4801
PIN CONFIGURATION
ML4801
16-Pin PDIP (P16)
16-Pin Narrow SOIC (S16N)
IEAO 1
IAC 2
16 VEAO
15 VFB
ISENSE 3
14 VREF
VRMS 4
13 VCC
SS 5
12 PFC OUT
VDC 6
11 PWM OUT
RTCT 7
10 GND
RAMP 1 8
9
RAMP 2
TOP VIEW
PIN DESCRIPTION
PIN
NAME
FUNCTION
1
IEAO
PFC transconductance current error
amplifier output
2
IAC
PFC gain control reference input
3
I SENSE
Current sense input to the PFC current
limit comparator
4
V RMS
5
NAME
FUNCTION
9
RAMP 2
PWM ramp current sense input
10
GND
Ground
11
PWM OUT PWM driver output
12
PFC OUT
PFC driver output
Input for PFC RMS line voltage
compensation
13
VCC
Positive supply (connected to an
internal shunt regulator).
SS
Connection point for the PWM soft start
capacitor
14
V REF
Buffered output for the internal 7.5V
reference
6
VDC
PWM voltage feedback input
15
V FB
PFC transconductance voltage error
amplifier input
7
RTCT
Connection for oscillator frequency
setting components
16
VEAO
PFC transconductance voltage error
amplifier output
RAMP 1
PFC ramp input
8
2
PIN
ML4801
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
VCC ............................................................................................... 18V
ISENSE Voltage .................................................. -3V to 5V
Voltage on Any Other Pin ...... GND - 0.3V to VCC + 0.3V
I REF ............................................................................................ 20mA
IAC Input Current .................................................... 10mA
Peak PFC OUT Current, Source or Sink ................ 500mA
Peak PWM OUT Current, Source or Sink .............. 500mA
PFC OUT, PWM OUT Energy Per Cycle .................. 1.5µJ
Junction Temperature .............................................. 150°C
Storage Temperature Range ..................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ..................... 260°C
Thermal Resistance (θJA)
Plastic DIP ....................................................... 80°C/W
Plastic SOIC .................................................. 105°C/W
OPERATING CONDITIONS
Temperature Range
ML4801CX ................................................. 0°C to 70°C
ML4801IX ............................................... -40°C to 85°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 15V, RT = 29.4kΩ, RRAMP1 = 15.4kΩ, CT = 270pF, CRAMP1 = 620pF,
TA = Operating Temperature Range (Note 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5
V
VOLTAGE ERROR AMPLIFIER
Transconductance
0
VNON INV = VINV, VEAO = 3.75V
Feedback Reference Voltage
Input Bias Current
40
65
80
2.43
2.50
2.57
V
-0.5
-1.0
µA
Note 2
Output High Voltage
6.0
Output Low Voltage
6.7
µ
Ω
Input Voltage Range
V
0.1
0.4
V
Source Current
∆VIN = ±0.5V, VOUT = 6V
-40
-70
-150
µA
Sink Current
∆VIN = ±0.5V, VOUT = 1.5V
40
70
150
µA
60
70
dB
60
70
dB
Open Loop Gain
PSRR
11V < VCC < 16.5V
CURRENT ERROR AMPLIFIER
Transconductance
-1.5
VNON INV = VINV, VEAO = 3.75V
Input Offset Voltage
V
60
100
120
µ
0
8
15
mV
-0.5
-1.0
µA
Input Bias Current
Output High Voltage
2
Ω
Input Voltage Range
6.0
Output Low Voltage
6.7
V
0.65
1.0
V
Source Current
∆VIN = ±0.5V, VOUT = 6V
-40
-70
-150
µA
Sink Current
∆VIN = ±0.5V, VOUT = 1.5V
40
70
150
µA
55
65
dB
60
75
dB
Open Loop Gain
PSRR
11V < VCC < 16.5V
3
ML4801
ELECTRICAL CHARACTERISTICS
SYMBOL
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Threshold Voltage
2.65
2.75
2.85
V
Hysteresis
175
250
325
mV
Threshold Voltage
-0.9
-1.0
-1.1
V
∆PFC ILIMIT Threshold - Gain Modulator Output
120
220
OVP COMPARATOR
PFC ILIMIT COMPARATOR
Delay to Output
mV
150
300
ns
1.5
1.6
V
Input Bias Current
±0.3
±1
µA
Delay to Output
150
300
ns
DC ILIMIT COMPARATOR
Threshold Voltage
1.4
VIN OK COMPARATOR
Threshold Voltage
2.4
2.5
2.6
V
Hysteresis
0.8
1.0
1.2
V
IAC = 100µA, VRMS = VFB = 0V
0.65
0.85
1.05
IAC = 50µA, VRMS = 1V, VFB = 0V
1.90
2.20
2.40
IAC = 50µA, VRMS = 1.8V, VFB = 0V
0.90
1.05
1.25
IAC = 100µA, VRMS = 3.3V, VFB = 0V
0.20
0.30
0.40
GAIN MODULATOR
Gain (Note 3)
Bandwidth
IAC = 100µA
10
MHz
Output Voltage
IAC = 350µA, VRMS = 1V,
VFB = 0V
0.65
0.75
0.85
V
Initial Accuracy
TA = 25ºC
188
200
212
kHz
Voltage Stability
11V < VCC < 16.5V
OSCILLATOR
Temperature Stability
Total Variation
Over Line and Temp
2
%
218
2.5
PFC Dead Time
4
%
182
Ramp Valley to Peak Voltage
CT Discharge Current
1
VRAMP 2 = 0V, VRAMP 1 = 2.5V
kHz
V
350
470
600
ns
3.5
5.5
7.5
mA
ML4801
ELECTRICAL CHARACTERISTICS
SYMBOL
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage
TA = 25ºC, I(VREF) = 1mA
7.4
7.5
7.6
V
Line Regulation
11V < VCC < 16.5V
10
25
mV
Load Regulation
1mA < I(VREF) < 10mA
10
20
mV
REFERENCE
Temperature Stability
0.4
7.35
%
Total Variation
Line, Load, Temp
Long Term Stability
TJ = 125ºC, 1000 Hours
Minimum Duty Cycle
VIEAO > 6.7V
Maximum Duty Cycle
VIEAO < 1.2V
Output Low Voltage
IOUT = -20mA
0.4
0.8
V
IOUT = -100mA
0.7
2.0
V
IOUT = -10mA, VCC = 9V
0.4
0.8
V
5
7.65
V
25
mV
0
%
PFC
Output High Voltage
Rise/Fall Time
90
95
%
IOUT = 20mA
VCC - 0.8
V
IOUT = 100mA
VCC - 2.0
V
CL = 1000pF
50
ns
PWM
DC
Duty Cycle Range
VOL
Output Low Voltage
VOH
Output High Voltage
0-44
0-47
0-50
%
IOUT = -20mA
0.4
0.8
V
IOUT = -100mA
0.7
2.0
V
IOUT = -10mA, VCC = 9V
0.4
0.8
V
IOUT = 20mA
VCC - 0. 8
V
IOUT = 100mA
VCC - 2.0
V
Rise/Fall Time
CL = 1000pF
50
ns
Start-up Current
VCC = 12V, CL = 0
200
350
µA
Operating Current
VCC = 14V, CL = 0
5.5
7.0
mA
SUPPLY
Undervoltage Lockout Threshold
12.4
13.0
13.6
V
Undervoltage Lockout Hysteresis
2.7
3.0
3.3
V
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Includes all bias currents to other circuits connected to the VFB pin.
Note 3: Gain = K x 5.3V; K = (IMULO - IOFFSET) x IAC x (VEAO - 0.625V)-1.
5
ML4801
FUNCTIONAL DESCRIPTION
The ML4801 consists of a combined average-currentcontrolled, continuous boost Power Factor Corrector (PFC)
front end and a synchronized Pulse Width Modulator
(PWM) back end. It is distinguished from earlier combo
controllers by its dramatically reduced start-up and
operating currents. The PWM section is intended to be
used in current mode. The PWM stage uses conventional
trailing-edge duty cycle modulation, while the PFC uses
leading-edge modulation. This patented leading/trailing
edge modulation technique results in a higher useable
PFC error amplifier bandwidth, and can significantly
reduce the size of the PFC DC buss capacitor.
The synchronization of the PWM with the PFC simplifies
the PWM compensation due to the reduced ripple on the
PFC output capacitor (the PWM input capacitor). The
PWM section of the ML4801 runs at twice the frequency
of the PFC, which allows the use of smaller PWM output
magnetics and filter capacitors while holding down the
losses in the PFC stage power components.
In addition to power factor correction, a number of
protection features have been built into the ML4801.
These include soft-start, PFC over-voltage protection, peak
current limiting, brown-out protection, duty cycle limit,
and under-voltage lockout.
POWER FACTOR CORRECTION
Power factor correction makes a non-linear load look like
a resistive load to the AC line. For a resistor, the current
drawn from the line is in phase with, and proportional to,
the line voltage, so the power factor is unity (one). A
common class of non-linear load is the input of most
power supplies, which use a bridge rectifier and
capacitive input filter fed from the line. The peakcharging effect which occurs on the input filter capacitor
in such a supply causes brief high-amplitude pulses of
current to flow from the power line, rather than a
sinusoidal current in phase with the line voltage. Such a
supply presents a power factor to the line of less than one
(another way to state this is that it causes significant
current harmonics to appear at its input). If the input
current drawn by such a supply (or any other non-linear
load) can be made to follow the input voltage in
instantaneous amplitude, it will appear resistive to the AC
line and a unity power factor will be achieved.
To maintain the input current of a device drawing power
from the AC line in phase with, and proportional to, the
input voltage, a way must be found to cause that device
to load the line in proportion to the instantaneous line
voltage. The PFC section of the ML4801 uses a boostmode DC-DC converter to accomplish this. The input to
the converter is the full wave rectified AC line voltage.
No filtering is applied following the bridge rectifier, so the
input voltage to the boost converter ranges, at twice line
6
frequency, from zero volts to the peak value of the AC
input and back to zero. By forcing the boost converter to
meet two simultaneous conditions, it is possible to ensure
that the current which the converter draws from the power
line matches the instantaneous line voltage. One of these
conditions is that the output voltage of the boost converter
must be set higher than the peak value of the line
voltage. A commonly used value is 385VDC, to allow for
a high line of 270VACrms. The other condition is that the
current which the converter is allowed to draw from the
line at any given instant must be proportional to the line
voltage. The first of these requirements is satisfied by
establishing a suitable voltage control loop for the
converter, which sets an average operating level for a
current error amplifier and switching output driver. The
second requirement is met by using the rectified AC line
voltage to modulate the instantaneous input of the current
control loop. Such modulation causes the current error
amplifier to command a power stage current which varies
directly with the input voltage. In order to prevent ripple
which will necessarily appear at the output of the boost
circuit (typically about 10VAC on a 385V DC level), from
introducing distortion back through the voltage error
amplifier, the bandwidth of the voltage loop is
deliberately kept low. A final refinement is to adjust the
overall gain of the PFC such to be proportional to 1/VIN2,
which linearizes the transfer function of the system as the
AC input voltage varies.
Since the boost converter topology in the ML4801 PFC is
of the current-averaging type, no slope compensation is
required.
PFC SECTION
Gain Modulator
Figure 1 shows a block diagram of the PFC section of the
ML4801. The gain modulator is the heart of the PFC, as it
is this circuit block which controls the response of the
current loop to line voltage waveform and frequency, rms
line voltage, and PFC output voltage. There are three
inputs to the gain modulator. These are:
1) A current representing the instantaneous input voltage
(amplitude and waveshape) to the PFC. The rectified
AC input sine wave is converted to a proportional
current via an (external) resistor and is then fed into the
gain modulator at IAC. Sampling current in this way
minimizes ground noise, as is required in high power
switching power conversion environments. The gain
modulator responds linearly to this current.
2) A voltage proportional to the long-term rms AC line
voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the
gain modulator at VRMS. The gain modulator’s output is
ML4801
FUNCTIONAL DESCRIPTION
16
VFB
VEA
POWER FACTOR CORRECTOR
2.75V
IEA
1.6kΩ
-
13
1
IEAO
VEAO
15
(Continued)
-
+
2.5V
VCC
OVP
+
7.5V
REFERENCE
VREF
14
+
–
IAC
2
VRMS
4
PFC
CONTROLLER
8V
GAIN
MODULATOR
PFC ILIMIT
-1V
+
-
PFC
OUTPUT
DRIVER
1.6kΩ
ISENSE
3
PFC OUT
12
RAMP 1
OSCILLATOR
8
RTCT
÷2
7
DUTY CYCLE
LIMIT
Figure 1. PFC Section Block Diagram
inversely proportional to VRMS2 (except at unusually
low values of VRMS where special gain contouring
takes over to limit power dissipation of the circuit
components under heavy brownout conditions). The
relationship between VRMS and gain is designated as K.
3) The output of the voltage error amplifier, VEAO. The
gain modulator responds linearly to variations in this
voltage.
The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way
the gain modulator forms the reference for the current
error loop, and ultimately controls the instantaneous
current draw of the PFC from the power line. The general
form for the output of the gain modulator is:
IGAINMOD =
IAC ´ VEAO
VRMS 2
´ 1V
More exactly, the output current of the gain modulator is
given by:
IGAINMOD = K × (VEAO − 0.625V) × IAC
where K is in units of V-1.
Note that the output current of the gain modulator is
limited to ≅ 500µA.
(1)
Current Error Amplifier
The current error amplifier’s output controls the PFC duty
cycle to keep the current through the boost inductor a
linear function of the line voltage. At the inverting input
to the current error amplifier, the output current of the
gain modulator is summed with a current which results
from a negative voltage being impressed upon the ISENSE
pin (current into ISENSE ≅ VSENSE/1.6kΩ). The negative
voltage on ISENSE represents the sum of all currents
flowing in the PFC circuit, and is typically derived from a
current sense resistor in series with the negative terminal
of the input bridge rectifier. In higher power applications,
two current transformers are sometimes used, one to
monitor the ID of the boost MOSFET(s) and one to monitor
the IF of the boost diode. As stated above, the inverting
input of the current error amplifier is a virtual ground.
Given this fact, and the arrangement of the duty cycle
modulator polarities internal to the PFC, an increase in
positive current from the gain modulator will cause the
output stage to increase its duty cycle until the voltage on
ISENSE is adequately negative to cancel this increased
current. Similarly, if the gain modulator’s output
decreases, the output duty cycle will decrease to achieve
a less negative voltage on the ISENSE pin.
Cycle-By-Cycle Current Limiter
The ISENSE pin, as well as being a part of the current
feedback loop, is a direct input to the cycle-by-cycle
current limiter for the PFC section. Should the input
voltage at this pin ever be more negative than -1V, the
output of the PFC will be disabled until the protection
flip-flop is reset by the clock pulse at the start of the next
PFC power cycle.
7
ML4801
FUNCTIONAL DESCRIPTION
(Continued)
Overvoltage Protection
The OVP comparator serves to protect the power circuit
from being subjected to excessive voltages if the load
should suddenly change. A resistor divider from the high
voltage DC output of the PFC is fed to VFB. When the
voltage on VFB exceeds 2.75V, the PFC output driver is
shut down. The PWM section will continue to operate. The
OVP comparator has 250mV of hysteresis, and the PFC
will not restart until the voltage at VFB drops below 2.5V.
The OVP trip level should be set at a level where the
active and passive external power components and the
ML4801 are within their safe operating voltages, but not
so low as to interfere with the regulator operation of the
boost voltage regulation loop.
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates the proper compensation of the two
transconductance error amplifiers. Figure 2 shows the
types of compensation networks most commonly used for
the voltage and current error amplifiers, along with their
respective return points. The current loop compensation is
returned to VREF to produce a soft-start characteristic on
the PFC: as the reference voltage comes up from zero
volts, it creates a differentiated voltage on IEAO which
prevents the PFC from immediately demanding a full duty
cycle on its boost converter.
There are two major concerns when compensating the
voltage loop error amplifier; stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier’s
open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest
anticipated international power frequency). Rapid
perturbations in line or load conditions will cause the
input to the voltage error amplifier (VFB) to deviate from
its 2.5V (nominal) value. If this happens, the
transconductance of the voltage error amplifier will
increase significantly. This increases the gain-bandwidth
product of the voltage loop, resulting in a much more
rapid voltage loop response to such perturbations than
would occur with a conventional linear gain
characteristic. The current amplifier compensation is
similar to that of the voltage error amplifier with the
exception of the choice of crossover frequency. The
crossover frequency of the current amplifier should be at
least 10 times that of the voltage amplifier, to prevent
interaction with the voltage loop. It should also be limited
to less than 1/6th that of the switching frequency, e.g.
16.7kHz for a 100kHz switching frequency.
There is a also a degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop
perturbations. However, the boost inductor will usually be
8
the dominant factor in overall current loop response.
Therefore, this contouring is significantly less marked than
that of the voltage error amplifier.
For more information on compensating the current and
voltage control loops, see Application Notes 33, 34, and
55. Application Note 16 also contains valuable
information for the design of this class of PFC.
Oscillator (RTCT)
The oscillator frequency is set by the values of RT and CT,
which determine the ramp and off-time of the ML4801's
master oscillator:
fOSC =
1
t RAMP + t DEADTIME
(2)
The deadtime of the oscillator is derived from the
following equation:
FG V
HV
t RAMP = C T ´ R T ´ ln
REF
REF
- 125
.
.
- 375
IJ
K
(3)
at VREF = 7.5V:
t RAMP = C T ´ R T ´ 0.51
The ramp of the oscillator may be determined using:
t DEADTIME =
25
. V
´ C T = 455 ´ C T
. mA
55
(4)
The deadtime is so small (tRAMP >> tDEADTIME) that the
VREF
GND
PFC
OUTPUT
16
1
IEAO
VEAO
VFB
15
VEA
IEA
+
2.5V
+
+
-
IAC
-
2
VRMS
4
GAIN
MODULATOR
ISENSE
3
Figure 2. Compensation Network Connections for the
Voltage and Current Error Amplifiers
ML4801
FUNCTIONAL DESCRIPTION
(Continued)
operating frequency can typically be approximated by:
fOSC =
1
t RAMP
(5)
EXAMPLE:
For the application circuit shown in the data sheet, with
the oscillator running at:
fOSC = 100kHz =
1
This voltage may be derived either by a current sensing
resistor or a current transformer.
Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 25µA
supplies the charging current for the capacitor, and startup of the PWM begins at 1.25V. Start-up delay can be
programmed by the following equation:
t RAMP
t RAMP = 0.51 ´ R T ´ C T = 1 ´ 10 - 5
C SS = t DELAY ×
25µA
. V
125
(6)
Solving for RT x CT yields 2 x 10-4. Selecting standard
components values, CT = 270pF, and RT = 36.5kΩ.
where CSS is the required soft start capacitance, and
tDELAY is the desired start-up delay.
PWM SECTION
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.
The PWM section of the ML4801 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, and that the PWM stage is
optimized for current-mode operation. In the ML4801, the
operating frequency of the PFC section is fixed at 1/2 of
the PWM's operating frequency. This is done through the
use of a 2:1 digital frequency divider ("T" flip-flop) linking
the two functional sections of the IC.
No voltage error amplifier is included in the PWM stage
of the ML4801, as this function is generally performed on
the output side of the PWM’s isolation boundary. To
facilitate the design of optocoupler feedback circuitry, an
offset has been built into the PWM’s RAMP 2 input which
allows VDC to command a zero percent duty cycle for
input voltages below 1.25V.
PWM Current Limit
The RAMP 2 pin provides a direct input to the cycle-bycycle current limiter for the PWM section. Should the
input voltage at this pin ever exceed 1.5V, the output of
the PWM will be disabled until the output flip-flop is reset
by the clock pulse at the start of the next PWM power
cycle.
VIN OK Comparator
The VIN OK comparator monitors the DC output of the
PFC and inhibits the PWM if this voltage on VFB is less
than its nominal 2.5V. Once this voltage reaches 2.5V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start
commences.
PWM Control (RAMP 2)
In addition to its PWM current limit function, RAMP 2 is
used as the sampling point for a voltage representing the
current in the primary of the PWM’s output transformer.
Solving for the minimum value of CSS:
C SS = 5ms ×
25µA
= 100nF
125
. V
Generating VCC
The ML4801 is a voltage-fed part. It requires an external
15V±10% or better Zener shunt voltage regulator, or some
other VCC regulator, to maintain the voltage supplied to
the part at 15V nominal. This allows a low power
dissipation while at the same time delivering 13V
nominal of gate drive at the PWM OUT and PFC OUT
outputs. If using a Zener diode, it is important to limit the
current through the Zener to avoid overheating or
destroying it. This can be easily done with a single resistor
in series with the Vcc pin, returned to a bias supply of
typically 18V to 20V. The resistor’s value must be chosen
to meet the operating current requirement of the ML4801
itself (8.5mA max.) plus the current required by the two
gate driver outputs.
EXAMPLE:
With a VBIAS of 20V, a VCC limit of 16.5V (max) and
driving a total gate charge of 110nC at 100kHz (1 IRF840
MOSFET and 2 IRF830 MOSFETs), the gate driver current
required is:
IGATEDRIVE = 100kHz ´ 110nC = 11mA
RBIAS =
20V - 16.5V
= 180Ω
7.5mA + 11mA
The ML4801 should be locally bypassed with a 10nF and
a 1µF ceramic capacitor. In most applications, an
electrolytic capacitor of between 33µF and 100µF is also
required across the part, both for filtering and as part of
the start-up bootstrap circuitry.
9
ML4801
LEADING/TRAILING MODULATION
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with
the modulating ramp. When the modulating ramp reaches
the level of the error amplifier output voltage, the switch
will be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 3 shows a typical trailing edge
control scheme.
In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 4
shows a leading edge control scheme.
SW2
L1
+
I2
I1
TYPICAL APPLICATIONS
Figure 9 is the application circuit for a complete 100W
power factor corrected power supply, designed using the
methods and general topology detailed in Application
Note 33.
I3
L1
I4
+
RL
VIN
SW1
DC
One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the
first stage is reduced. Calculation and evaluation have
shown that the 120Hz component of the PFC’s output
ripple voltage can be reduced by as much as 30% using
this method.
SW2
I2
I1
I4
VIN
RL
SW1
DC
RAMP
C1
I3
RAMP
C1
VEAO
VEAO
REF
U3
+
–EA
DFF
RAMP
OSC
U4
CLK
+
–
U1
TIME
RAMP
R
Q
D U2
Q
CLK
OSC
U4
TIME
Figure 3. Typical Trailing Edge Control Scheme
10
REF
VSW1
U3
+
–EA
CLK
VEAO
+
–
CMP
U1
DFF
TIME
VSW1
R
Q
D U2
Q
CLK
TIME
Figure 4. Leading/Trailing Edge Control Scheme
160
180
0
90
–160
µS
IVEAO (µA)
ML4801
0
1
3
2
4
0
5
0
1
3
2
VFB (V)
4
5
4
5
VFB (V)
Figure 5. IVEAO vs. VFB
Figure 6. gM of VOTA
200
500
160
K
µS
120
80
40
0
0
1
3
2
VFB (V)
Figure 7. gM of IOTA
4
5
0
0
1
2
3
VRMS (V)
Figure 8. K of Multiplier
11
ML4801
AC INPUT
85 TO 265VAC
F1
3.15A
C1
680nF
D1
8A, 600V
"FRED " Diode
L1
3mH
Q2
R17 IRF830
33Ω
Q1
IRF840
R2A
357kΩ
BR1
4A, 600V
C4
C5
10nF 100µF
C25
100nF
T1
R1A
249kΩ
R21
22Ω
R2B
357kΩ
15V
R1B
249kΩ
D12
1N5401
C12
20µF
R4
13kΩ
R14
33Ω
1N4745
16V
R12
27kΩ
ISENSE
VREF
VRMS
VCC
R20
1.5Ω
C23
R26
100nF
10kΩ
R7B
178kΩ
TL431
C15
10nF
PFC OUT
C16
1µF
C13
100nF
C14
1µF
D8
1N5818
GND
RTCT
RAMP 1
RAMP 2
R11
768kΩ
C9
10nF
C8
100nF
D10
1N5818
ML4801
1nF
R6
36.5kΩ
20kΩ
R10
6.2kΩ
C17
220pF
C11
10nF
470pF
Figure 9. 100W Power Factor Corrected Power Supply
12
R8
2.37kΩ
C31
1nF
R22
8.66kΩ
R25
2.26kΩ
PWM OUT
VDC
C18
270pF
R18
220Ω
R23
1.5kΩ
VFB
SS
60kΩ
C22
4.7µF
10kΩ
VDC
IAC
C19
220nF
Q3
IRF830
R19
220Ω
C6
1µF
12VDC
RTN
R7A
178kΩ
IEAO
R5
300mΩ
1W
C21
1800µF
C24
1µF
R24
1.2kΩ
C7
220pF
C2
470nF
L2
D11
MBR2545CT 15µH
D6
BYV26C
C20
1µF
D3
BYV26C
R28
180Ω
C30
47µF
T2
R15
3Ω
R3
75kΩ
D13
1N5401
D7
16V
R30
4.7kΩ
R27
82kΩ
C3
100nF
D5
BYV26C
L1: Premier Magnetics #TSD-734
L2: 15µH, 10A DC
T1: Premier Magnetics #PMGD- 03
T2: Premier Magnetics #TSD-1048
Premier Magnetics: (714) 362-4211
ML4801
PHYSICAL DIMENSIONS
inches (millimeters)
Package: P16
16-Pin PDIP
0.740 - 0.760
(18.79 - 19.31)
16
0.240 - 0.260 0.295 - 0.325
(6.09 - 6.61) (7.49 - 8.26)
PIN 1 ID
1
0.02 MIN
(0.50 MIN)
(4 PLACES)
0.100 BSC
(2.54 BSC)
0.055 - 0.065
(1.40 - 1.65)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
SEATING PLANE
0.016 - 0.022
(0.40 - 0.56)
0º - 15º
0.008 - 0.012
(0.20 - 0.31)
Package: S16N
16-Pin Narrow SOIC
0.386 - 0.396
(9.80 - 10.06)
16
0.148 - 0.158 0.228 - 0.244
(3.76 - 4.01) (5.79 - 6.20)
PIN 1 ID
1
0.017 - 0.027
(0.43 - 0.69)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.059 - 0.069
(1.49 - 1.75)
0º - 8º
0.055 - 0.061
(1.40 - 1.55)
0.012 - 0.020
(0.30 - 0.51)
SEATING PLANE
0.004 - 0.010
(0.10 - 0.26)
0.015 - 0.035
(0.38 - 0.89)
0.006 - 0.010
(0.15 - 0.26)
15
ML4801
ORDERING INFORMATION
© Micro Linear 1998.
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML4801CP
ML4801CS
0°C to 70°C
0°C to 70°C
16-Pin Plastic DIP (P16)
16-Pin Narrow SOIC (S16N)
ML4801IP
ML4801IS
–40°C to 85°C
–40°C to 85°C
16-Pin Plastic DIP (P16)
16-Pin Narrow SOIC (S16N)
is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502;
5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897;
5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669;
5,825,165; 5,825,223; 5,838,723. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability
arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits
contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits
infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult
with appropriate legal counsel before deciding on a particular application.
14
2092 Concourse Drive
San Jose, CA 95131
Tel: (408) 433-5200
Fax: (408) 432-0295
www.microlinear.com
DS4801-01